Display panel and display apparatus

Abstract

The present disclosure relates to a display panel and a display apparatus, and to the field of display technology. The display panel comprises signal transmission structures; each signal transmission structure comprises a first signal line segment, an electrostatic discharge unit, and a second signal line segment which are connected in sequence; at least some of the electrostatic discharge units each comprise a signal distribution structure, a plurality of first transistors connected in parallel, and a plurality of second transistors connected in parallel; a first electrode of each first transistor is configured to load a first power supply voltage, and a second electrode and a gate electrode of each first transistor are electrically connected to the signal distribution structure; a first electrode and a gate electrode of each second transistor are configured to load a second power supply voltage, and a second electrode of each second transistor is electrically connected to the signal distribution structure; the first power supply voltage is greater than the second power supply voltage; the first signal line segment and the second signal line segment are both electrically connected to the signal distribution structure; each second signal line segment is at least partially located in a transistor layer. The display panel provided by the present disclosure has high electrostatic resistance.

Description

Display panel and display device

[0001] Cross-references

[0002] This disclosure claims priority to Chinese Patent Application No. 202411960181.2, filed on December 27, 2024, entitled “Display Panel and Display Device”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of display technology, and more specifically, to a display panel and a display device. Background Technology

[0004] With the development of display technology, display panels are being used more and more widely in daily life. During production and use, display panels frequently face the problem of electrostatic discharge (ESD) breakdown. Therefore, it is necessary to improve the anti-static capability of display panels.

[0005] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0006] The purpose of this disclosure is to overcome the shortcomings of the prior art and provide a display panel and display device to improve the antistatic performance of the display panel.

[0007] According to one aspect of this disclosure, a display panel is provided, including a transistor layer and a first source / drain metal layer sequentially stacked on one side of a substrate.

[0008] The display panel includes a signal transmission structure, which includes a first signal line segment, an electrostatic discharge unit, and a second signal line segment connected in sequence. The second signal line segment is located on the side of the electrostatic discharge unit closer to the display area.

[0009] At least a portion of the electrostatic discharge unit includes a signal distribution structure, a plurality of first transistors connected in parallel, and a plurality of second transistors connected in parallel. Both the first and second transistors are metal-oxide transistors. The first terminal of the first transistor is used to apply a first power supply voltage, and the second terminal and gate of the first transistor are electrically connected to the signal distribution structure. The first terminal and gate of the second transistor are used to apply a second power supply voltage, and the second terminal of the second transistor is electrically connected to the signal distribution structure. The first power supply voltage is greater than the second power supply voltage.

[0010] The first signal segment and the second signal segment are electrically connected to the signal distribution structure, and the second signal segment is at least partially located in the transistor layer.

[0011] In one exemplary embodiment of this disclosure, at least a portion of the electrostatic discharge unit includes a plurality of first transistor groups connected in parallel, each first transistor group including a plurality of first transistors with the same gate and connected in parallel;

[0012] At least a portion of the electrostatic discharge unit includes a plurality of parallel second transistor groups, each of the second transistor groups including a plurality of second transistors with the same gate and connected in parallel.

[0013] In one exemplary embodiment of this disclosure, the first transistor includes a plurality of sub-transistors connected in series; the second transistor includes a plurality of sub-transistors connected in series.

[0014] In one exemplary embodiment of this disclosure, the transistor layer includes at least one gate layer and at least one metal-oxide-semiconductor layer;

[0015] The signal transmission structure includes a first signal transmission structure for loading a column start signal or a clock signal to the gate drive circuit of the display panel; the second signal segment of the first signal transmission structure is at least partially located in the metal oxide semiconductor layer.

[0016] In an exemplary embodiment of this disclosure, the second signal segment of the first signal transmission structure includes a first sub-trace electrically connected to the signal distribution structure and a second sub-trace electrically connected to one end of the first sub-trace away from the signal distribution structure. The first sub-trace is located in the metal oxide semiconductor layer, and the second sub-trace is located in the gate layer.

[0017] In one exemplary embodiment of this disclosure, one end of the signal distribution structure is electrically connected to the first signal line segment, and the other end is electrically connected to the second signal line segment;

[0018] The first transistors are arranged in pairs, with each pair of first transistors disposed on both sides of the signal distribution structure; the gate of the first transistor includes a first end for electrical connection with the signal distribution structure and a second end away from the first end; the display panel is provided with a first trace structure corresponding to at least one pair of first transistors, the second ends of the gates of the two first transistors of the first transistor pair are both electrically connected to the first trace structure, and the first trace structure overlaps with the signal distribution structure.

[0019] And / or, the second transistors are arranged in pairs, with each pair of second transistors disposed on both sides of the signal distribution structure; the gate of the second transistor includes a first end for electrical connection to a second power supply voltage terminal and a second end away from the first end; the display panel is provided with a second trace structure corresponding to at least one pair of second transistors, the second ends of the gates of the two second transistors of the second transistor pair are both electrically connected to the second trace structure, and the second trace structure overlaps with the signal distribution structure.

[0020] In one exemplary embodiment of this disclosure, the signal transmission structure includes a second signal transmission structure, wherein a first signal segment of the second signal transmission structure is electrically connected to a pin of a flexible printed circuit board.

[0021] The electrostatic discharge unit of the second signal transmission structure further includes a third wiring structure electrically connected to the first wiring structure, wherein the orthographic projection of the third wiring structure on the substrate is located within the orthographic projection of the signal distribution structure on the substrate.

[0022] And / or, the electrostatic discharge unit of the second signal transmission structure further includes a fourth trace structure electrically connected to the second trace structure, wherein the orthographic projection of the fourth trace structure on the substrate is located within the orthographic projection of the signal distribution structure on the substrate.

[0023] In an exemplary embodiment of this disclosure, the size of the third trace structure is not less than the length of the channel region of the first transistor along the length direction of the channel region of the first transistor; and the size of the third trace structure is not less than the width of the channel region of the first transistor along the width direction of the channel region of the first transistor.

[0024] And / or, along the length direction of the channel region of the second transistor, the size of the fourth trace structure is not less than the length of the channel region of the second transistor; along the width direction of the channel region of the second transistor, the size of the fourth trace structure is not less than the width of the channel region of the second transistor.

[0025] In one exemplary embodiment of this disclosure, in the electrostatic discharge unit of the second signal transmission structure, the total width of the channel region of the first transistor is not less than 8 times the length of the channel region of the first transistor;

[0026] And / or, in the electrostatic discharge unit of the second signal transmission structure, the total width of the channel region of the second transistor is not less than 8 times the length of the channel region of the second transistor.

[0027] In one exemplary embodiment of this disclosure, the transistor layer includes a metal oxide semiconductor layer, and the active layers of the first transistor and the second transistor are both located in the metal oxide semiconductor layer.

[0028] The metal oxide semiconductor layer is provided with a fifth wiring structure that corresponds one-to-one with the first transistor and is conductive; the gate of the first transistor is electrically connected to the signal distribution structure through the corresponding fifth wiring structure.

[0029] And / or, the metal oxide semiconductor layer is provided with a sixth trace structure that corresponds one-to-one with the second transistor and is conductive; the gate of the second transistor is electrically connected to the second power supply voltage terminal through the corresponding sixth trace structure.

[0030] In one exemplary embodiment of this disclosure, the signal transmission structure includes a third signal transmission structure, wherein a first signal segment of the third signal transmission structure is electrically connected to an electrical detection pad;

[0031] In the electrostatic discharge unit of the third signal transmission structure, the total width of the channel region of the first transistor is not less than 18 times the length of the channel region of the first transistor.

[0032] And / or, in the electrostatic discharge unit of the third signal transmission structure, the total width of the channel region of the second transistor is not less than 18 times the length of the channel region of the second transistor.

[0033] According to another aspect of this disclosure, a display device is provided, including the aforementioned display panel.

[0034] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0035] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0036] Figure 1 is a schematic diagram of the structure of the display panel in one embodiment of this disclosure.

[0037] Figure 2 is a schematic diagram of the film layer structure of the display panel in one embodiment of this disclosure.

[0038] Figure 3 is a partial structural schematic diagram of the display panel in one embodiment of this disclosure.

[0039] Figure 4 is a partial structural diagram of the display panel in one embodiment of this disclosure.

[0040] Figure 5 is a schematic diagram of the electrostatic discharge unit in one embodiment of this disclosure.

[0041] Figure 6 is a schematic diagram of the principle of the first electrostatic discharge unit in one embodiment of this disclosure.

[0042] Figure 7 is a schematic diagram of the principle of the second electrostatic discharge unit in one embodiment of this disclosure.

[0043] Figure 8 is a schematic diagram of the principle of the third electrostatic discharge unit in one embodiment of this disclosure.

[0044] Figure 9 is a schematic diagram of the principle of the fourth electrostatic discharge unit in one embodiment of this disclosure.

[0045] Figure 10 is a schematic diagram of the structure of the metal oxide semiconductor layer in the first electrostatic discharge unit in one embodiment of the present disclosure.

[0046] Figure 11 is a schematic diagram of the structure of the third gate layer in the first electrostatic discharge unit in one embodiment of the present disclosure.

[0047] Figure 12 is a schematic diagram of the structure of the first source / drain metal layer in the first electrostatic discharge unit in one embodiment of the present disclosure.

[0048] Figure 13 is a schematic diagram of the structure of the second gate layer, the metal oxide semiconductor layer, and the third gate layer in the first electrostatic discharge unit in one embodiment of the present disclosure.

[0049] Figure 14 is a schematic diagram of the structure of the second gate layer, the metal oxide semiconductor layer, the third gate layer, and the first source / drain metal layer in the first electrostatic discharge unit in one embodiment of the present disclosure.

[0050] Figure 15 is a schematic diagram of the structure of the metal oxide semiconductor layer in the second electrostatic discharge unit in one embodiment of the present disclosure.

[0051] Figure 16 is a schematic diagram of the structure of the metal oxide semiconductor layer and the third gate layer in the second electrostatic discharge unit in one embodiment of the present disclosure.

[0052] Figure 17 is a schematic diagram of the structure of the metal oxide semiconductor layer in the third electrostatic discharge unit in one embodiment of the present disclosure.

[0053] Figure 18 is a schematic diagram of the structure of the third gate layer in the third electrostatic discharge unit in one embodiment of the present disclosure.

[0054] Figure 19 is a schematic diagram of the structure of the first source / drain metal layer in the third electrostatic discharge unit in one embodiment of the present disclosure.

[0055] Figure 20 is a schematic diagram of the structure of the metal oxide semiconductor layer and the third gate layer in the third electrostatic discharge unit in one embodiment of the present disclosure.

[0056] Figure 21 is a schematic diagram of the structure of the metal oxide semiconductor layer and the second gate layer in the third electrostatic discharge unit in one embodiment of the present disclosure.

[0057] Figure 22 is a schematic diagram of the structure of the second gate layer, the metal oxide semiconductor layer, the third gate layer, and the first source / drain metal layer in the third electrostatic discharge unit in one embodiment of the present disclosure.

[0058] Figure 23 is a schematic diagram of the structure of the metal oxide semiconductor layer and the third gate layer in the fourth electrostatic discharge unit in one embodiment of the present disclosure. Detailed Implementation

[0059] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0060] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” and “third,” etc., are used only as markers and are not a limitation on the number of objects.

[0061] This disclosure provides a display panel PNL, as shown in FIG1. ​​The display panel PNL includes a display area AA and a peripheral area BB located on at least one side of the display area AA, for example, the peripheral area BB surrounds the display area AA. In the display area AA, the display panel PNL is provided with an array of display units UU, each display unit UU including a sub-pixel PX and a pixel driving circuit PDC for driving the sub-pixel PX. The display panel PNL does not provide display units UU in the peripheral area BB, or the provided display units UU are not used for displaying images. Referring to FIG1, the display panel PNL is provided with a plurality of first scan signal traces GLGPL extending along the row direction DH in the display area AA, each first scan signal trace GL corresponding to a row of display units. The pixel driving circuit PDC of each display unit UU in a row of display units is electrically connected to the corresponding first scan signal trace GL. The display panel PNL is also provided with a plurality of data traces DL extending along the column direction DV in the display area AA, each data trace DL corresponding to a column of display units. Each display unit UU in the display unit column has its pixel drive circuit (PDC) electrically connected to its corresponding data trace (DL). Thus, each display unit UU's pixel drive circuit (PDC) is connected to a first scan signal trace (GL) and a data trace (DL). When a scan signal is applied to the first scan signal trace (GL), the driving voltage applied to the data trace (DL) can be written into the pixel drive circuit (PDC), allowing the pixel drive circuit (PDC) to control the brightness of the sub-pixel (PX) based on the written driving voltage.

[0062] Optionally, the pixel driving circuit PDC includes at least a data writing transistor, a driving transistor, and a storage capacitor. The gate of the driving transistor can be electrically connected to one electrode plate of the storage capacitor. The source of the data writing transistor can be electrically connected to the data trace DL, and the gate of the data writing transistor can be electrically connected to the first scan signal trace GL. The pixel driving circuit PDC is configured such that when a scan signal is applied to the first scan signal trace GL, the data writing transistor is turned on, thereby causing the driving voltage on the data trace DL to be written to the gate of the driving transistor and the storage capacitor. When the data writing transistor is turned off, the driving voltage can be maintained by the storage capacitor. The driving transistor can output a driving current to drive the sub-pixel PX to emit light under the control of the voltage on its gate. It is understood that the pixel driving circuit PDC of the present disclosure embodiment may also include other transistors or capacitors to give the pixel driving circuit PDC better driving performance. For example, the pixel driving circuit PDC can be a 7T1C (7 thin film transistors and one storage capacitor), an 8T1C (8 thin film transistors and one storage capacitor), or a pixel driving circuit PDC with other architectures.

[0063] In this embodiment of the disclosure, the sub-pixels PX in the display panel PNL are current-driven self-emissive elements, such as thin-film self-emissive elements. For example, the sub-pixels PX are OLED, PLED, QLED, etc. Furthermore, the sub-pixels PX located in the display area AA include sub-pixels PX of various colors. For example, the sub-pixels PX include red sub-pixels for emitting red light, green sub-pixels for emitting green light, and blue sub-pixels for emitting blue light. It is understood that in other embodiments of this disclosure, the sub-pixels PX in the display area AA may also be of only one color, or may have sub-pixels PX of other colors (e.g., yellow sub-pixels for emitting yellow light, cyan sub-pixels for emitting cyan light, white sub-pixels for emitting white light, etc.).

[0064] In one embodiment of this disclosure, referring to FIG2, the display panel PNL may include a substrate SBT, a driving layer DRL, and a pixel layer PXL stacked sequentially. The pixel layer PXL is provided with sub-pixels PX, and the driving layer DRL is provided with a pixel driving circuit PDC for driving the sub-pixels PX. Each sub-pixel PX can emit light under the drive of the pixel driving circuit PDC to display an image.

[0065] Optionally, the substrate SBT can be an inorganic material substrate or an organic material substrate; of course, it can also be a composite substrate formed by stacking inorganic and organic material substrates. For example, in some embodiments of this disclosure, the material of the substrate SBT can be glass materials such as soda-lime glass, quartz glass, and sapphire glass. In other embodiments of this disclosure, the material of the substrate SBT can be polymethyl methacrylate, polyvinyl alcohol, polyvinylphenol, polyethersulfone, polyimide, polyamide, polyacetal, polycarbonate, polyethylene terephthalate, polyethylene naphthalate, or combinations thereof. In other embodiments of this disclosure, the substrate SBT can also be a flexible substrate, for example, the material of the substrate SBT may include polyimide.

[0066] Optionally, in the driving layer DRL, any pixel driving circuit PDC may include a thin-film transistor and a storage capacitor. Further, the thin-film transistor may be selected from top-gate, bottom-gate, or dual-gate thin-film transistors; the material of the active layer of the thin-film transistor may be amorphous silicon semiconductor material, low-temperature polycrystalline silicon semiconductor material, metal oxide semiconductor material, organic semiconductor material, carbon nanotube semiconductor material, or other types of semiconductor material; the thin-film transistor may be an N-type or P-type thin-film transistor.

[0067] It is understood that any two transistors in a pixel driving circuit can be of the same or different types. For example, in some embodiments, some transistors in a pixel driving circuit can be N-type transistors and some transistors can be P-type transistors. Further exemplarily, in other embodiments, in a pixel driving circuit, the active layer material of some transistors can be low-temperature polycrystalline silicon semiconductor material, and the active layer material of some transistors can be metal-oxide-semiconductor material.

[0068] Optionally, the driving layer DRL may include a semiconductor layer, a gate insulating layer, a gate layer, an interlayer dielectric, a source / drain metal layer, a planarization layer, etc., stacked between the substrate SBT and the pixel layer PXL. Each thin-film transistor and storage capacitor can be formed from the semiconductor layer, gate insulating layer, gate layer, interlayer dielectric, source / drain metal layer, etc. The positional relationship of each layer can be determined according to the thin-film transistor's layer structure. Further, the semiconductor layer can be used to form the channel region of the transistor, and can also be used to form partial traces or conductive structures if necessary. The gate layer can be used to form one or more gate layer traces such as scan signal traces, reset signal traces, and light emission control signal traces, or it can be used to form the gate of the transistor, or it can be used to form part or all of the electrode plates of the storage capacitor. The source / drain metal layer can be used to form data traces, power supply voltage traces, etc., or it can be used to form part of the electrode plates of the storage capacitor. Of course, in other embodiments of this disclosure, the driving layer DRL may also include other layers as needed, such as a light-shielding layer located between the semiconductor layer and the substrate SBT. Depending on the requirements, any one of the aforementioned semiconductor layers, gate layers, source / drain metal layers, etc., can be multiple layers. For example, the driving layer DRL may include two different semiconductor layers, or two or three source / drain metal layers, or two or three gate layers. Correspondingly, the insulating layers (e.g., gate insulating layer, interlayer dielectric layer, planarization layer, etc.) in the driving layer DRL can be adaptively increased or decreased, or new insulating layers can be added as needed. In the embodiments of this disclosure, the driving layer DRL includes at least a metal oxide semiconductor layer OSCL.

[0069] Optionally, the driving layer DRL may also include a passivation layer, which may be disposed on the surface of the source / drain metal layer away from the substrate SBT, in order to protect the source / drain metal layer.

[0070] As an example, referring to Figure 2, the driving layer DRL may include a metal light-shielding layer BSM, a first inorganic buffer layer BUF1, a low-temperature polysilicon semiconductor layer PSCL, a first gate insulating layer GI1, a first gate layer GT1, a second inorganic buffer layer BUF2, a second gate layer GT2, a second gate insulating layer GI2, a metal oxide semiconductor layer OSCL, a third gate insulating layer GI3, a third gate layer GT3, a first source / drain metal layer SD1, a first planarization layer PLN1, a second source / drain metal layer SD2, and a second planarization layer PLN2, stacked sequentially.

[0071] As another example, the driving layer DRL may also include a third source / drain metal layer SD3 and a third planarization layer PLN3 located on the side of the second planarization layer PLN2 away from the substrate SBT.

[0072] Referring to Figure 2, the light-emitting elements in the pixel layer PXL are thin-film light-emitting elements, which may include two electrodes stacked together and light-emitting functional units sandwiched between the two electrodes. For example, referring to Figure 2, the pixel layer PXL may include a pixel electrode layer PEL, a light-emitting functional layer EFL, and a common electrode layer COML stacked sequentially. The pixel electrode layer PEL has multiple pixel electrodes in the display area of ​​the display panel; the portion of the light-emitting functional layer EFL connected to the pixel electrodes serves as the light-emitting functional unit of the light-emitting element; and the common electrode layer COML serves as the common electrode and is electrically connected to the light-emitting functional units of each light-emitting element.

[0073] Furthermore, the pixel layer PXL may also include a pixel definition layer PDL located between the pixel electrode layer PEL and the light-emitting functional layer EFL. The pixel definition layer PDL has multiple through-holes that correspond one-to-one with the multiple pixel electrodes, with each pixel opening exposing at least a portion of the corresponding pixel electrode. For example, the pixel definition layer PDL covers the edge of the pixel electrode and exposes at least a portion of the internal region of the pixel electrode, so that the pixel definition layer PDL can effectively define the actual effective region of the pixel electrode (the region directly connected to the light-emitting functional unit), thereby defining the light-emitting region and light-emitting area of ​​the light-emitting element. The light-emitting functional layer EFL at least covers the pixel electrode exposed by the pixel definition layer PDL. The common electrode layer COML may cover the light-emitting functional layer EFL in the display area. The pixel electrodes and the common electrode layer COML provide charge carriers such as electrons and holes to the light-emitting functional layer EFL, causing the light-emitting functional layer EFL to emit light. The portion of the light-emitting functional layer EFL located between the pixel electrodes and the common electrode layer COML can serve as a light-emitting functional unit. The pixel electrodes, the common electrode layer COML, and the light-emitting functional unit form a light-emitting element. In this design, one of the pixel electrode and the common electrode layer COML serves as the anode of the light-emitting element, and the other serves as the cathode of the light-emitting element.

[0074] Optionally, referring to Figure 2, the display panel PNL may also have a thin-film encapsulation layer (TFE). The TFE can be disposed on the surface of the pixel layer PXL away from the substrate SBT. In one example, the TFE may include alternating layers of inorganic and organic encapsulation layers. The inorganic encapsulation layer can effectively block external moisture and oxygen, preventing water and oxygen from invading the pixel layer PXL and causing material aging in the pixel layer PXL. Optionally, the edge of the inorganic encapsulation layer can be located in the peripheral area. The organic encapsulation layer is located between two adjacent inorganic encapsulation layers to achieve planarization and reduce stress between the inorganic encapsulation layers. The edge of the organic encapsulation layer can be located between the edge of the display area and the edge of the inorganic encapsulation layer.

[0075] Referring to Figure 3, the display panel PNL has electrostatic discharge units (DUs) in its peripheral area BB. In some cases, these ESD units (DUs) can form a ring, which is referred to as an ESD ring. Furthermore, these ESD structures are located near the ends of the display panel PNL, especially near the bonding area of ​​the display panel PNL, in order to provide electrostatic protection against externally input signals.

[0076] Referring to Figure 3, the display panel PNL may have pins or pads at one end of the peripheral area BB. For example, P01 to P05 are pins for loading different signals, such as pins for loading STV signals, clock signals, flexible printed circuit board (FPC) signals, and electrical detection signals, respectively. These pins or pads can be electrically connected to signal sources such as chips, circuit boards, or probes, for example, through bonding or contact connections. In the example of Figure 4, these pins or pads include, but are not limited to, electrical detection pads for electrical detection, gate drive circuit pins for loading drive signals to the gate drive circuit of the display panel PNL, flexible printed circuit board (FPC) pins for bonding with the flexible circuit board, and drive pins for bonding with the source drive chip. It is understood that in some examples of this disclosure, the display panel PNL may only have one or more of the above-mentioned example pins / pads, or other pins or pads may be provided as needed.

[0077] Referring to Figure 4, these pins or pads can load signals to the target circuit through the signal transmission structure SCH. The signal transmission structure SCH includes a first signal segment LA, an electrostatic discharge unit DU, and a second signal segment LB connected in sequence. The first signal segment LA can be electrically connected to the pin or pad, for example, directly. The second signal segment LB is located on the side of the electrostatic discharge unit DU closer to the display area AA, and is used to load signals to the peripheral area BB or the display area AA.

[0078] In related technologies, both the first signal segment LA and the second signal segment LB are disposed on the source / drain metal layer to have low resistance. However, the inventors have found that the low resistance of the second signal segment LB results in insufficient hysteresis of electrostatic pulses on the pins or pads, and the electrostatic discharge unit DU cannot perform electrostatic discharge in a timely and sufficient manner; this leads to a greater risk of electrostatic breakdown of the display panel PNL caused by electrostatic pulses.

[0079] Therefore, this disclosure provides a signal transmission structure SCH. Referring to FIG4, the display panel PNL includes a signal transmission structure SCH, which includes a first signal segment LA, an electrostatic discharge unit DU, and a second signal segment LB connected in sequence. Referring to FIG5-FIG9, at least a portion of the electrostatic discharge unit DU includes a signal distribution structure MA, a plurality of parallel first transistors T1, and a plurality of parallel second transistors T2, wherein the first transistors T1 and T2 are both metal-oxide transistors. The first terminal of the first transistor T1 is used to apply a first power supply voltage VG1, and the second terminal and gate of the first transistor T1 are electrically connected to the signal distribution structure MA; the first terminal and gate of the second transistor T2 are used to apply a second power supply voltage VG2, and the second terminal of the second transistor T2 is electrically connected to the signal distribution structure MA; the first power supply voltage VG1 is greater than the second power supply voltage VG2; the first signal segment LA and the second signal segment LB are respectively electrically connected to the signal distribution structure MA, and the second signal segment LB is at least partially located in the transistor layer TL.

[0080] In this embodiment, the electrostatic discharge unit DU includes multiple first transistors T1 connected in parallel, thus achieving a larger discharge rate for high-level static electricity. The electrostatic discharge unit DU also includes multiple second transistors T2 connected in parallel, thus achieving a larger discharge rate for low-level static electricity. Although both the first transistors T1 and the second transistors T2 in this embodiment are metal-oxide transistors (MOS), the parallel connection of multiple transistors overcomes the potential problem of slow electrostatic discharge rate. Furthermore, the stability and uniformity of MOS transistors improve the uniformity of the electrostatic discharge unit DU. More importantly, the use of MOS transistors for the first transistors T1 and the second transistors T2 results in lower leakage current, ensuring low loss in the signal transmission structure SCH during normal signal transmission. This guarantees signal transmission accuracy and low delay while reducing ESD power consumption. Additionally, when one transistor fails due to electrostatic breakdown, the other parallel transistors ensure the continued operation of the electrostatic discharge unit DU, improving the reliability of the signal transmission structure SCH.

[0081] In this embodiment, the second signal segment LB is at least partially disposed on the transistor layer TL. Each film layer in the transistor layer TL, such as a semiconductor layer or a gate layer, has a sheet resistance greater than that of the source / drain metal layers. Therefore, partially disposing the second signal segment LB on the transistor layer TL is equivalent to adding a blocking resistor to the output of the electrostatic discharge unit DU. This blocking resistor can effectively reduce the voltage amplitude of the electrostatic pulse to reduce the impact on the downstream circuitry of the signal transmission structure SCH; on the other hand, it can extend the electrostatic discharge time of the electrostatic discharge unit DU, allowing the electrostatic discharge unit DU to perform electrostatic discharge more fully.

[0082] In one embodiment of this disclosure, referring to Figures 6-9, in at least a portion of the electrostatic discharge unit DU, the first transistor T1 includes a plurality of first sub-transistors ST1 connected in series. Thus, the series connection of the plurality of first sub-transistors ST1 results in a smaller leakage current for the first transistor T1, further reducing ESD power consumption. For example, in the example of Figures 6-9, the first transistor T1 includes two first sub-transistors ST1 connected in series with a common source layer, and the metal oxide material between the channel regions of the two first sub-transistors ST1 is conductive.

[0083] In one embodiment of this disclosure, referring to Figures 8 and 9, at least a portion of the electrostatic discharge unit DU includes a plurality of first transistor groups TIS connected in parallel, each first transistor group including a plurality of first transistors T1 connected in parallel with the same gate; thus, the plurality of first transistors T1 are arranged in parallel with the same gate to form a first transistor group, which is beneficial to improve the space utilization of the electrostatic discharge unit DU, so as to provide as many first transistors T1 as possible or to make the total length of the channel region of the first transistors T1 longer.

[0084] Referring to Figure 7, in one example, each first transistor group includes two first transistors T1 connected in parallel and with a common gate, and each first transistor T1 includes two first sub-transistors ST1 connected in series.

[0085] Referring to Figure 8, in another example, each first transistor group includes two parallel and common-gate first transistors T1, and each first transistor T1 includes two series-connected first sub-transistors ST1.

[0086] Referring to Figure 9, in one example, each first transistor group includes four first transistors T1 connected in parallel and with a common gate, and each first transistor T1 includes two first sub-transistors ST1 connected in series.

[0087] In one embodiment of this disclosure, referring to Figures 6-9, in at least a portion of the electrostatic discharge unit DU, the second transistor T2 includes a plurality of second sub-transistors ST2 connected in series. Thus, the series connection of the plurality of second sub-transistors ST2 results in a smaller leakage current in the second transistor T2, further reducing ESD power consumption. For example, in the example of Figures 6-9, the second transistor T2 includes two second sub-transistors ST2 connected in series with a common source layer, and the metal oxide material between the channel regions of the two second sub-transistors ST2 is conductive.

[0088] In one embodiment of this disclosure, referring to Figures 8 and 9, at least a portion of the electrostatic discharge unit DU includes a plurality of parallel-connected second transistor groups T2S, each second transistor group including a plurality of second transistors T2 connected in parallel with the same gate; thus, the plurality of second transistors T2 are arranged in parallel with the same gate to form a second transistor group, which is beneficial to improve the space utilization of the electrostatic discharge unit DU, so as to provide as many second transistors T2 as possible or to make the total length of the channel region of the second transistors T2 longer.

[0089] Referring to Figure 7, in one example, each second transistor group includes two parallel and common-gate second transistors T2, and each second transistor T2 includes two series-connected second sub-transistors ST2.

[0090] Referring to Figure 8, in another example, each second transistor group includes two parallel and common-gate second transistors T2, and each second transistor T2 includes two series-connected second sub-transistors ST2.

[0091] Referring to Figure 9, in one example, each second transistor group includes four parallel and common-gate second transistors T2, and each second transistor T2 includes two series-connected second sub-transistors ST2.

[0092] In some embodiments of this disclosure, each electrostatic discharge unit DU located in the ESD ring includes a plurality of first transistors T1 connected in parallel and a plurality of second transistors T2 connected in parallel.

[0093] In some other embodiments of this disclosure, the partial electrostatic discharge unit DU located in the ESD ring includes a plurality of first transistors T1 connected in parallel and a plurality of second transistors T2 connected in parallel; the partial electrostatic discharge unit DU located in the ESD ring may include only a single first transistor T1 and a single second transistor T2, for example, including a first transistor T1 formed by two sub-transistors connected in series and a second transistor T2 formed by two sub-transistors connected in series.

[0094] As an example, some signal transmission structures SCH are used to transmit data voltages. These signal transmission structures SCH can be configured with only a first transistor T1 formed by two sub-transistors connected in series and a second transistor T2 formed by two sub-transistors connected in series.

[0095] In one embodiment of this disclosure, referring to FIG4, the transistor layer TL includes at least one gate layer and at least one metal oxide semiconductor layer OSCL; the signal transmission structure SCH includes a first signal transmission structure SCH1 for loading a column start signal (STV signal or clock signal) to the gate drive circuit of the display panel PNL; the second signal segment LB of the first signal transmission structure SCH1 is at least partially located in the metal oxide semiconductor layer OSCL.

[0096] For example, the second signal segment LB of the first signal transmission structure SCH1 includes a first sub-trace LB1 electrically connected to the signal distribution structure MA and a second sub-trace LB2 electrically connected to one end of the first sub-trace LB1 away from the signal distribution structure MA. The first sub-trace LB1 is located in the metal oxide semiconductor layer OSCL, and the second sub-trace LB2 is located in the gate layer.

[0097] Taking Figure 4 as an example, the display panel PNL has a first gate layer GT1, a second gate layer GT2, and a third gate layer GT3 (not shown in Figure 4) on the transistor layer TL, and a metal oxide semiconductor layer OSCL. The first signal transmission structure SCH1 includes a first signal segment LA, an electrostatic discharge unit DU, a first sub-trace LB1, and a second sub-trace LB2 arranged sequentially. The first signal segment LA is located on the first source / drain metal layer SD1, the first sub-trace LB1 is located on the metal oxide semiconductor layer OSCL, and the second sub-trace LB2 is located on the first gate layer GT1. Although the first sub-trace LB1 is conductive, its sheet resistance is still greater than that of the first source / drain metal layer SD1. The arrangement of the first sub-trace LB1 can significantly increase the resistance of the output terminal of the electrostatic discharge unit DU, thereby blocking electrostatic pulses. Furthermore, referring to Figure 4, the first sub-trace LB1 is bent to have a maximum length, further increasing its resistance.

[0098] In this embodiment, the column start signal and clock signal applied to the gate drive circuit are crucial for the normal display of the display panel PNL; compared to other signals, the damage caused by electrostatic discharge (ESD) breakdown is greater. Therefore, the first signal transmission structure SCH1 provides stronger ESD protection by specifically designating the first sub-trace LB1. It is understandable that when another signal also requires further enhancement of its ESD protection, the signal transmission structure SCH of that signal can also adopt the structure of the first signal transmission structure SCH1.

[0099] In the example of Figure 4, the second sub-trace LB2 is disposed on the first gate layer GT1. In other examples of this disclosure, the second sub-trace LB2 may also be disposed on the second gate layer GT2 or the third gate layer GT3.

[0100] In some embodiments of this disclosure, referring to Figures 5 to 9, in at least a portion of the electrostatic discharge unit DU, one end of the signal distribution structure MA is electrically connected to the first signal line segment LA, and the other end is electrically connected to the second signal line segment LB.

[0101] In one example, referring to Figures 20 and 22, the first transistors T1 are arranged in pairs, with each pair of first transistors T1 disposed on both sides of the signal distribution structure MA; the gate of the first transistor T1 includes a first end for electrical connection with the signal distribution structure MA and a second end away from the first end; the display panel PNL is provided with a first trace structure HL1 corresponding to at least one pair of first transistors T1P, the second ends of the gates of the two first transistors T1 of the first transistor pair T1P are both electrically connected to the first trace structure HL1, and the first trace structure HL1 overlaps with the signal distribution structure MA.

[0102] On one hand, the gates of the first transistor pair T1P on both sides of the signal distribution structure MA are electrically connected to each other. This allows the gates of the first transistor pair T1P and the signal distribution structure MA to be arranged in parallel with multiple electrical connection points. This can improve the boost or buck speed of the gate of the first transistor T1P when an electrostatic pulse arrives. Moreover, the two gates of the first transistor pair T1P serve as backups for each other, improving the reliability of the first transistor to T1P. On the other hand, the first trace structure HL1 overlaps with the signal distribution structure MA, forming a coupling capacitor between the first trace structure HL1 and the signal distribution structure MA. When an electrostatic pulse arrives, the electrostatic pulse can charge or discharge this coupling capacitor, thereby blocking the impact of the electrostatic pulse on the downstream circuit of the signal transmission structure SCH.

[0103] In one example, referring to Figure 20, the first wiring structure HL1 may include a single wiring structure to which the gates of each first sub-transistor ST1 of the first transistor T1 are connected. For example, the gates of the first sub-transistors ST1 of the first transistor T1 extend in the column direction DV, and the first wiring structure HL1 extends in the row direction DH; the first wiring structure HL1 is connected to the ends of the gates of each first sub-transistor ST1. Further, the first wiring structure HL1 and the gates of each first sub-transistor ST1 are disposed on the same layer, for example, both on the third gate layer GT3.

[0104] In another example, referring to Figures 11 and 13, the first wiring structure HL1 may include multiple wiring structures corresponding one-to-one with the gates of the respective first sub-transistors ST1 of the first transistor T1. The two ends of each wiring structure are electrically connected to the gates of the first sub-transistors ST1 of the two first transistors T1, respectively. For example, the extension direction of the gate of the first sub-transistor ST1 of the first transistor T1 is the row direction DH, and the extension direction of the first wiring structure HL1 is also the row direction DH. The gate of one first sub-transistor ST1, one wiring structure, and the gate of the other first sub-transistor ST1 are connected sequentially. Further, the first wiring structure HL1 and the gates of the first sub-transistors ST1 are disposed on the same layer, for example, all on the third gate layer GT3.

[0105] In one example, referring to Figures 20 and 22, the second transistors T2 are arranged in pairs, with each pair of second transistors T2 positioned on opposite sides of the signal distribution structure MA. The gate of each second transistor T2 includes a first terminal for electrical connection to a second power supply voltage terminal and a second terminal away from the first terminal. The display panel PNL is provided with a second trace structure LL1 corresponding to at least one pair of second transistors T2P. The second terminals of the gates of both second transistors T2 in the pair of second transistors T2P are electrically connected to the second trace structure LL1, which overlaps with the signal distribution structure MA. This improves the reliability of the second transistors T2 and blocks electrostatic pulses.

[0106] In one example, in at least a portion of the electrostatic discharge unit DU, the first transistor T1 is arranged in pairs and the second transistor T2 is arranged in pairs. In other examples, in a portion of the electrostatic discharge unit DU, only the first transistor T1 may be arranged in pairs or only the second transistor T2 may be arranged in pairs.

[0107] In one example, the second wiring structure LL1 may include a single wiring structure to which the gates of each of the second subtransistors ST2 of the second transistor T2 are connected. For example, the gates of the second subtransistors ST2 of the second transistor T2 extend in the column direction DV, and the second wiring structure LL1 extends in the row direction DH; the second wiring structure LL1 is connected to the ends of the gates of each of the second subtransistors ST2. Further, the second wiring structure LL1 and the gates of each of the second subtransistors ST2 are disposed on the same layer, for example, on the third gate layer GT3.

[0108] In another example, the second wiring structure LL1 may include multiple wiring structures corresponding one-to-one with the gates of the respective second subtransistors ST2 of the second transistor T2, with each end of the wiring structure electrically connected to the gates of the second subtransistors ST2 of the two second transistors T2, respectively. For example, the extension direction of the gates of the second subtransistors ST2 of the second transistor T2 is the row direction DH, and the extension direction of the second wiring structure LL1 is also the row direction DH. The gate of one second subtransistor ST2, one wiring structure, and the gate of the other second subtransistor ST2 are connected sequentially. Further, the second wiring structure LL1 is disposed on the same layer as the gates of the second subtransistors ST2, for example, all of them are disposed on the third gate layer GT3.

[0109] In one embodiment of this disclosure, referring to FIG20, at least a portion of the electrostatic discharge unit DU further includes a third wiring structure HL2 electrically connected to the first wiring structure HL1. The orthographic projection of the third wiring structure HL2 on the substrate SBT lies within the orthographic projection of the signal distribution structure MA on the substrate SBT. Thus, the third wiring structure HL2 can further increase the coupling capacitance between the gate terminal of the first transistor T1 and the signal distribution structure MA, thereby providing stronger blocking capability against electrostatic pulses. When a high-level electrostatic pulse arrives, the electromotive force change caused by the high electrostatic pulse can, through the coupling between the gate terminal of the first transistor T1 and the signal distribution structure MA, pull up the voltage at the gate terminal of the first transistor T1. Simultaneously, the signal distribution structure MA charges the gate terminal of the first transistor T1 to further pull up the voltage at the gate terminal of the first transistor T1. Thus, through the synergy of charging and coupling, the voltage rise rate at the gate terminal of the first transistor T1 can be increased, thereby increasing the turn-on speed of the first transistor T1 and achieving rapid release of high-level electrostatic pulses.

[0110] In one example, along the length of the channel region of the first transistor T1, the size of the third trace structure HL2 is not less than the length of the channel region of the first transistor T1; along the width of the channel region of the first transistor T1, the size of the third trace structure HL2 is not less than the width of the channel region of the first transistor T1. Thus, the third trace structure HL2 and the signal distribution structure MA have a large overlap area, resulting in a large coupling capacitance, enabling the electrostatic discharge unit DU to release high-level electrostatic pulses more effectively and quickly.

[0111] In one embodiment of this disclosure, referring to FIG20, at least a portion of the electrostatic discharge unit DU further includes a fourth wiring structure LL2 electrically connected to the second wiring structure LL1. The orthographic projection of the fourth wiring structure LL2 on the substrate SBT lies within the orthographic projection of the signal distribution structure MA on the substrate SBT. Thus, the fourth wiring structure LL2 can further increase the coupling capacitance between the gate terminal of the second transistor T2 and the signal distribution structure MA, thereby providing stronger blocking capability against electrostatic pulses. When a low-level electrostatic pulse arrives, the electromotive force change caused by the low-level electrostatic pulse can pull down the voltage at the gate terminal of the second transistor T2 through the coupling effect between the gate terminal of the second transistor T2 and the signal distribution structure MA. Simultaneously, the gate terminal of the second transistor T2 discharges to the signal distribution structure MA to pull down the voltage at the gate terminal of the second transistor T2. Thus, through the synergy of charging and coupling, the voltage pull-down rate at the gate terminal of the second transistor T2 can be increased, thereby increasing the turn-on speed of the second transistor T2 and achieving rapid release of low-level electrostatic pulses.

[0112] In one example, along the length of the channel region of the second transistor T2, the size of the fourth trace structure LL2 is not less than the length of the channel region of the second transistor T2; along the width of the channel region of the second transistor T2, the size of the fourth trace structure LL2 is not less than the width of the channel region of the second transistor T2. Thus, the fourth trace structure LL2 and the signal distribution structure MA have a large overlap area, resulting in a large coupling capacitance, enabling the electrostatic discharge unit DU to release low-level electrostatic pulses more effectively and quickly.

[0113] In one embodiment of this disclosure, the signal transmission structure SCH includes a second signal transmission structure, wherein a first signal segment LA of the second signal transmission structure is electrically connected to a pin of the flexible printed circuit board (FPC); the electrostatic discharge unit DU of the second signal transmission structure further includes a third trace structure HL2 electrically connected to the first trace structure HL1, and / or, the electrostatic discharge unit DU of the second signal transmission structure further includes a fourth trace structure LL2 electrically connected to the second trace structure LL1. For example, the second signal transmission structure simultaneously includes both the third trace structure HL2 and the fourth trace structure LL2.

[0114] It is understood that other signal transmission structures SCH disclosed herein may also be configured with a third routing structure HL2 or a fourth routing structure LL2 as needed, or may not be configured with a third routing structure HL2 and a fourth routing structure LL2 as needed.

[0115] In one embodiment of this disclosure, in the electrostatic discharge unit DU of the second signal transmission structure, the total width of the channel region of the first transistor T1 is not less than 8 times the length of the channel region of the first transistor T1. For example, the total width of the channel region of the first transistor T1 is 8 to 16 times the length of the channel region of the first transistor T1. Specifically, the total width of the channel region of the first transistor T1 is 8, 9, 10, 11, 12, 13, 14, 15, or 16 times the length of the channel region of the first transistor T1. Thus, the first transistor T1 of the electrostatic discharge unit DU of the second signal transmission structure has sufficient width to have a large discharge capability during discharge.

[0116] In this embodiment, the total width of the channel region of the first transistor T1 refers to the sum of the widths of the channel regions of each individual first transistor T1; when the first transistor T1 has multiple first sub-transistors ST1 connected in series, the width of the channel region of the first transistor T1 is the width of the channel region of a single first sub-transistor ST1. When the first transistor T1 has multiple first sub-transistors ST1 connected in series, the length of the channel region of the first transistor T1 is the sum of the lengths of the channel regions of the first sub-transistors ST1 connected in series.

[0117] It is understood that in other signal transmission structures SCH of the present disclosure embodiments, the total width of the channel region of the first transistor T1 may be not less than 8 times the length of the channel region of the first transistor T1, as needed.

[0118] For example, the signal transmission structure SCH includes a third signal transmission structure, wherein the first signal segment LA of the third signal transmission structure is electrically connected to the electrical detection pad; in the electrostatic discharge unit DU of the third signal transmission structure, the total width of the channel region of the first transistor T1 is not less than 18 times the length of the channel region of the first transistor T1; for example, the total width of the channel region of the first transistor T1 is 18 to 28 times the length of the channel region of the first transistor T1. Exemplarily, in the third signal transmission structure, the total width of the channel region of the first transistor T1 is 18, 20, 22, 24, 26, or 28 times the length of the channel region of the first transistor T1.

[0119] In one embodiment of this disclosure, in the electrostatic discharge unit DU of the second signal transmission structure, the total width of the channel region of the second transistor T2 is not less than 8 times the length of the channel region of the second transistor T2, for example, the total width of the channel region of the second transistor T2 is 8 to 16 times the length of the channel region of the second transistor T2. For example, the total width of the channel region of the second transistor T2 is 8, 9, 10, 11, 12, 13, 14, 15, or 16 times the length of the channel region of the second transistor T2. Thus, the second transistor T2 of the electrostatic discharge unit DU of the second signal transmission structure has sufficient width to have a large discharge capability during discharge.

[0120] In this embodiment, the total width of the channel region of the second transistor T2 refers to the sum of the widths of the channel regions of each individual second transistor T2; when the second transistor T2 has multiple second sub-transistors ST2 connected in series, the width of the channel region of the second transistor T2 is the width of the channel region of a single second sub-transistor ST2. When the second transistor T2 has multiple second sub-transistors ST2 connected in series, the length of the channel region of the second transistor T2 is the sum of the lengths of the channel regions of the connected second sub-transistors ST2.

[0121] It is understood that in other signal transmission structures SCH of the present disclosure embodiments, the total width of the channel region of the second transistor T2 may be not less than 8 times the length of the channel region of the second transistor T2, as needed.

[0122] For example, in the electrostatic discharge unit DU of the third signal transmission structure, the total width of the channel region of the second transistor T2 is not less than 18 times the length of the channel region of the second transistor T2; for example, the total width of the channel region of the second transistor T2 is 18 to 28 times the length of the channel region of the second transistor T2. Exemplarily, in the third signal transmission structure, the total width of the channel region of the second transistor T2 is 18, 20, 22, 24, 26, or 28 times the length of the channel region of the second transistor T2.

[0123] In one example, in the electrostatic discharge unit DU of the second signal transmission structure, the total width of the channel region of the first transistor T1 is not less than 8 times the length of the channel region of the first transistor T1; in the electrostatic discharge unit DU of the second signal transmission structure, the total width of the channel region of the second transistor T2 is not less than 8 times the length of the channel region of the second transistor T2.

[0124] In one example, in the electrostatic discharge unit DU of the third signal transmission structure, the total width of the channel region of the first transistor T1 is not less than 18 times the length of the channel region of the first transistor T1; in the electrostatic discharge unit DU of the third signal transmission structure, the total width of the channel region of the second transistor T2 is not less than 18 times the length of the channel region of the second transistor T2.

[0125] In one embodiment of this disclosure, in the electrostatic discharge unit DU of at least a portion of the signal transmission structure SCH, the metal-oxide-semiconductor layer OSCL is provided with a fifth conductive trace structure HL3 that corresponds one-to-one with the first transistor T1; the gate of the first transistor T1 is electrically connected to the signal distribution structure MA through the corresponding fifth trace structure HL3. Thus, the fifth trace structure HL3 is equivalent to a blocking resistor placed between the gate of the first transistor T1 and the signal distribution structure MA. This blocking resistor can reduce the impact of electrostatic pulses on the gate of the first transistor T1, reducing the risk of the first transistor T1 failing due to electrostatic breakdown.

[0126] In one embodiment of this disclosure, in the electrostatic discharge unit DU of at least a portion of the signal transmission structure SCH, the metal-oxide-semiconductor layer OSCL is provided with a sixth conductive trace structure LL3 corresponding one-to-one with the second transistor T2; the gate of the second transistor T2 is electrically connected to the second power supply voltage terminal GV2P through the corresponding sixth trace structure LL3. Thus, the sixth trace structure LL3 is equivalent to a blocking resistor provided between the gate terminal of the second transistor T2 and the second power supply voltage terminal GV2P. This blocking resistor can reduce the impact of electrostatic pulses on the gate terminal of the second transistor T2, reducing the risk of the second transistor T2 failing due to electrostatic breakdown.

[0127] In some embodiments of this disclosure, at least some electrostatic discharge units (DUs) include multiple transistor units, each transistor unit including one or more transistors, and all transistors in the transistor unit share a common active layer. By having transistor units share the same active layer, the layout area of ​​the transistor units can be reduced, thereby improving the performance of the electrostatic discharge unit (DU).

[0128] In this embodiment, the transistors located in the same transistor unit can all be the first transistor T1, or all be the second transistor T2, or a mixture of the first transistor T1 and the second transistor T2.

[0129] For example, in the example of Figure 5, a first transistor T1 and a second transistor T2 share the same active layer A, and the first transistor T1 and the second transistor T2 form a transistor cell. The electrostatic discharge unit DU includes six transistor cells, that is, it has six active layers.

[0130] For example, in the example of Figure 6, a first transistor T1 and a second transistor T2 share the same active layer A, forming a transistor cell. The first transistor T1 includes two first sub-transistors ST1 connected in series, and the second transistor T2 includes two second sub-transistors ST2 connected in series. The electrostatic discharge unit DU comprises six transistor cells, i.e., has six active layers.

[0131] For example, in the example of Figure 7, a first transistor T1 and a second transistor T2 share the same active layer A, forming a transistor cell. The first transistor T1 includes two first sub-transistors ST1 connected in series, and the second transistor T2 includes two second sub-transistors ST2 connected in series. The electrostatic discharge unit DU comprises 12 transistor cells, i.e., has 12 active layers.

[0132] For example, in the example of Figure 8, the electrostatic discharge unit DU includes eight active layers A, forming eight transistor units. Four of these transistor units each include a first transistor T1 formed by two first sub-transistors ST1 connected in series; the other four transistor units each include a second transistor T2 formed by two second sub-transistors ST2 connected in series.

[0133] For example, in the example of Figure 9, the electrostatic discharge unit DU includes 16 active layers A, forming 16 transistor units. Eight of these transistor units each include a first transistor T1 formed by two first sub-transistors ST1 connected in series; the other eight transistor units each include a second transistor T2 formed by two second sub-transistors ST2 connected in series.

[0134] The following examples illustrate the structure of the electrostatic discharge unit DU provided in this disclosure. Figure 6 is a schematic diagram of the first electrostatic discharge unit in this example. Figure 10 is a schematic diagram of the structure of the metal oxide semiconductor layer OSCL in the first electrostatic discharge unit in this example. Figure 11 is a schematic diagram of the structure of the third gate layer GT3 in the first electrostatic discharge unit in this example. Figure 12 is a schematic diagram of the structure of the first source / drain metal layer SD1 in the first electrostatic discharge unit in this example. Figure 13 is a schematic diagram of the structure of the second gate layer GT2, the metal oxide semiconductor layer OSCL, and the third gate layer GT3 in the first electrostatic discharge unit in this example. Figure 14 is a schematic diagram of the structure of the second gate layer GT2, the metal oxide semiconductor layer OSCL, the third gate layer GT3, and the first source / drain metal layer SD1 in the first electrostatic discharge unit in this example.

[0135] Referring to Figures 10-14, the metal-oxide-semiconductor (OSCL) layer has six active layers A. Each active layer A is used to form a second transistor T2 (including two second sub-transistors ST2 connected in series) and a first transistor T1 (including two first sub-transistors ST1 connected in series). The second terminals of the first transistor T1 and the second transistor T2 coincide and are electrically connected to the connection portion MC located in the first source-drain metal layer SD1 through vias. The first source-drain metal layer SD1 has a signal distribution structure MA and six connection portions MC, which are electrically connected to the six active layers A respectively, thereby making the second terminals of each first transistor T1 and each second transistor T2 electrically connected to the signal distribution structure MA. Thus, in this first electrostatic discharge unit, the first transistor T1 and the second transistor T2 share a common active layer.

[0136] A third transition structure M2DL, corresponding to the active layer A, is disposed in the first source-drain metal layer SD1. The third transition structure M2DL is electrically connected to the first electrode of the second transistor T2 via a via, and is also electrically connected to the second power supply voltage trace VG2L located in the third gate layer GT3 via a via. Thus, the second power supply voltage VG2 applied to the second power supply voltage trace VG2L can be applied to the first electrode of the second transistor T2. The metal-oxide-semiconductor layer OSCL also has a sixth trace structure LL3, corresponding to the active layer A, and the first source-drain metal layer SD1 also has a fourth transition structure M2GL, corresponding to the active layer A. The gate of the second transistor T2 is disposed in the third gate layer GT3. The third transition structure M2DL is electrically connected to the sixth trace structure LL3 via a via, the sixth trace structure LL3 is then electrically connected to the fourth transition structure M2GL via a via, and the fourth transition structure M2GL is then electrically connected to the gate of the second transistor T2 via a via. This allows the second power supply voltage VG2 to be applied to the gate of the second transistor T2. In this example, the gates T1G of the first transistor T1 and T2G of the second transistor both extend along the row direction DH, which is the same as the extension direction of the first power supply voltage trace VG1L and the second power supply voltage trace VG2L. Accordingly, the width direction of the channel region of the first transistor T1 and the channel region of the second transistor T2 is the row direction DH, and the length direction is the column direction DV.

[0137] A first transition structure M1DL, corresponding to the active layer A, is provided in the first source-drain metal layer SD1. The first transition structure M1DL is electrically connected to the first electrode of the second transistor T2 via a via, and also electrically connected to the first power supply voltage trace VG1L located in the third gate layer GT3 via a via. Thus, the first power supply voltage VG1 applied to the first power supply voltage trace VG1L can be applied to the first electrode of the first transistor T1. The metal-oxide-semiconductor layer OSCL also has a fifth trace structure HL3 corresponding to the active layer A, and the first source-drain metal layer SD1 also has a second transition structure M1GL corresponding to the active layer A. The gate of the first transistor T1 is provided in the third gate layer GT3. The connection portion MC is electrically connected to the fifth trace structure HL3 via a via, the fifth trace structure HL3 is electrically connected to the second transition structure M1GL via a via, and the second transition structure M1GL is electrically connected to the gate of the first transistor T1 via a via. Thus, the signal distribution structure MA is electrically connected to the gate of the first transistor T1.

[0138] In the first electrostatic discharge unit, a second power supply voltage trace VG2L, a first power supply voltage trace VG1L, a second power supply voltage trace VG2L, and a first power supply voltage trace VG1L are alternately arranged along the column direction DV. Three sets of transistor placement spaces are formed between the four power supply traces, and the three sets of transistor placement spaces are divided into six transistor placement spaces by the signal distribution structure MA. In two adjacent sets of transistor placement spaces, the transistor placement and electrical connection methods can be mirror-symmetrical.

[0139] In the first electrostatic discharge unit, the first source-drain metal layer SD1 is further provided with one or more coupling parts MB that are electrically connected to the signal distribution structure MA. The coupling parts MB overlap with the first power supply voltage trace VG1L or the second power supply voltage trace VG2L to increase the load of the signal distribution structure MA and reduce the influence of electrostatic pulses.

[0140] In the first electrostatic discharge unit, the second gate layer GT2 is also provided with a back gate trace BGL. The back gate trace BGL overlaps with the channel regions of the first transistor T1 and the second transistor T2. It can both shield the first transistor T1 and the second transistor T2 from light and provide a bias voltage so that the first transistor T1 and the second transistor T2 have a large conduction current when they are turned on.

[0141] In this first electrostatic discharge unit, the gates of the first transistor T1 located on both sides of the signal distribution structure MA are electrically connected through the first wiring structure HL1, and the gates of the second transistor T2 located on both sides of the signal distribution structure MA are electrically connected through the second wiring structure LL1. Both the first wiring structure HL1 and the second wiring structure LL1 are disposed on the third gate layer GT3.

[0142] In the first electrostatic discharge unit, both the second power supply voltage line VG2L and the first power supply voltage line VG1L are provided with protrusions. These protrusions overlap with the signal distribution structure MA to increase the load on the signal distribution structure MA and block the impact of electrostatic pulses.

[0143] In one example, the first electrostatic discharge unit can be used as a signal transmission structure (SCH) for transmitting signals from a flexible printed circuit board (FPC).

[0144] The embodiments disclosed herein can also modify the first electrostatic discharge unit to form a second electrostatic discharge unit. Figure 7 is a schematic diagram of the principle of the second electrostatic discharge unit in this example. Figure 15 is a schematic diagram of the structure of the metal oxide semiconductor layer OSCL in the second electrostatic discharge unit in this example. Figure 16 is a schematic diagram of the structure of the metal oxide semiconductor layer OSCL and the third gate layer GT3 in the second electrostatic discharge unit in this example. Referring to Figures 15 and 16, the second electrostatic discharge unit differs from the first electrostatic discharge unit only in the pattern of the metal oxide semiconductor layer OSCL. Specifically, one active layer A in the first electrostatic discharge unit is split into two in the second electrostatic discharge unit, thereby doubling the number of transistors in the electrostatic discharge unit DU. Referring to Figure 16, each active layer A still contains one first transistor T1 (containing two first sub-transistors ST1 connected in series) and one second transistor T2 (containing two second sub-transistors ST2 connected in series). However, in this second electrostatic discharge unit, the width of the channel region of each first transistor T1 and second transistor T2 is reduced. Compared to the first electrostatic discharge unit, the second electrostatic discharge unit has a reduced channel width but an increased number of transistors. Therefore, in the event of electrostatic breakdown of a transistor, the second electrostatic discharge unit can continue to operate better and has better reliability than the first electrostatic discharge unit.

[0145] This disclosure also provides an example of a third electrostatic discharge unit. Figure 8 is a schematic diagram of the third electrostatic discharge unit in this example. Figure 17 is a schematic diagram of the structure of the metal oxide semiconductor layer OSCL within the third electrostatic discharge unit in this example. Figure 18 is a schematic diagram of the structure of the third gate layer GT3 within the third electrostatic discharge unit in this example. Figure 19 is a schematic diagram of the structure of the first source / drain metal layer SD1 within the third electrostatic discharge unit in this example. Figure 20 is a schematic diagram of the structure of the metal oxide semiconductor layer OSCL and the third gate layer GT3 within the third electrostatic discharge unit in this example. Figure 21 is a schematic diagram of the structure of the metal oxide semiconductor layer OSCL and the second gate layer GT2 within the third electrostatic discharge unit in this example. Figure 22 is a schematic diagram of the structure of the second gate layer GT2, the metal oxide semiconductor layer OSCL, the third gate layer GT3, and the first source / drain metal layer SD1 within the third electrostatic discharge unit in this example.

[0146] Referring to Figures 17-22, the metal-oxide-semiconductor (OSCL) layer has four groups of eight active layers A. Each group of active layers A includes two adjacent and partially connected active layers A. The two active layers A that are close to the second power supply voltage line VG2L and are partially connected are called the second active layer group, and the two active layers A that are close to the first power supply voltage line VG1L and are partially connected are called the first active layer group. Within each active layer A of each first active layer group, two first sub-transistors ST1 are connected in series. The third gate layer GT3 has the gate T1G of the first transistor T1, which extends along the column direction DV, and the first transistors T1 in the first active layer group share a common gate. Within each active layer A of each second active layer group, two second sub-transistors ST2 are connected in series. The third gate layer GT3 has the gate T2G of the second transistor, which extends along the column direction DV, and the second transistors T2 in the second active layer group share a common gate. The first source-drain metal layer SD1 has a signal distribution structure MA and two protrusions. The second terminal of each first transistor T1 (located in the metal-oxide-semiconductor layer OSCL) is electrically connected to one of the protrusions through a via; the second terminal of each second transistor T2 is electrically connected to one of the protrusions through a via. The first source-drain metal layer SD1 is provided with a third transition structure M2DL extending along the column direction DV. The third transition structure M2DL is electrically connected to the second power supply voltage trace VG2L through a via, and is also electrically connected to the first terminal of the second transistor T2 (located in the metal-oxide-semiconductor layer OSCL) through a via. The first source-drain metal layer SD1 is provided with a first transition structure M1DL extending along the column direction DV. The first transition structure M1DL is electrically connected to the first power supply voltage trace VG1L through a via, and is also electrically connected to the first terminal of the first transistor T1 (located in the metal-oxide-semiconductor layer OSCL) through a via. Near the second transistor T2, the first source-drain metal layer SD1 has a fourth transition structure M2GL corresponding to the second active layer group, and the metal-oxide-semiconductor layer OSCL has a sixth routing structure LL3 corresponding to the second active layer group. The third transition structure M2DL is electrically connected to the sixth routing structure LL3 through a via, and the sixth routing structure LL3 is electrically connected to the fourth transition structure M2GL through a via. The fourth transition structure M2GL is electrically connected to the gate on the second active layer group through a via. Near the first transistor T1, the first source-drain metal layer SD1 has a second transition structure M1GL corresponding to the first active layer group, and the metal-oxide-semiconductor layer OSCL has a fifth routing structure HL3 corresponding to the first active layer group. The first transition structure M1DL is electrically connected to the fifth routing structure HL3 through a via, and the fifth routing structure HL3 is electrically connected to the second transition structure M1GL through a via. The second transition structure M1GL is electrically connected to the gate on the first active layer group through a via.The third gate layer GT3 also includes a second trace structure LL1 electrically connected to the two M2Gs, and a fourth trace structure LL2 electrically connected to the second trace structure LL1, to increase the load on the signal distribution structure MA. The third gate layer GT3 also includes a first trace structure HL1 electrically connected to the two M1Gs, and a third trace structure HL2 electrically connected to the first trace structure HL1, to further increase the load on the signal distribution structure MA.

[0147] In this third electrostatic discharge unit, the first source-drain metal layer SD1 is further provided with one or more coupling portions MB electrically connected to the signal distribution structure MA. The coupling portions MB overlap with the first power supply voltage trace VG1L or the second power supply voltage trace VG2L to increase the load of the signal distribution structure MA and reduce the impact of electrostatic pulses. In this third electrostatic discharge unit, the second gate layer GT2 is further provided with a back gate trace BGL, which overlaps with the channel regions of the first transistor T1 and the second transistor T2. This can both shield the first transistor T1 and the second transistor T2 from light and provide a bias voltage so that the first transistor T1 and the second transistor T2 have a large conduction current when they are turned on. In this third electrostatic discharge unit, the gates of the first transistor T1 located on both sides of the signal distribution structure MA are electrically connected through the first trace structure HL1, and the gates of the second transistor T2 located on both sides of the signal distribution structure MA are electrically connected through the second trace structure LL1. The first trace structure HL1 and the second trace structure LL1 are both disposed on the third gate layer GT3.

[0148] In the third electrostatic discharge unit, the second gate layer GT2 is also provided with a back gate trace BGL extending along the row direction DH, and a back gate side branch BG connected to the back gate side branch BG and corresponding to the active layer group. The back gate side branch BG overlaps with each channel region in the corresponding active layer group.

[0149] In one example, the third electrostatic discharge unit can be used in the signal transmission structure SCH for transmitting electrical detection signals.

[0150] This embodiment can also modify the third electrostatic discharge unit to form a fourth electrostatic discharge unit. Figure 9 is a schematic diagram of the fourth electrostatic discharge unit in this example. Figure 23 is a schematic diagram of the structure of the metal oxide semiconductor layer OSCL and the third gate layer GT3 within the fourth electrostatic discharge unit in this example. Referring to Figure 23, the fourth electrostatic discharge unit differs from the third electrostatic discharge unit only in the pattern of the metal oxide semiconductor layer OSCL. Specifically, one active layer A portion of the third electrostatic discharge unit is split into two portions in the fourth electrostatic discharge unit, thereby doubling the number of transistors in the fourth electrostatic discharge unit. In the event of electrostatic breakdown of one transistor, the second electrostatic discharge unit can continue to operate better than the first electrostatic discharge unit, exhibiting better reliability.

[0151] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A display panel, characterized by, It includes a transistor layer and a first source / drain metal layer sequentially stacked on one side of a substrate. The display panel includes a signal transmission structure, which includes a first signal line segment, an electrostatic discharge unit, and a second signal line segment connected in sequence. The second signal line segment is located on the side of the electrostatic discharge unit closer to the display area. At least a portion of the electrostatic discharge unit includes a signal distribution structure, a plurality of first transistors connected in parallel, and a plurality of second transistors connected in parallel. Both the first and second transistors are metal-oxide transistors. The first terminal of the first transistor is used to apply a first power supply voltage, and the second terminal and gate of the first transistor are electrically connected to the signal distribution structure. The first terminal and gate of the second transistor are used to apply a second power supply voltage, and the second terminal of the second transistor is electrically connected to the signal distribution structure. The first power supply voltage is greater than the second power supply voltage. The first signal segment and the second signal segment are electrically connected to the signal distribution structure, and the second signal segment is at least partially located in the transistor layer.

2. The display panel of claim 1, wherein, At least a portion of the electrostatic discharge unit includes a plurality of first transistor groups connected in parallel, each first transistor group including a plurality of first transistors with the same gate and connected in parallel; At least a portion of the electrostatic discharge unit includes a plurality of parallel second transistor groups, each of the second transistor groups including a plurality of second transistors with the same gate and connected in parallel.

3. The display panel of claim 1, wherein, The first transistor includes a plurality of sub-transistors connected in series; the second transistor includes a plurality of sub-transistors connected in series.

4. The display panel of claim 1, wherein, The transistor layer includes at least one gate layer and at least one metal-oxide-semiconductor layer; The signal transmission structure includes a first signal transmission structure for loading a column start signal or a clock signal to the gate drive circuit of the display panel; the second signal segment of the first signal transmission structure is at least partially located in the metal oxide semiconductor layer.

5. The display panel according to claim 4, wherein, The second signal segment of the first signal transmission structure includes a first sub-trace electrically connected to the signal distribution structure and a second sub-trace electrically connected to one end of the first sub-trace away from the signal distribution structure. The first sub-trace is located in the metal oxide semiconductor layer, and the second sub-trace is located in the gate layer.

6. The display panel of claim 1, wherein, One end of the signal distribution structure is electrically connected to the first signal segment, and the other end is electrically connected to the second signal segment; The first transistors are arranged in pairs, with each pair of first transistors disposed on both sides of the signal distribution structure; the gate of the first transistor includes a first end for electrical connection with the signal distribution structure and a second end away from the first end; the display panel is provided with a first trace structure corresponding to at least one pair of first transistors, the second ends of the gates of the two first transistors of the first transistor pair are both electrically connected to the first trace structure, and the first trace structure overlaps with the signal distribution structure. And / or, the second transistors are arranged in pairs, with each pair of second transistors disposed on both sides of the signal distribution structure; the gate of the second transistor includes a first end for electrical connection to a second power supply voltage terminal and a second end away from the first end; the display panel is provided with a second trace structure corresponding to at least one pair of second transistors, the second ends of the gates of the two second transistors of the second transistor pair are both electrically connected to the second trace structure, and the second trace structure overlaps with the signal distribution structure.

7. The display panel of claim 6, wherein, The signal transmission structure includes a second signal transmission structure, wherein a first signal segment of the second signal transmission structure is electrically connected to a pin of a flexible printed circuit board. The electrostatic discharge unit of the second signal transmission structure further includes a third wiring structure electrically connected to the first wiring structure, wherein the orthographic projection of the third wiring structure on the substrate is located within the orthographic projection of the signal distribution structure on the substrate. And / or, the electrostatic discharge unit of the second signal transmission structure further includes a fourth trace structure electrically connected to the second trace structure, wherein the orthographic projection of the fourth trace structure on the substrate is located within the orthographic projection of the signal distribution structure on the substrate.

8. The display panel of claim 7, wherein, Along the length of the channel region of the first transistor, the size of the third trace structure is not less than the length of the channel region of the first transistor; along the width of the channel region of the first transistor, the size of the third trace structure is not less than the width of the channel region of the first transistor. And / or, along the length of the channel region of the second transistor, the size of the fourth trace structure is not less than the length of the channel region of the second transistor; Along the width direction of the channel region of the second transistor, the size of the fourth trace structure is not less than the width of the channel region of the second transistor.

9. The display panel of claim 7, wherein, In the electrostatic discharge unit of the second signal transmission structure, the total width of the channel region of the first transistor is not less than 8 times the length of the channel region of the first transistor; And / or, in the electrostatic discharge unit of the second signal transmission structure, the total width of the channel region of the second transistor is not less than 8 times the length of the channel region of the second transistor.

10. The display panel of claim 1, wherein, The transistor layer includes a metal oxide semiconductor layer, and the active layers of the first transistor and the second transistor are both located in the metal oxide semiconductor layer. The metal oxide semiconductor layer is provided with a fifth wiring structure that corresponds one-to-one with the first transistor and is conductive; the gate of the first transistor is electrically connected to the signal distribution structure through the corresponding fifth wiring structure. And / or, the metal oxide semiconductor layer is provided with a sixth trace structure that corresponds one-to-one with the second transistor and is conductive; the gate of the second transistor is electrically connected to the second power supply voltage terminal through the corresponding sixth trace structure.

11. The display panel of claim 1, wherein, The signal transmission structure includes a third signal transmission structure, wherein the first signal segment of the third signal transmission structure is electrically connected to the electrical detection pad. In the electrostatic discharge unit of the third signal transmission structure, the total width of the channel region of the first transistor is not less than 18 times the length of the channel region of the first transistor. And / or, in the electrostatic discharge unit of the third signal transmission structure, the total width of the channel region of the second transistor is not less than 18 times the length of the channel region of the second transistor.

12. A display device comprising the display panel as described in any one of claims 1 to 11.

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