Hard-stops for flip-chip architectures, methods of manufacturing the hard-stops, and chips and flip-chip assemblies comprising the hard-stops

Abstract

Disclosed are hard-stops for flip-chip architectures, manufacturing thereof, and chips and flip-chip assemblies comprising the hard-stops. The manufacturing involves depositing a photoresist layer (203) on a base layer (202), forming one or more openings (203a) in the photoresist that expose one or more areas of the base layer, depositing a seed layer (204) on the photoresist layer and within the openings, depositing a silicon layer (205) on the seed layer, removing the photoresist layer by a solvent, thereby lifting-off unwanted photoresist-seed-silicon stacks while keeping one or more seed-silicon islands (205a), annealing to form a eutectic bond between the silicon and the seed, thereby obtaining one or more annealed seed-silicon islands (206a), and shaping the annealed seed-silicon islands to one or more hard-stops (208a) of respective desired dimensions.

Description

[0001] Hard-stops for flip-chip architectures, methods of manufacturing the hard-stops, and chips and flip-chip assemblies comprising the hard-stops

[0002] Field of the invention

[0003] The invention relates to hard-stops for flip-chip architectures, methods of manufacturing the hard-stops, and chips and flip-chip assemblies comprising the hard-stops.

[0004] Background art

[0005] Among various physical implementations of qubits for quantum computing, superconducting circuits based on Josephson junctions are a promising platform. In the context of superconducting quantum processors, flip-chip architectures allow separate fabrication of two chips which are later combined. For example, a control circuitry chip and a qubit chip are first manufactured separately and are later combined. The flip-chip approach can offer, among other things, more precise isolation between control and qubit elements to enhance control.

[0006] An aspect of manufacturing flip-chip architectures is controlling the spacing between the two chips, as this spacing affects the capacitive coupling between the qubit elements and their corresponding control circuits. Approaches includes using hard-stops, such as polymer-based hard-stops, electroplated metallic hard-stops, direct bonding using indium bumps.

[0007] However, there is still interest in improved methods of fabricating hard-stops for flipchip architectures in the context of superconducting quantum computing.

[0008] Summary of the invention

[0009] A task set forth by the inventor is to provide improved improved methods of fabricating hard-stops for flip-chip architectures in the context of superconducting quantum computing .

[0010] The inventor solved the task by providing chips with hard-stops, a method of manufacturing hard-stops for flip-chip architectures, and flip-chip assemblies comprising the hard-stops, as set out in the appended set of claims.

[0011] The technical advantage includes at least one of:

[0012] • preservation of the quality of the underlying base layer, as the fabrication process does not require aggressive etching of the base surface, which is particularly useful in the case of a superconducting base layer for superconducting quantum-computing chips;

[0013] • enhanced mechanical stability of the hard-stops due to the formation of eutectic bonds;

[0014] • compatibility with subsequent fabrication steps and cleaning processes involving aggressive cleaning agents such as nitric acid and hydrofluoric acid;

[0015] • capability for self-alignment between chips, which simplifies assembly;

[0016] • improved reliability during thermal cycling due to the robust nature of the hard-stops;• potential for multiple use and reassembly of chips, enabling iterative optimization of quantum-processor parameters;

[0017] • enabling more precise and reliable spacing between chips in flip-chip architectures while maintaining compatibility with subsequent fabrication processes and preserving the quality of circuit components on the chips.

[0018] These advantages contribute to improved fabrication of superconducting quantum circuits while maintaining process flexibility and reliability. The invention has applications in quantum computing and quantum simulations, for example by chips and flip-chip assemblies comprising the hard-stops that can be manufactured according to the present invention. Technical advantages are further set out in the detailed description below.

[0019] Brief description of the drawings

[0020] The present invention is discussed in more detail below, with reference to the attached drawings showing examples, in which:

[0021] Fig- 1 shows the method of manufacturing the hard-stops.

[0022] Figs. 2a-2h show intermediate results of the manufacturing steps.

[0023] Figs. 3a-3h show intermediate results of the manufacturing steps in case a base layer already has a pattern.

[0024] Fig. 4a illustrates shapes of the hard-stops.

[0025] Fig. 4b illustrates the flip-chip assembly.

[0026] Figs. 5a-5c show SEM images of hard-stops before and after annealing.

[0027] Detailed description

[0028] Embodiments of the present disclosure will be described herein below with reference to the accompanying drawings. However, the embodiments of the present disclosure are not limited to the specific embodiments and should be construed as including all modifications, changes, equivalent devices and methods, and / or alternative embodiments of the present disclosure.

[0029] The terms “have,” “may have,” “include,” and “may include” as used herein indicate the presence of corresponding features (for example, elements such as numerical values, functions, operations, or parts), and do not preclude the presence of additional features.

[0030] The terms “A or B,” “at least one of A or / and B,” or “one or more of A or / and B” as used herein include all possible combinations of items enumerated with them. For example, “A or B,” “at least one of A and B,” or “at least one of A or B” means (1) including at least one A, (2) including at least one B, or (3) including both at least one A and at least one B.The terms such as “first” and “second” as used herein may modify various elements regardless of an order and / or importance of the corresponding elements, and do not limit the corresponding elements. These terms may be used for the purpose of distinguishing one element from another element. For example, a first element may be referred to as a second element without departing from the scope the present invention, and similarly, a second element may be referred to as a first element.

[0031] It will be understood that, when an element (for example, a first element) is “(operatively or communicatively) coupled with / to” or “connected to” another element (for example, a second element), the element may be directly coupled with / to another element, and there may be an intervening element (for example, a third element) between the element and another element. To the contrary, it will be understood that, when an element (for example, a first element) is “directly coupled with / to” or “directly connected to” another element (for example, a second element), there is no intervening element (for example, a third element) between the element and another element.

[0032] The expression “configured to (or set to)” as used herein may be used interchangeably with “suitable for” “having the capacity to” “designed to” “adapted to” “made to,” or “capable of’ according to a context. The term “configured to (set to)” does not necessarily mean “specifically designed to” in a hardware level. Instead, the expression “apparatus configured to...” may mean that the apparatus is “capable of...” along with other devices or parts in a certain context.

[0033] The terms used in describing the various embodiments of the present disclosure are for the purpose of describing particular embodiments and are not intended to limit the present disclosure. As used herein, the singular forms are intended to include the plural forms as well, unless the context clearly indicates otherwise. All of the terms used herein including technical or scientific terms have the same meanings as those generally understood by an ordinary skilled person in the related art unless they are defined otherwise. The terms defined in a generally used dictionary should be interpreted as having the same or similar meanings as the contextual meanings of the relevant technology and should not be interpreted as having ideal or exaggerated meanings unless they are clearly defined herein. According to circumstances, even the terms defined in this disclosure should not be interpreted as excluding the embodiments of the present disclosure.

[0034] The person skilled in the art will understand that the features described above and / or below may be combined in any way deemed useful. The drawings of the present disclosure show examples / embodiments of the invention, which will be described in detail hereinafter. Itis to be understood that one or more of elements / components shown and / or described in one or more of these examples / embodiments and not in others may be used in those others too unless mechanical or other limitations prevent such an implementation. Moreover, describing features of different examples / embodiments in a single passage does not automatically mean that those features are inextricably linked. They may be applied separately from one another.

[0035] Superconducting quantum processors based on flip-chip architectures have attracted research interest. There are various approaches for implementing such architectures, including different methods for achieving controlled spacing between chips. For example, there are silicon-based spacing elements [Niedzielski et al], polymer-based approaches [Norris et al], direct bonding technique using indium bumps [Kosen et al], superconducting hard stops by electroplating [WO2024231595A1],

[0036] However, there are limitations to such approaches. For instance, polymer-based hard-stops, while easier to implement, are not compatible with subsequent fabrication steps and may degrade during thermal cycling. Other implementations avoid hard-stops altogether and rely solely on indium bump bonding, but this can result in tilt between the chips and may allow only single use of the fabricated chips.

[0037] In view of the desire to work with flip-chip assemblies in the context of superconducting quantum computing, there is interest in improved methods of fabricating hard-stops that maintain the quality of superconducting components while providing reliable chip separation and allowing for subsequent processing steps.

[0038] The present invention provides a different way of manufacturing hard-stops. The present invention includes a method of manufacturing hard-stops for flip-chip architectures. The method is shown in Fig. 1 as a flowchart. The method comprises:

[0039] providing (1) a substrate (201) with a base layer (202) on the substrate; depositing (2) a first photoresist layer (203) on the base layer (202), the first photoresist layer comprising one or more openings (203a; 203b) that expose one or more areas (202a; 202b) of the base layer (202);

[0040] depositing (3) a seed layer (204) on the first photoresist layer (203) and within the one or more openings (203a; 203b), the seed layer being in direct contact with and covering the one or more areas (202a; 202b);

[0041] depositing (4) a silicon layer (205) on the seed layer (204);removing (5) the first photoresist layer (203) by a solvent, thereby lifting-off unwanted photoresist-seed-silicon stacks while keeping one or more seed-silicon islands (205a; 205b) formed on the one or more areas (202a; 202b);

[0042] annealing (6) to form eutectic bonds between the silicon and the seed, thereby obtaining one or more annealed seed-silicon islands (206a; 206b); and

[0043] shaping (7) the one or more annealed seed-silicon islands (206a; 206b) to one or more hard-stops (208a; 208b) of respective desired dimensions.

[0044] Figs. 2a-2h show intermediate results of the manufacturing steps that are outlined in more detail below. Figs. 3a-3h show intermediate results of the manufacturing steps, in case a base layer already has a pattern (202-1), but are otherwise identical to Figs. 2a-2h. Figs. 3a-3h are for showcasing that the present method can be applied to produce hard-stops while preserving the quality of already pre-existing patterns (202-1) on the base layer. The order and combination of manufacturing steps eliminates the need to perform dry-etching on interested parts (202-1) of the base layer, thereby preserving their quality. That is particularly useful when desiring to add hard-stops to a superconducting base layer (202) with the pattern (202-1) that has high-quality requirements for functioning as part of a superconducting quantum computer chip, e.g. involving fine-structured Josephson-junction features. The below description focuses on Figs. 2a-2h, but applies to Figs. 3a-3h as well.

[0045] Fig. 2a shows the result after manufacturing step 1 of providing (1) a substrate (201) with a base layer (202) on the substrate.

[0046] The substrate (201) may be formed of any suitable dielectric material, such as silicon, sapphire, etc. The base layer (202) is preferably a superconducting material layer, such as NbTiN, Nb, or Ta, which is suitable for forming circuitry for a quantum processor.

[0047] Fig. 2b shows the result after manufacturing step 2 of depositing (2) a first photoresist layer (203) on the base layer (202), the first photoresist layer comprising one or more openings (203 a; 203b) that expose one or more areas (202a; 202b) of the base layer (202).

[0048] Preferably, the openings (203a; 203b) are designed larger than the intended final dimensions of the hard-stops to ensure adequate coverage by the seed layer (outlined further below) while maintaining sufficient distance from the edge of the photoresist for reliable liftoff. Preferably, the openings are at least 10pm larger, more preferably 50pm larger, most preferably 100pm larger, than the intended final dimensions of the hard-stops.

[0049] Preferably, the first photoresist layer (203) is a bilayer photoresist comprising a bottom layer (203-1) and a top layer (203-2). Such a bilayer is advantageous for providing the one or more openings (202a; 202b), by exposure for defining locations of the intended openings,followed by developing and cleaning. The thickness of the photoresist layer (203) may depend on the type of involved photoresist(s).

[0050] Preferably, the bilayer photoresist comprises a bottom layer (203-1) of polydimethylglutarimide (PMGI) and a top layer (203-2) of positive photoresist S1805. This bilayer structure is particularly advantageous for achieving reliable lift-off and for devising the one or more opening (203a; 203b). As an illustrative and non-limiting example of devising the openings, the process of forming the one or more openings (203a; 203b) may comprise the following steps:

[0051] • First, spin-coating a PMGI layer (203-1) onto the base layer (202) and baking to remove solvents (i.e., exposing to a certain suitable temperature for a sufficient time length);

[0052] • Second, spin-coating a SI 805 positive photoresist layer (203-2) on top of the PMGI layer (203-1) and baking as well.

[0053] • Third, exposing the obtained bilayer stack (203) to UV light through a photomask defining the locations of the intended openings (203 a; 203b);

[0054] • Fourth, developing the exposed top layer (203-2) in a developer (e.g. MF-319) for creating openings in said top layer (203-2);

[0055] • Fifth, developing the underlying PMGI layer (203-1) in a separate step using a dedicated PMGI developer;

[0056] • Finally, subjecting the structure to a oxygen plasma treatment to remove any residual resist in the opened areas.

[0057] As an illustrative example, the thickness of the PMGI layer may be in between 400-600nm. The thickness of the SI 805 layer may also be in between 400-600nm.

[0058] Fig. 2c shows the result after manufacturing step 3 of depositing (3) a seed layer (204) on the first photoresist layer (203) and within the one or more openings (203a; 203b), the seed layer being in direct contact with and covering the one or more areas (202a; 202b).

[0059] Preferably, the seed layer (204) is of gold, i.e., is a gold seed layer (204), preferably deposited by e-beam evaporation. Gold enables robust eutectic bonding to the subsequently deposited silicon layer. Preferably, the gold seed layer (204) is deposited by e-beam evaporation to a thickness of 50-250nm, more preferably of 100-230nm, even more preferably of 150-210nm, most preferably about 200nm. Such relatively thick gold layer enhances the robustness of the (later formed) eutectic bonding with the subsequently deposited silicon layer.

[0060] Preferably, prior to seed layer deposition, the exposed areas of the base layer are cleaned using oxygen plasma treatment to remove organic contaminants and / or hydrofluoric acid (HF) treatment to remove native oxides. Such cleaning steps improve the interfaceproperties between the superconducting base layer (202) and the seed layer (204), by enhancing adhesion of the seed layer, while additionally for example also maintaining the superconducting properties of the base layer.

[0061] Fig.2d shows the result after manufacturing step 4 of depositing (4) a silicon layer (205) on the seed layer (204).

[0062] Preferably, the silicon layer (205) is of amorphous silicon (a-Si). That is, preferably, step 4 is depositing (4) an amorphous-silicon layer (205) on the seed layer (204). The use of amorphous silicon offers superior deposition control and uniformity compared to crystalline silicon. Amorphous silicon is particularly preferred in combination with a gold seed layer. The amorphous structure facilitates better eutectic bonding with a gold seed layer.

[0063] Preferably, the amorphous silicon is deposited by PECVD to a thickness equal to or slightly greater than the desired final hard-stop height (e.g., 15pm). For example, the final hard-stop height preferably ranges in between 1-30pm, depending on the use case. For example, for some applications where strong capacitive coupling is required, one may choose to devise an amorphous-silicon thickness that is relatively thin, e.g. around 1pm.

[0064] Fig. 2e shows the result after manufacturing step 5 of removing (5) the first photoresist layer (203) by a solvent, thereby lifting-off unwanted photoresist-seed-silicon stacks while keeping one or more seed-silicon islands (205a; 205b) formed on the one or more areas (202a; 202b).

[0065] Fig. 2f shows the result after manufacturing step 6 of annealing (6) to form eutectic bonds between the silicon and the seed, thereby obtaining one or more annealed seed-silicon islands (206a; 206b).

[0066] The annealing causes the formation of strong eutectic bonds between the silicon islands and the seed layer, thereby significantly improving mechanical stability of the hard-stops. A temperature for the annealing may be chosen depending on the seed material.

[0067] Preferably, the seed layer is a gold seed layer and the annealing (6) is performed at a temperature between 350°C and 450°C, more preferably between 375°C and 425°C, more preferably 390°C and 410°C, most preferably at approximately 400°C. These temperature ranges are more particularly advantageous when the seed layer is a gold seed layer and the silicon layer is of amorphous silicon.

[0068] Figs. 2g-h show the result after manufacturing step 7 of shaping (7) the one or more annealed seed-silicon islands (206a; 206b) to one or more hard-stops (208a; 208b) of respective desired dimensions. Preferably, the shaping (7) comprises using a second photoresist layer (207) and dry-etching.Preferably, the shaping (7) comprises:

[0069] depositing (7-1) a second photoresist layer (207) on the base layer (202) and the one or more annealed seed-silicon islands (206a; 206b), the second photoresist layer (207) comprising one or more further openings (207-la, 207-2a; 207-lb, 207-2b) for exposing respective parts of the one or more annealed seed-silicon islands (206a; 206b); and

[0070] dry-etching (7-2) the one or more annealed seed-silicon islands (206a; 206b) via the exposed respective parts to obtain the one or more hard-stops (208a; 208b) and removing the second photoresist layer (207).

[0071] The technical advantage of this two-step approach, achieved in combination with the previous manufacturing steps, includes precise control over the final hard-stop dimensions while protecting the surrounding base layer. The technical advantage further includes the ability to achieve accurate in-plane dimensions for enhanced self-alignment capabilities. The desired end-shape of the hard-stops may be chosen to match for assembling chips. For example, a first chip (200-1) may have a hard-stop of with a first shape and a second chip (200-2) may have a hard-stop with a second shape that is complementary to the first shape, wherein the second shape includes an opening dimensioned to receive the hard-stop of the first chip, for selfalignment of the first and second chips. A preferred example of the shapes is outlined further below and in the illustrations of Figs. 4a-4b.

[0072] Next, a number of preferred aspects is outlined in more detail.

[0073] Preferably, the base layer (202) is a superconducting base layer (202). Superconducting base layers play a central part in quantum circuit operations and form fundamental building blocks of superconducting quantum processors, including for example control lines, resonators, and ground planes. The quality of this superconducting layer directly impacts the performance of the quantum processor, for example in terms of coherence times and gate fidelities.

[0074] The superconducting base layer (202) may be formed of various materials suitable for quantum circuit applications, including but not limited to Niobium titanium nitride (NbTiN), Niobium (Nb), Tantalum (Ta), and / or other superconducting materials such as aluminum (Al) or titanium nitride (TiN), depending on specific application requirements.

[0075] The base layer (202) can be deposited on the substrate (201) using techniques that ensure high film quality, such as DC magnetron sputtering, RF sputtering, Atomic layer deposition (ALD); or Electron beam evaporation. The thickness of the base layer (202) depends on the applications, and may for example be in the range of 50-500nm, preferably 100-300nm.

[0076] A technical advantage of the present invention is that it can preserve the quality of such superconducting base layer (202) during hard-stop fabrication. For example, a surfaceroughness can be kept minimal to reduce unwanted losses. Conventional methods often require direct etching of the substrate, which can damage or degrade the surface where the superconducting layer is subsequently deposited. In contrast, the present invention allows for deposition of the superconducting layer before hard-stop fabrication, protection of the superconducting layer during processing, compatibility with thorough cleaning procedures for maintaining high film quality, and thereby thus preservation of superconducting properties after the fabrication process. The method thus enables thorough cleaning steps using aggressive chemicals (such as 100% nitric acid and concentrated HF) without compromising the hard-stops or the base layer, thereby ensuring high-quality surfaces for subsequent fabrication steps such as air bridges and Josephson junctions. Figs. 3a-3h further illustrate that a pre-existing pattern (202-1) may be preserved in its quality during the manufacturing of the hard-stops. The parts close to the hard-stop are not of interest as compared to the pre-existing pattern (202-1).

[0077] Preferably, the seed layer (204) is of gold, i.e., the seed layer (204) consists of gold and can thus be referred to as a gold seed layer (204). Gold is particularly advantageous as a seed layer material due to its chemical stability and resistance to oxidation, adhesion properties, ability to form eutectic bonds with silicon, and compatibility with subsequent processing steps and cleaning agents.

[0078] Preferably, in combination with the gold seed layer (204), the silicon layer (205) is of amorphous silicon. I.e., preferably, the seed layer (204) is a gold seed layer (204) and the silicon layer (205) is an amorphous-silicon layer (205). The combined gold-silicon stack structure provides high mechanical stability and is thereby particularly preferred combination.

[0079] Preferably, at least one of the one or more hard-stops (208a; 208b) has a cylindrical shape (208a-l) or a ring shape (208a-2) with an inner opening (208a-3). Fig. 4a illustrates such shapes of the hard-stops.

[0080] Such geometric configurations are advantageous for reliable self-alignment in flip-chip assemblies and improve alignment accuracy. The cylindrical shape (208a-l) may involve a circular cross-section in a plane parallel to the substrate surface and vertical sidewalls perpendicular to the substrate surface, with a diameter depending on the desired hard-stop dimensions, e.g. ranging from 50 to 500pm, and a height depending on the desired hard-stop height and related to the deposited silicon layer thickness, e.g. typically 1-30pm. The ring shape (208a-2) with inner opening (208a-3) may involve an annular structure with concentric outer and inner circles, vertical sidewalls for both outer and inner circumferences, and a matching outer diameter. The inner opening (208a-3) diameter may be sized to accommodate a cylindrical hard-stop of an opposing chip. These geometric configurations may be implemented forexample by including varying control of photomask design and fabrication, photolithography exposure and development, dry etching parameters, and post-etch cleaning and inspection.

[0081] Preferably, the method further comprises, after the annealing (6) and before the shaping (7), polishing the one or more annealed seed-silicon islands (206a; 206b) to a desired height and surface planarity. The order of processing steps suitable for obtaining the annealed seed-silicon islands thus enables to achieve precise height control and surface planarity of the hard-stops, while maintaining the quality of the base layer.

[0082] Further provided is a hard-stop (205a, 205b, 208a) for flip-chip architectures, the hard-stop comprising a seed layer (204) and a silicon layer (205) disposed on the seed layer (204), wherein a eutectic bond is formed between the silicon and the seed. The eutectic bond may be obtained by an annealing step as outlined above.

[0083] Preferably, the seed layer is of gold. Preferably, the silicon layer is of amorphous silicon. The combination of gold and amorphous silicon is particularly preferred. Moreover, the hard-stop preferably comprises one or more, most preferably all, of the preferred aspects as outlined above and below.

[0084] Further provided is a chip for a flip-chip architecture, the chip comprising:

[0085] a substrate (201);

[0086] a base layer (202) disposed on the substrate (201);

[0087] one or more hard-stops (208a; 208b) disposed on the base layer (202), each hard-stop comprising a seed layer (204) in direct contact with the base layer and a silicon layer (205) disposed on the seed layer (204).

[0088] The chip preferably comprises one or more, preferably all of, the preferred aspects as outlined above and below.

[0089] Furter provided is a flip-chip assembly (300) comprising:

[0090] a first chip (200-1) preferably with one or more of the above preferred aspects, wherein at least one hard-stop of the first chip has a first shape; and

[0091] a second chip (200-2) preferably with one or more of the above preferred aspects, wherein at least one hard-stop of the second chip has a second shape that is complementary to the first shape,

[0092] wherein the second shape includes an opening dimensioned to receive the hard-stop of the first chip, for self-alignment of the first and second chips.

[0093] The chips (200-1, 200-2) preferably comprise one or more, preferably all of, the preferred aspects as outlined above and below.Preferably, the first shape is a cylindrical shape (208a-l) and the second shape is a ring shape (208a-2) with an inner opening (208a-3) dimensioned to receive the cylindrically-shaped hard-stop of the first chip.

[0094] So, the hard-stops may be formed in complementary patterns on opposing chips -preferably, as a circle / cylinder on one chip matching a ring with corresponding inner opening on the opposite chip.

[0095] In other words, preferably, the flip-chip assembly (300) comprises:

[0096] a first chip (200-1) preferably with one or more of the above preferred aspects, wherein at least one hard-stop of the first chip has a cylindrical shape (208a- 1); and

[0097] a second chip (200-2) preferably with one or more of the above preferred aspects, wherein at least one hard-stop of the second chip has a ring shape (208a-2) with an inner opening (208a-3) dimensioned to receive the cylindrically-shaped hard-stop of the first chip, for self-alignment of the first and second chips.

[0098] The provided configuration efficiently enables self-alignment during assembly. The resulting chip structure comprises the hard-stops firmly bonded to the respective base layers via the respective seed layers. The configuration provides mechanical stability while maintaining sufficient control on the distance, e.g. for providing sufficient control and / or electrical isolation for quantum circuit operations. Fig. 4b illustrates the flip-chip assembly (300).

[0099] Preferably, at least one of, more preferably both of, the first chip (200-1) and the second chip (200-2) are obtained by the manufacturing method of the present disclosure, more preferably with one or more of, most preferably all of, the preferred aspects as outlined above and below.

[0100] Figs. 5a-5c show SEM images of hard-stops before and after annealing, at the example of the preferred combination of gold and amorphous silicon.

[0101] Fig. 5a shows an SEM image of a hard-stop before annealing.

[0102] Fig. 5b shows an SEM image of a hard-stop after annealing.

[0103] Fig. 5c shows another SEM image of a hard-stop after annealing.

[0104] Figs. 5a-5c showcase the eutectic bond formed by the annealing and the high regularity that can be achieved by the specific order and combination of manufacturing steps of the present disclosure, leading to an increased bonding-strength and simplified assembly while preserving high-quality of a superconducting base material and eventual pre-existing patterns therein.

[0105] The materials for the layers may be chosen depending on product preferences. Below, some examples are listed:The substrate (201) may include one or more of Silicon (Si) wafer, Sapphire (aluminium oxide, AI2O3), Silicon carbide (SiC), fused silica (silicon dioxide, SiCh), glass, Gallium arsenide (GaAs).

[0106] The superconducting base layer (202) may include one or more of Niobium titanium nitride (NbTiN), Niobium (Nb), Tantalum (Ta), Aluminum (Al), Titanium nitride (TiN), Molybdenum rhenium (MoRe), Tantalum nitride (TaN).

[0107] The first photoresist layer (203) may comprise various bilayer combinations, such as the preferred PMGI / S1805, or PMGI / S1813, LOR / S1805, LOR / PMMA, PMGI / AZ1512.

[0108] The seed layer (204) may comprise one or more of Gold (Au) (preferred), Platinum (Pt), Palladium (Pd), Silver (Ag), Copper (Cu), Aluminium (Al). The annealing-temperature is accordingly chosen depending on the material. For example, for Al, preferably a relatively higher annealing-temperature is used as compared to Au. The seed-layer material is preferably different from the base-layer material.

[0109] The silicon layer (205) may comprise one or more of amorphous silicon (a-Si), polycrystalline silicon, silicon deposited by electron beam evaporation.

[0110] The following list of references is referred to in the present document and is incorporated herein by way of reference.

[0111] List of references

[0112] [A] Authors. Title. Publisher. Date.

[0113] [Kosen et al] Sandoko Kosen et al. Signal crosstalk in a flip-chip quantum processor. PRX Quantum 5, 030350 (2024). 2024.

[0114] [Niedzielski et al] B. M. Niedzielski et al. Silicon Hard-Stop Spacers for 3D Integration of Superconducting Qubits. 2019 IEDM, USA, (2019), pp. 31.3.1-31.3.4. 2019

[0115] [Norris et al] Norris et al. Improved parameter targeting in 3D-integrated superconducting circuits through a polymer spacer process. EPJ Quantum Technology (2024) 11:5. 2024.

[0116] [WO2024231595A1] Superconducting Hard-Stops for Flip Chip.

Claims

What is claimed is:

1. Method of manufacturing hard-stops for flip-chip architectures, the method comprising: providing (1) a substrate (201) with a base layer (202) on the substrate; depositing (2) a first photoresist layer (203) on the base layer (202), the first photoresist layer comprising one or more openings (203a; 203b) that expose one or more areas (202a; 202b) of the base layer (202);depositing (3) a seed layer (204) on the first photoresist layer (203) and within the one or more openings (203a; 203b), the seed layer being in direct contact with and covering the one or more areas (202a; 202b);depositing (4) a silicon layer (205) on the seed layer (204);removing (5) the first photoresist layer (203) by a solvent, thereby lifting-off unwanted photoresist-seed-silicon stacks while keeping one or more seed-silicon islands (205a; 205b) formed on the one or more areas (202a; 202b);annealing (6) to form eutectic bonds between the silicon and the seed, thereby obtaining one or more annealed seed-silicon islands (206a; 206b); andshaping (7) the one or more annealed seed-silicon islands (206a; 206b) to one or more hard-stops (208a; 208b) of respective desired dimensions.

2. The method of claim 1, wherein the shaping (7) comprises:depositing (7-1) a second photoresist layer (207) on the base layer (202) and the one or more annealed seed-silicon islands (206a; 206b), the second photoresist layer (207) comprising one or more further openings (207-la, 207-2a; 207-lb, 207-2b) for exposing respective parts of the one or more annealed seed-silicon islands (206a; 206b); anddry-etching (7-2) the one or more annealed seed-silicon islands (206a; 206b) via the exposed respective parts to obtain the one or more hard-stops (208a; 208b) and removing the second photoresist layer (207).

3. The method of any one of the preceding claims, wherein the base layer (202) is a superconducting base layer (202).

4. The method of any one of the preceding claims, wherein the seed layer (204) is of gold.

5. The method of any one of the preceding claims, wherein the silicon layer (205) is of amorphous silicon.

6. The method of any one of the preceding claims, wherein at least one of the one or more hard-stops (208a; 208b) has a cylindrical shape (208a- 1) or a ring shape (208a-2) with an inner opening (208a-3).

7. The method of any one of the preceding claims, further comprising, after the annealing (6) and before the shaping (7), polishing the one or more annealed seed-silicon islands (206a; 206b) to a desired height and surface planarity.

8. The method of claim 4, wherein the annealing (6) is performed at a temperature between 350°C and 450°C.

9. The method of any one of the preceding claims, wherein the first photoresist layer (203) is a bi-layer comprising a bottom layer (203-1) and a top layer (203-2).

10. Hard-stop (205a, 205b, 208a) for flip-chip architectures, the hard-stop comprising a seed layer (204) and a silicon layer (205) disposed on the seed layer (204), wherein a eutectic bond is formed between the silicon and the seed.

11. Chip for a flip-chip architecture, the chip comprising:a substrate (201);a base layer (202) disposed on the substrate (201);one or more hard-stops (208a; 208b) disposed on the base layer (202), each hard-stop comprising a seed layer (204) in direct contact with the base layer and a silicon layer (205) disposed on the seed layer (204).

12. The chip of claim 11, wherein the base layer (202) is a superconducting base layer (202).

13. The chip of any one of the preceding claims, wherein the seed layer (204) is of gold.

14. The chip of any one of the preceding claims, wherein the silicon layer (205) is of amorphous silicon.

15. The chip of any one of the preceding claims, wherein at least one of the one or more hard-stops (208a; 208b) has a cylindrical shape (208a- 1) or a ring shape (208a-2) with an inner opening (208a-3).

16. Flip-chip assembly (300) comprising:a first chip (200-1) according to any one of claims 11-15, wherein at least one hard-stop of the first chip has a first shape; anda second chip (200-2) according to any one of claims 11-15, wherein at least one hard-stop of the second chip has a second shape that is complementary to the first shape, wherein the second shape includes an opening dimensioned to receive the hard-stop of the first chip, for self-alignment of the first and second chips.

17. The flip-chip assembly (300) of claim 16, wherein:at least one hard-stop of the first chip has a cylindrical shape (208a-l); andat least one hard-stop of the second chip has a ring shape (208a-2) with an inner opening (208a-3) dimensioned to receive the cylindrically-shaped hard-stop of the first chip, for selfalignment of the first and second chips.15

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