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1/4 rate 4-tap DFE (decision feedback equalizer) for high-speed serial interface receiving end

A high-speed serial interface, decision feedback equalization technology, applied to the shaping network in the transmitter/receiver, baseband system components, etc.

Active Publication Date: 2014-01-01
TSINGHUA UNIV
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

When the data transmission rate of the high-speed serial interface reaches 10Gbps or above, the stronger the attenuation of the channel, the greater the ISI, and the power consumption of the system will also be a prominent problem

Method used

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  • 1/4 rate 4-tap DFE (decision feedback equalizer) for high-speed serial interface receiving end
  • 1/4 rate 4-tap DFE (decision feedback equalizer) for high-speed serial interface receiving end
  • 1/4 rate 4-tap DFE (decision feedback equalizer) for high-speed serial interface receiving end

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Embodiment Construction

[0042] The implementation of the present invention will be described in detail below in conjunction with the drawings and examples.

[0043] The preferred embodiments will be described in detail below in conjunction with the accompanying drawings. It should be emphasized that the following description is only exemplary and not intended to limit the scope of the invention and its application.

[0044] figure 1 is a simplified high-speed serial interface transceiver circuit block diagram. It includes 1 / 4 rate 4-tap decision feedback equalizer 100, 4:1 multiplexer (MUX), clock receiver & generator (Clock Receiver&Generator), current mode logic driver circuit (CML Driver) and bias generation circuit (Bias Generator). The clock receiver and generator receives the half-rate CML level differential clock signal input from the outside, passes through the frequency divider and CML to CMOS circuit, and generates four 1 / 4-rate CMOS clock signals CLK1 and CLK2 with a phase shift of 90 d...

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Abstract

The invention relates to a 1/4 rate 4-tap DFE (decision feedback equalizer) for a high-speed serial interface receiving end. The 1/4 rate 4-tap DFE comprises four channels with same structures, and each channel comprises a sampling and holding module, a summator, and two latches, wherein firstly, current input high-speed serial data is sampled by using a pair of 1/4 rate clock signals with a 90-degree phase shift by virtue of the sampling and holding module, so that 1/4 rate data is obtained; the 1/4 rate data decided at the last cycle passes through the two cascaded latches, different deferred data can be obtained; by virtue of combining the deferred data from the four channels, the 4-tap feedback signals can be realized in each channel, and are fed back to the front summator; the summator sums the current 1/4 rate data and four feedback signals to obtain the current decided 1/4 rate data, and then decision feedback is realized; the 1/4 rate 4-tap DFE for the high-speed serial interface receiving end, provided by the invention, samples by using the 1/4 rate clock, and is equipped with 4 tap so as to simultaneously meet the requirements of low power dissipation and strong balance capability.

Description

technical field [0001] The invention belongs to the technical field of circuit design and data transmission, and particularly relates to a 1 / 4 rate 4-tap decision feedback equalizer used for a high-speed serial interface receiving end. Background technique [0002] The high-speed serial interface mainly includes two parts: the transmitting end and the receiving end. The functions realized are: at the transmitting end, the low-speed parallel signal is converted into a high-speed serial signal by using high-speed clock sampling technology, and then transmitted in the channel; The receiving end extracts the clock and data signals from the received data, and uses the serial-to-parallel conversion circuit to convert the high-speed serial signal into a low-speed parallel signal. Since the actual channel cannot completely satisfy the ideal waveform transmission distortion-free condition, channel distortion is inevitable. The channel distortion will cause the intersymbol interferen...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04L25/03
Inventor 袁帅王自强郑旭强乌力吉张春王志华
Owner TSINGHUA UNIV
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