Pixel circuit, driving method and display device
A pixel circuit and circuit technology, applied in the field of driving methods, display devices, and pixel circuits, capable of solving the problems of increasing the area of a single pixel and reducing the PPI of a display device, etc.
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Embodiment 1
[0038] Embodiment 1 of the present invention provides a pixel circuit, such as figure 1As shown, the pixel circuit includes: a first sub-pixel circuit 10, two second sub-pixel circuits 21 and 22, a compensation sharing circuit 30, and a sharing control circuit 40, wherein the first sub-pixel circuit 10 includes 6 transistors, and the first sub-pixel circuit 10 includes six transistors. A switching transistor T1, a second switching transistor T2, a third switching transistor T3, a fourth switching transistor T4, a fifth switching transistor T5, a first driving transistor DT_G, a first capacitor C1, and a first electroluminescent element L1 , the second sub-pixel circuit 21 includes three transistors, an eighth switch transistor T8, a ninth switch transistor T9 and a second drive transistor DT_R, a second capacitor C2 and a second electroluminescent element L2, and the third sub-pixel circuit 22 Including three transistors, the tenth switch transistor T10, the eleventh switch tr...
Embodiment 2
[0061] like Figure 4 Shown is a schematic structural diagram of a pixel circuit provided in Embodiment 2 of the present invention, and figure 1 the difference is, Figure 4 The gate of the first switching transistor T1 in the circuit is connected to a signal output terminal Scan alone, and Figure 4 The circuit shown does not include the second switching transistor T2. At this time, the timing diagram of each signal driving the pixel circuit is as follows: Figure 5 shown, with figure 2 The difference is that in the second stage, when a low-level signal is applied to Gate, a low-level signal is applied to Scan at the same time, the first switching transistor T1 is turned on, and the first voltage Vg1 is applied to DG, and the The voltage of terminal B1 is set to Vg1; in the third stage, only a low level signal is applied to Scan, the first switching transistor T1 is turned on, other transistors are turned off, and a second voltage Vg2 is applied to DG to make B1 The volt...
Embodiment 3
[0065] The schematic structural diagram of the pixel circuit provided by the third embodiment of the present invention is as follows: Image 6 shown, with Figure 4 The difference between the provided circuits is that the A1 terminal of the first capacitor C1 is connected to the B2 terminal of the second capacitor C2 and the B3 terminal of the third capacitor C3 through the sixth switching transistor T6. At this time, the eighth switching transistor T8 is connected to the second capacitor. The A terminal of C2, the tenth switch transistor T10 is connected to the A terminal of the third capacitor C3, and the seventh switch transistor T7 may not be set at this time, and the driving method of the pixel circuit can be as follows Figure 7 shown, with Figure 5 The difference in the driving method is that in the second stage of compensating the second capacitor C2 and the third capacitor C3 to VDD+Vth1, the first voltages Vr1 and Vb1 are respectively applied to DR and DB, so that ...
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