CPU interconnection device and multichannel server CPU interconnection topological structure

A technology of multi-channel server and topology structure, which is applied in the field of CPU interconnection device and multi-channel server CPU interconnection topology structure, and can solve problems such as inability to interconnect multiple CPUs and limited number of QPI links.

Inactive Publication Date: 2016-07-27
LANGCHAO ELECTRONIC INFORMATION IND CO LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] However, due to the limited number of QPI links of the CPU itself, the

Method used

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  • CPU interconnection device and multichannel server CPU interconnection topological structure
  • CPU interconnection device and multichannel server CPU interconnection topological structure
  • CPU interconnection device and multichannel server CPU interconnection topological structure

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Embodiment Construction

[0032] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments It is a part of the embodiments of the present invention, but not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative work belong to the protection of the present invention. scope.

[0033] Such as figure 1 As shown, the embodiment of the present invention provides a CPU interconnection device 10, which may include:

[0034] The first NC (Node controller, node controller) chip 101, the second NC chip 102, the first CPU 103, the second CPU 104, the third CPU 105 and the fourth CPU 106, wherein,

[0035] The first NC chip 101 and th...

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Abstract

The invention provides a CPU interconnection device and multi-channel server CPU interconnection topology, the CPU interconnection device includes: two NC chips and four CPUs, wherein, the CPU has a QPI bus interface, and the NC chip has a QPI bus interface and NI bus Interface; according to the QPI link, the four CPUs are sequentially connected into a four-way configuration structure, and one NC chip is connected to any adjacent two CPUs, and the other NC chip is connected to the other two CPUs. In addition to the QPI link, according to the NI line corresponding to the NI bus interface, the NC chip can be used as a medium to realize the communication between any two CPUs, and the number of NC chips is not limited. Since the pairwise connection between CPUs is no longer limited to the QPI link, this solution can enable multiple CPUs of more servers to be interconnected by using a certain number of such CPU interconnection devices.

Description

technical field [0001] The invention relates to the technical field of computers, in particular to a CPU interconnection device and a multi-path server CPU interconnection topology. Background technique [0002] In key business industries such as finance and telecommunications, the basic requirements for server computing speed and shared memory are relatively high. Multi-channel servers, such as eight-channel servers and sixteen-channel servers, can not only meet these basic requirements, but also hold great advantages in database applications and cloud computing. [0003] Currently, multiple CPUs of a multi-channel server can be connected through QPI direct connection. [0004] However, due to the limited number of QPI links of the CPU itself, the existing connection method cannot interconnect multiple CPUs of more servers. Contents of the invention [0005] The invention provides a CPU interconnection device and a CPU interconnection topology structure of multiple serv...

Claims

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Application Information

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IPC IPC(8): G06F15/173
CPCG06F15/17337
Inventor 黄家明乔英良李冠广梁锐
Owner LANGCHAO ELECTRONIC INFORMATION IND CO LTD
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