FPGA configuration file updating method and device
A configuration file and file technology, applied in the direction of program control device, program loading/starting, etc., can solve the problems of low reliability, laborious, time-consuming FPGA configuration file update, etc., and achieve the effect of reducing labor intensity and saving update time
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[0032] The technical solutions in the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the present invention. Apparently, the described embodiments are part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.
[0033] see figure 1 , is a schematic diagram of the network architecture of the present invention. As shown in the figure, the network architecture includes: a main controller 10 and a plurality of power units 20, and the main controller 10 is a main controller of flexible direct current transmission. Such as figure 1 As shown, there are n power units, including power unit 1, power unit 2, . . . , power unit n. The main controller 10 communicates with each power unit 20 through an optica...
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