A low-complexity 1-bit signal decoder and its design method

Abstract

A low-complexity 1-bit signal decoder and a design method thereof, the decoder includes a counter module, a fixed subtraction module, M decoder submodules and an output control signal generating module; the counter module inputs a reset signal and a clock signal, the M decoder submodules form a parallel operation processing unit, M-1 fixed subtraction modules are arranged one-to-one between the counter module and the decoder submodule, and the address values ​​of adjacent decoder submodules differ by L; the data inputs of the M decoder submodules are all 1-bit digital signal streams, the enable ends are all connected to the output control signal generating module, and the outputs are all N-bit digital signal streams. The present invention also provides a design method for a low-complexity 1-bit signal decoder. The present invention has extremely low complexity and power consumption, is suitable for high-speed data processing, can be implemented in the form of an integrated circuit, and is suitable for high-bandwidth signal processing.

Description

Technical Field

[0001] The invention belongs to the field of signal processing, and in particular relates to a low-complexity 1-bit signal decoder and a design method thereof. Background Art

[0002] Digital signal processing technology has become increasingly popular, bringing unprecedented progress to many fields. The development of electronic information technology and integrated circuit technology has led to the need to convert analog signals into digital signals in more and more fields in order to further use digital signal processing methods for specific processing. A 1-bit digital stream level signal is a method of transmitting a low-speed analog signal or a low-speed multi-bit digital signal in a high-speed 1-bit logic level jump manner. The above-mentioned 1-bit digital stream level signal can be pulse density modulation (PDM) or pulse width modulation (PWM), but is not limited to the above two signal modulation forms. The converted multi-bit digital signal can be a pulse code modulation signal (PCM), which is also not limited to this possibility.

[0003] The existing technology uses the "filtering + downsampling" operation to complete decoding. In terms of implementation, there are usually two methods: the first is the "decoding algorithm based on multi-stage filters". This method uses cascaded multi-stage low-pass filtering and downsampling. Usually, the multi-stage modules use cascaded comb digital filters and other types of FIR digital filters to complete low-pass filtering, and then downsample by a certain multiple. Then it is sent to the next level of downsampling module. That is, each stage completes low-pass filtering and a certain multiple of downsampling. After multiple stages of cascading, the total downsampling multiple is equal to the product of the downsampling multiples of each stage. Finally, a frequency response compensation filter is used to uniformly correct the non-ideal characteristics of the frequency response curve caused by the previous stage filtering. For example Figure 1 As shown, a filter plus Lp times down-sampling 1-bit digital signal stream to N-bit low-speed signal stream decoder divides the whole process into multiple stages. The filter of each stage can be a FIR low-pass filter, or a CIC (cascaded comb filter) or any type of digital filter module; the last stage is a compensation filter, which is generally used to compensate for the non-ideal characteristics brought by all the previous filters. The main disadvantages of this method are: 1. The structure is complex. Except for the first stage filter input data bit width of 1 bit, the data bit width of the remaining filters is much larger than 1 bit. In order to perform filtering operations, more large-bit width convolution operations must be used, which will occupy more multiplier resources and greatly increase the complexity; 2. Due to the use of a longer order of convolution operations, the multiplication and addition operation logic depth is deeper and the delay is larger, so the processing throughput is not easy to increase, and the high-speed processing performance is limited. 3. The power consumption is large, which is caused by the use of more large-bit width shift registers for digital filtering to realize the signal data path cache at each level.

[0004] The second method is to use the "frequency domain filtering and decoding algorithm" to decode a 1-bit digital signal stream into an N-bit low-speed signal stream. The main disadvantage is that it is relatively complex. Generally, complex digital signal processing methods such as FFT are used to transform the signal filtering and extraction into the frequency domain for processing, and then transform it into the time domain before output. Since such operations require data to be framed and cached, they occupy more logic resources, and it is difficult to control power consumption at a low level. The operating speed and data throughput are also very limited. Summary of the invention

[0005] The purpose of the present invention is to provide a low-complexity 1-bit signal decoder and a design method thereof to address the problems of high complexity, limited operating speed and data throughput of traditional decoding methods in the above-mentioned prior art. The decoder has extremely low complexity and power consumption, is suitable for high-speed data processing, can be implemented in the form of an integrated circuit, and is suitable for high-bandwidth signal processing.

[0006] In order to achieve the above object, the present invention has the following technical solutions:

[0007] A low-complexity 1-bit signal decoder comprises a counter module, M-1 fixed subtraction modules, M decoder submodules and an output control signal generation module, where M is an integer and M≥1;

[0008] The counter module inputs a reset signal and a clock signal with a frequency of Fs, M decoder submodules form a parallel operation processing unit, and M-1 fixed subtraction modules are arranged one by one between the counter module and the second to M decoder submodules; the first decoder submodule directly collects the value output by the counter module as the address input, and the M-1 fixed subtraction modules respectively subtract (j-1)L from the address output by the counter module and send it to the second to M decoder submodules as the address input, 2≤j≤M, L is an integer and L≥1, so that the address values ​​of adjacent decoder submodules differ by L; the data inputs of the M decoder submodules are all 1-bit digital signal streams, the enable output ends are all connected to the output control signal generating module, and the data outputs are all N-bit digital signal streams.

[0009] As a preferred solution of the present invention, the decoder submodule includes a lookup table module, and the counter module counts the rising edge of the input clock signal. When the rising edge of the reset signal arrives, the counter module starts to count cyclically from 0 to M*L-1, and the count value is sent to the lookup table module as the address of the lookup table.

[0010] As a preferred solution of the present invention, the lookup table includes L*M addresses, and the data stored at each address is K bits of data.

[0011] As a preferred solution of the present invention, the decoder submodule includes a K-bit adder, and the output end of the lookup table outputs a corresponding K-bit value according to the address generated by the previous-stage counter. The K-bit value is selected according to whether the current input data is bit 0, i.e., a low level, or bit 1, i.e., a high level, to output the K-bit value of the lookup table directly to the K-bit adder or output its opposite to the K-bit adder.

[0012] As a preferred solution of the present invention, the decoder submodule also includes an enable pulse generating module, and the K-bit adder outputs an N-bit data stream through the K-bit register, the bit width conversion module and the N-bit register in sequence; the enable pulse generating module generates a positive pulse with a width of 1 / Fs when the address input of the lookup table is 0, and this pulse is used to clear the K-bit adder, and is also used as an enable signal of the N-bit register, and also serves as an output enable signal of the decoder submodule.

[0013] As a preferred solution of the present invention, two lookup tables are used, the contents of the two tables are opposite numbers, the address input ends of the two tables are connected to the same counter module output signal, and the output value of which table is sent to the K-bit adder is selected according to whether the current value of the input data stream is bit 0 or bit 1.

[0014] The present invention also provides a design method for a low-complexity 1-bit signal decoder, comprising the following steps:

[0015] Determine the design target performance of the decoder;

[0016] Determine the clock frequency Fs of the 1-bit data stream signal;

[0017] Determine a downsampling rate L of an N-bit output signal stream relative to a 1-bit data stream signal;

[0018] Determine a type of filter coefficients and order;

[0019] If the determined number of filter taps is not an integer multiple of L, the number of filter taps is made M times L by padding zeros on both sides of the coefficients, where M is an integer greater than zero;

[0020] Quantizing the determined L*M tap coefficients of the filter into K bits, and the performance of the filter coefficients after quantization can still meet the design target performance of the decoder;

[0021] The determined L*M tap coefficients are placed in a lookup table, the lookup table has L*M addresses, and each address has K bits of data;

[0022] The counter module is cleared when an external reset pulse signal arrives and adds one when each input clock rising edge arrives until the accumulated value reaches M*L-1 and then resets to zero. This cycle repeats until a reset pulse signal arrives again.

[0023] As a preferred solution of the present invention, M identical decoder sub-modules are connected to a counter module, the data input end of each decoder sub-module is connected to the same 1-bit data input signal, the address input end is connected to the output value of the counter module, and the first decoder sub-module directly collects the address output by the counter module, and the address values ​​of adjacent decoder sub-modules differ by L; each decoder sub-module uses the output value of the lookup table during the period when its address input end increases from 0 to M*L-1, and determines whether the accumulated value needs to be inverted based on the original lookup table output according to the logic level value of the 1-bit input data at the rising edge of the clock with a current frequency of Fs.

[0024] As a preferred solution of the present invention, the enable pulse generating module in each decoder sub-module generates a pulse level signal when the address input signal of the module lookup table is zero, and maintains a low level when the address input signal of the module lookup table is not zero; the register in the K-bit accumulator in each decoder sub-module is cleared when the generated pulse level signal arrives, and in other cases, the input value is accumulated according to the input clock with a frequency of Fs.

[0025] As a preferred solution of the present invention, the N-bit output register in each decoder sub-module is updated when the generated pulse level signal arrives, and its updated value is the register value of the K-bit accumulator, which is processed and transformed into a value with a bit width of N bits; the output control signal generating module selects the N-bit output value of the decoder sub-module to the decoder output signal port when the output enable of each decoder sub-module is at a high level, and the decoder output enable signal is the result of the logical OR of the output enable signals of each decoder sub-module.

[0026] Compared with the prior art, the decoder of the present invention has at least the following beneficial effects: the internal structure has a strong regularity, and the same decoder submodule can be used for multiple instantiations and proper connections and slight modifications to complete, and has strong scalability. At the same time, since the various decoder submodules work in parallel, the same parts can be fully reused. For example, the counter module and the lookup table module can be fully reused between different decoder submodules to minimize complexity. The decoder of the present invention does not use a multiplier at all when implementing the low-pass filtering and downsampling functions, because the present invention fully utilizes the characteristic that the PDM signal is only 1 bit, and changes the traditional multi-stage filtering extraction into a single-stage filtering extraction, so that all the multiplication operations of the filter tap data and the coefficients are simplified to the operation of keeping or taking the opposite number, which greatly reduces the complexity of the structure, improves the timing performance of the logic circuit, and can support higher speed and data throughput.

[0027] Furthermore, the decoder of the present invention greatly reduces the use of storage units while achieving equivalent low-pass filtering. On the one hand, the equivalent low-pass filtering requires the use of an M*L bit shift register to store the data to be filtered, which not only consumes storage resources, but also increases power consumption because the shift register will almost completely flip in each clock cycle. The present invention cleverly equates the filtering convolution operation to an accumulation operation, avoids the use of a long-order shift register, and saves power consumption and storage resources.

[0028] Compared with the prior art, the design method of the present invention has at least the following beneficial effects: parameterized design can be performed according to the performance requirements of the decoder for the application, and a trade-off between complexity and performance can be made by selecting different parameters to obtain a decoder design instantiation and implementation instantiation that meets the requirements. For example, a decoder with better output signal-to-noise ratio and nonlinear distortion performance can be obtained by increasing the number of low-pass filter taps M*L, and the complexity of the decoder will not increase significantly. The selection of parameters is flexible enough, and there is no constraint requirement on L, which is different from the existing method that requires L=2^P, where P is a positive integer. The present invention has higher parameter flexibility, is suitable for a wider range of application requirements, and has better customized design optimization. Compared with the existing methods, the present invention has low implementation complexity, and the maximum logic depth in the timing circuit is greatly reduced, making it possible to work at a higher clock frequency. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 Existing decoding flow chart based on multi-stage filter;

[0030] Figure 2 The low complexity 1-bit signal decoding flow chart of the present invention;

[0031] Figure 3A schematic diagram of the structure of a low-complexity 1-bit signal decoder according to the present invention;

[0032] Figure 4 A schematic diagram of the structure of a decoder submodule of the present invention;

[0033] Figure 5 Timing diagram of signals in various modules of the decoder of the present invention. DETAILED DESCRIPTION

[0034] The present invention is further described in detail below in conjunction with the accompanying drawings.

[0035] When used to transmit low-speed multi-bit digital signals, a low-speed digital signal representing the amplitude of each sampling point with N bits per sampling point is used as the input of a specific digital encoder, and the output of the encoder is a high-speed 1-bit digital stream signal, the spectrum of which contains the complete spectrum of the original N-bit digital signal and some additional high-frequency interference energy introduced by the encoder. Since the interference energy is in the high-frequency part and is separated from the spectrum of the signal in the spectrum, the 1-bit signal can be filtered out or suppressed by a simple analog filter to obtain the corresponding original analog signal.

[0036] On the other hand, it is known that when an analog signal can be converted into a sequence of 0 and 1 bits driven by a clock much larger than the signal bandwidth by a specific modulator, the 1-bit digital stream signal is considered to be a digital signal. This has the advantage of being conducive to long-distance transmission without causing any damage to the in-band signal spectrum shape, and can be completed with only one data signal line and one clock signal line. In order to facilitate the subsequent digital signal processing, a specific decoder is also required to convert the high-speed 1-bit signal into a digital signal with a lower speed of N bits. Therefore, the 1-bit digital stream signal can be regarded as a special digitization method for analog signals. The performance of the above-mentioned specific decoder determines the upper rate limit, signal-to-noise ratio, nonlinear distortion and other performance indicators of the N-bit width signal, which is also the main inventive point of the present invention. Taking the digital decoding of a 1-bit PDM signal as an example, using a decoder module to perform full digital decoding on a 1-bit PDM signal can obtain an N-bit signal with a sampling rate reduced by L times.

[0037] The present invention proposes a method for converting and decoding a 1-bit signal to a multi-bit digital signal. The decoding method has extremely low complexity and power consumption, and is very suitable for high-speed data processing. Because of its simple structure and strong regularity, it is very suitable for implementation in the form of an integrated circuit. The present invention can be applied to audio signals or higher bandwidth signal processing applications.

[0038] The meanings of the parameters involved below are as follows:

[0039] Fs——bit clock rate of 1-bit data stream;

[0040] L——downsampling rate;

[0041] M is the number of decoder submodules working in parallel inside this decoder;

[0042] K – the bit width of the accumulator inside the decoder submodule;

[0043] N——Decoder output sampling signal bit width, N>1;

[0044] The technical solution of the present invention describes a method for converting a 1-bit digital stream signal with a bit rate of Fs into a downsampled signal with a rate L times lower, and each sampling point of the downsampled signal is an N-bit digital signal. The method has the characteristics of low complexity and configurability, and due to its special implementation method, it is particularly suitable for implementation in FPGA or in a dedicated integrated circuit, and can achieve higher processing speed and data throughput. Therefore, it can be used not only for processing low-speed signals, but also for processing high-speed signals. The following steps can be used to convert a 1-bit digital signal stream with a bit sampling clock rate of Fs into an N-bit digital signal with a sampling clock of Fs / L. This function is the main function of the present invention. Figure 2 As shown, the input signal of the decoder includes a "1-bit data stream" and a clock signal with a frequency of Fs synchronized therewith; the output signal is an output enable signal and an N-bit data stream signal synchronized therewith. The output enable signal can be regarded as a periodic pulse signal with a frequency of Fs / L. During the period when the enable signal is at a high level, the N-bit data at the output end is valid.

[0045] The operation in the decoder can be regarded as a parallel operation process composed of M (M is an integer and M>=1) modules of the same structure combined in a specific way, such as Figure 3 As shown. A low-complexity 1-bit signal decoder comprises a counter module, M-1 fixed subtraction modules, M decoder submodules and an output control signal generating module, M is an integer and M≥1; the counter module inputs a reset signal and a clock signal with a frequency of Fs, the M decoder submodules form a parallel operation processing unit, and the M-1 fixed subtraction modules are arranged one by one between the counter module and the second to M decoder submodules; the first decoder submodule directly collects the value output by the counter module as an address, and the M-1 fixed subtraction modules respectively subtract (j-1)L (where j=2, 3, ...M) from the address output by the counter module and send it to the second to M decoder submodules as address input, L is an integer and L≥1, so that the address values ​​of adjacent decoder submodules differ by L; the data inputs of the M decoder submodules are all 1-bit digital signal streams, the enable output ends are all connected to the output control signal generating module, and the data outputs are all N-bit digital signal streams.

[0046] Each decoder submodule is exactly the same inside. The decoder submodule includes a lookup table module. The counter module counts the rising edge of the input clock signal. When the rising edge of the reset signal arrives, the counter module starts counting in a cycle from 0 to M*L-1, and the count value is sent to the lookup table module as the address of the lookup table.

[0047] The lookup table contains L*M addresses, and the data stored at each address is a K-bit data. The decoder submodule includes a K-bit adder, and the output end of the lookup table outputs the corresponding K-bit value according to the address generated by the previous stage counter. The K-bit value is selected to output the K-bit value of the lookup table directly to the K-bit adder or output its inverse to the K-bit adder according to whether the current input data is bit 0, i.e., low level, or bit 1, i.e., high level.

[0048] Another way to perform equivalent operations is to use two lookup tables. The contents of the two lookup tables are opposite numbers. The address inputs of the two tables are connected to the same counter module output signal. Depending on whether the current value of the input data stream is bit 0 or bit 1, the output value of which table is sent to the K-bit adder is selected.

[0049] The decoder submodule also includes an enable pulse generating module. The K-bit adder outputs an N-bit data stream through a K-bit register, a bit width conversion module and an N-bit register in sequence. The enable pulse generating module generates a positive pulse with a width of 1 / Fs when the address input of the lookup table is 0. This pulse is used to clear the K-bit adder, and is also used as an enable signal for the N-bit register, and also as an output enable signal for the decoder submodule.

[0050] An example is given of a design method for a low-complexity 1-bit signal decoder, comprising the following steps:

[0051] 1. First, determine the design target performance of the decoder, including output signal-to-noise ratio, output THD and other performance index requirements.

[0052] 2. Determine the clock rate Fs of the 1-bit data stream signal;

[0053] 3. Determine the downsampling rate L of the N-bit output signal stream relative to the 1-bit data stream signal;

[0054] 4. Determine the coefficients and order of a FIR type filter. Determine a set of filter coefficients through possible filter design methods, methods, tools, etc., and the filter with these coefficients can meet the target performance of the filter decoder design.

[0055] 5. If the number of FIR filter taps determined in the previous step is not an integer multiple of L, the number of FIR taps can be made M times L by padding zeros on both sides of the coefficients, where M is an integer greater than zero.

[0056] 6. Quantize the L*M tap coefficients of the filter determined in the previous step into K bits, and ensure that the performance of the filter coefficients after quantization can still meet the performance to be achieved in step 1.

[0057] 7. Place the L*M tap coefficients determined in the previous step into the lookup table. At this time, the lookup table has L*M addresses, and each address bit has K bits of data.

[0058] 8. The counter module is cleared when the external reset pulse signal arrives and adds one when each input clock rising edge arrives, until the accumulated value reaches M*L-1 and then resets to zero, and repeats this cycle until the reset pulse signal arrives again.

[0059] 9. Put M identical decoder submodules ( Figure 4 )according to Figure 3 The data input of each decoder submodule is connected to the same 1-bit data input signal. The address input of each decoder submodule is connected to the counter output value, the counter output value offset L, the counter output value offset 2L, and so on, until the address input of the last decoder submodule is connected to the value of the counter output value offset (M-1)L.

[0060] 10. Each decoder submodule determines whether the value sent to the accumulator needs to be inverted based on the original lookup table output value during the period when its address input terminal changes incrementally from 0 to M*L-1 according to the logic level value of the 1-bit input data at the rising edge of the current clock (frequency Fs).

[0061] 11. The enable pulse generating module in each decoder submodule generates a pulse level signal when the address input signal of the lookup table of this module is zero, and maintains a low level when the address input signal of the lookup table of this module is not zero.

[0062] 12. The register in the K-bit accumulator in each decoder submodule is cleared when the pulse signal generated in the previous step arrives, and in other cases, the input value is accumulated according to the input clock (frequency Fs).

[0063] 13. The N-bit output register in each decoder submodule is updated when the pulse generated in step 11 arrives. The updated value is the register value of the K-bit accumulator, which is transformed into a value with a bit width of N bits after necessary processing, usually K>N.

[0064] 14. The output control signal generating module in the decoder module selects the N-bit output value of each decoder submodule to the decoder output signal port when the output enable of each decoder submodule is high. At the same time, the decoder output enable signal is the result of the logical OR of the output enable signals of each decoder submodule.

[0065] The timing diagram of the signals in all the above modules is as follows Figure 5 Assuming M=4, it can be seen that after the external reset pulse arrives, the decoder outputs v(1), v(2), v(3)... (v(n) is the number of N bits) in sequence. The output value change interval is synchronized with the decoder output enable signal pulse generation, and the interval is L clock cycles with a frequency of Fs.

[0066] The main features of the present invention described above include the following aspects:

[0067] 1) Only one-stage filter is used to filter the 1-bit data stream and then L-fold downsampling is performed, instead of using a multi-stage structure.

[0068] 2) The downsampling rate L can be any positive integer without any other constraints.

[0069] 3) The digital operation inside the decoder module in the present invention does not include a multiplier. The present invention completes the filtering operation in the filter through the controlled coordination of a lookup table and an accumulator.

[0070] 4) The present invention converts the serial operation of hierarchical filtering and extraction of the data path in the prior art into an M-way parallel operation path, which greatly improves the operation efficiency of the module, makes the circuit timing performance better, and is more suitable for high-speed signal processing and application.

[0071] 5) The equivalent operation result output of the digital FIR filter is realized, but the shift register or memory unit with the same length as the filter order is not used, and only a small number of registers are used to temporarily store the output result. Therefore, the present invention has the advantages of low implementation complexity and low power consumption.

[0072] 6) The design method included in the present invention is a systematic design method, which can control the overall performance by adjusting the design parameters (M, N, K) according to the design target requirements.

[0073] The above description is only a preferred embodiment of the present invention and is not intended to impose any limitation on the technical solution of the present invention. Those skilled in the art should understand that, without departing from the spirit and principles of the present invention, the technical solution can also be subjected to several simple modifications and substitutions, and these modifications and substitutions will also fall within the scope of protection covered by the claims.

Claims

1. A low complexity 1-bit signal decoder, characterized in that: It includes a counter module, M-1 fixed subtraction modules, M decoder submodules and an output control signal generation module, where M is an integer and M≥1; The counter module inputs a reset signal and a clock signal with a frequency of Fs, and M decoder submodules form a parallel operation processing unit. M-1 fixed subtraction modules are arranged one by one between the counter module and the second to M decoder submodules; the first decoder submodule directly collects the value output by the counter module as the address input, and the M-1 fixed subtraction modules respectively subtract (j-1)L from the address output by the counter module and send it to the second to M decoder submodules as the address input, 2≤j≤M, L is an integer and L≥1, so that the address values ​​of adjacent decoder submodules differ by L; the data inputs of the M decoder submodules are all 1-bit digital signal streams, the enable output ends are all connected to the output control signal generation module, and the data outputs are all N-bit digital signal streams; The decoder submodule includes a lookup table module. The counter module counts the rising edge of the input clock signal. When the rising edge of the reset signal arrives, the counter module starts to count cyclically from 0 to M*L-1, and the count value is sent to the lookup table module as the address of the lookup table. The lookup table contains L*M addresses, and the data stored at each address is a K-bit data; The decoder submodule includes a K-bit adder, and the output end of the lookup table outputs a corresponding K-bit value according to the address generated by the previous stage counter. The K-bit value is selected according to whether the current input data is bit 0, i.e., a low level, or bit 1, i.e., a high level, to select whether to output the K-bit value of the lookup table directly to the K-bit adder or output its inverse to the K-bit adder; Alternatively, two lookup tables are used, the contents of the two tables are opposite numbers, the address inputs of the two tables are connected to the same counter module output signal, and the output value of which table is sent to the K-bit adder is selected according to whether the current value of the input data stream is bit 0 or bit 1; The decoder submodule also includes an enable pulse generation module. The K-bit adder sequentially passes through the K-bit register, the bit width conversion module and the N-bit register to output an N-bit data stream. The enable pulse generation module generates a positive pulse with a width of 1 / Fs when the address input of the lookup table is 0. This pulse is used to clear the K-bit adder, and is also used as an enable signal of the N-bit register, and also as an output enable signal of the decoder submodule. The counter module and the lookup table module can be reused between different decoder sub-modules to reduce complexity.

2. A design method for a low-complexity 1-bit signal decoder as claimed in claim 1, characterized in that: The following steps are involved: Determine the design target performance of the decoder; Determine the clock frequency Fs of the 1-bit data stream signal; Determine a downsampling rate L of an N-bit output signal stream relative to a 1-bit data stream signal; Determine a type of filter coefficients and order; If the determined number of filter taps is not an integer multiple of L, the number of filter taps is made M times L by padding zeros on both sides of the coefficients, where M is an integer greater than zero; Quantizing the determined L*M tap coefficients of the filter into K bits, and the performance of the filter coefficients after quantization can still meet the design target performance of the decoder; The determined L*M tap coefficients are placed in a lookup table, the lookup table has L*M addresses, and each address has K bits of data; The counter module is cleared when an external reset pulse signal arrives and adds one when each input clock rising edge arrives until the accumulated value reaches M*L-1 and then resets to zero. This cycle repeats until a reset pulse signal arrives again.

3. The design method of a low-complexity 1-bit signal decoder according to claim 2, characterized in that: Connect M identical decoder submodules to the counter module, connect the data input end of each decoder submodule to the same 1-bit data input signal, connect the address input end to the counter module output value, and make the first decoder submodule directly collect the address output by the counter module, and the address values ​​of adjacent decoder submodules differ by L; Each decoder submodule uses the output value of the lookup table during the period when its address input terminal changes incrementally from 0 to M*L-1, and determines whether the accumulated value needs to be inverted based on the original lookup table output according to the logic level value of 1 bit of input data at the rising edge of the clock with the current frequency Fs.

4. The design method of a low-complexity 1-bit signal decoder according to claim 2, characterized in that: The enable pulse generating module in each decoder submodule generates a pulse level signal when the address input signal of the lookup table of this module is zero, and maintains a low level when the address input signal of the lookup table of this module is not zero; The register in the K-bit accumulator in each decoder submodule is cleared when the generated pulse level signal arrives, and in other cases, the input value is accumulated according to the input clock with a frequency of Fs.

5. The design method of a low-complexity 1-bit signal decoder according to claim 2, characterized in that: The N-bit output register in each decoder submodule is updated when the generated pulse level signal arrives, and the updated value is the register value of the K-bit accumulator, which is processed and transformed into a value with a bit width of N bits; The output control signal generating module selects the N-bit output value of each decoder submodule to the decoder output signal port when the output enable of each decoder submodule is at a high level. The decoder output enable signal is the logical OR result of the output enable signals of each decoder submodule.

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