LED drive circuit

Abstract

The embodiment of the present invention discloses an LED driving circuit, comprising: a signal receiving module, the signal receiving module is used to receive a row driving signal, a first column driving signal and a second column driving signal; a signal holding module, the signal holding module is used to hold the first column driving signal according to the row driving signal; an adjustment module, the adjustment module is connected to an LED chip, the adjustment module is used to receive an adjustment signal, and drive the LED chip to emit light according to the first column driving signal, the second column driving signal and the adjustment signal. The LED driving circuit provided by the embodiment of the present invention can simultaneously realize the driving of a Micro-LED display screen with high pixel density and large area, and can also realize low power consumption and high efficiency driving, so that the Micro-LED display module has better brightness uniformity and contrast.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor technology, and in particular to an LED driving circuit. Background Art

[0002] Micro Light-Emitting Diode (Micro-LED) has the characteristics of self-luminous display. It is a fully solid-state light-emitting diode with long life, high brightness, low power consumption, small size, and ultra-high resolution. It can be used in extreme environments such as high temperature or radiation. More and more manufacturers have planned it as a new generation of display technology.

[0003] Micro-LED products can be divided into two directions: micro displays with high pixel density (PPI (Pixels Per Inch)>1000) Micro-LED arrays and larger display screens with low pixel density (PPI<1000) Micro-LED arrays. Therefore, the driving methods for Micro-LEDs are divided into high pixel density display driving and low pixel density display driving. However, both high pixel density display driving and low pixel density display driving cannot achieve the driving of large-area display screens with high pixel density. Summary of the invention

[0004] In view of this, an embodiment of the present invention provides an LED driving circuit to achieve high pixel density and large area Micro-LED array driving.

[0005] An embodiment of the present invention provides an LED driving circuit, comprising:

[0006] A signal receiving module, the signal receiving module is used to receive a row driving signal, a first column driving signal and a second column driving signal;

[0007] a signal holding module, the signal holding module being used to hold the first column driving signal according to the row driving signal;

[0008] The regulating module is connected to the LED chip, and is used to receive a regulating signal, and drive the LED chip to emit light according to the first column driving signal, the second column driving signal and the regulating signal.

[0009] Furthermore, the signal receiving module includes a first NMOS tube and a second NMOS tube, the gate of the first NMOS tube and the gate of the second NMOS tube are connected and used to receive a row drive signal, the drain of the first NMOS tube is used to receive a first column drive signal, and the drain of the second NMOS tube is used to receive a second column drive signal.

[0010] Further, the signal holding module includes a first PMOS tube, a second PMOS tube, a third NMOS tube and a fourth NMOS tube;

[0011] The gate of the first PMOS tube, the gate of the third NMOS tube, the drain of the second PMOS tube and the drain of the fourth NMOS tube are connected;

[0012] The gate of the second PMOS tube, the gate of the fourth NMOS tube, the drain of the first PMOS tube and the drain of the third NMOS tube are connected;

[0013] The gate of the third NMOS tube is connected to the source of the first NMOS tube, and the gate of the fourth NMOS tube is connected to the source of the second NMOS tube;

[0014] The drain of the first PMOS tube is connected to the drain of the third NMOS tube, and the drain of the second PMOS tube is connected to the drain of the fourth NMOS tube;

[0015] The source of the first PMOS tube and the source of the second PMOS tube are both connected to the positive electrode of the working power supply;

[0016] The source of the third NMOS tube and the source of the fourth NMOS tube are both connected to the negative electrode of the working power supply.

[0017] Furthermore, the regulating module includes a third PMOS tube and a fourth PMOS tube, the gate of the third PMOS tube is used to receive the regulating signal, the source of the third PMOS tube is connected to the positive electrode of the working power supply, the drain of the third PMOS tube is connected to the source of the fourth PMOS tube, the gate of the fourth PMOS tube is connected to the gate of the third NMOS tube, and the drain of the fourth PMOS tube is connected to the LED chip.

[0018] Furthermore, the LED driving circuit also includes a column scanning module, which includes a shift register and a latch, the data input end of the shift register receives a column control signal, the data output end of the shift register is connected to the data input end of the latch, and the data output end of the latch outputs a first column driving signal.

[0019] Furthermore, the first column driving signal is input into an inverter to obtain a second column driving signal.

[0020] Furthermore, the LED driving circuit also includes an adjustment signal generating circuit, and the adjustment signal generating circuit includes a control circuit, a current regulating circuit, a decoder circuit and a mirror circuit;

[0021] The current regulating circuit is used to generate a regulating current;

[0022] The mirror circuit is used to replicate the regulated current to generate a plurality of mirror currents;

[0023] The decoder circuit includes a plurality of switches, and the decoder circuit generates a regulation signal based on a plurality of the mirror currents according to the number of closures of the switches;

[0024] The control circuit is used for outputting the adjustment signal according to the control signal.

[0025] Furthermore, the current regulation circuit includes a power supply, a current adder, a current subtractor and an NMOS tube; the current adder is used to generate a current addition signal, the current subtractor is used to generate a current subtraction signal, the current addition signal is subtracted from the current subtraction signal to generate a regulation current, and the regulation current is input into the mirror circuit via the power supply and the NMOS tube.

[0026] Furthermore, the mirror circuit includes a plurality of NMOS tubes, the base of each NMOS tube is connected to the current regulating circuit, the source of each NMOS tube is grounded, and the drain of each NMOS tube is connected to the corresponding switch in the decoder circuit.

[0027] Furthermore, the decoder circuit also includes a plurality of decoders connected in series, and a data output terminal of each decoder is connected to a switch and then connected to a data input terminal of the next decoder.

[0028] The LED driving circuit provided in the embodiment of the present invention can simultaneously realize the driving of a Micro-LED display screen with high pixel density and large area, and can also realize low power consumption and high efficiency driving, so that the Micro-LED display module has better brightness uniformity and contrast. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 A schematic diagram of a module of an LED driving circuit provided in Embodiment 1 of the present invention;

[0030] Figure 2 A circuit structure diagram of an LED driving circuit provided in Embodiment 1 of the present invention;

[0031] Figure 3 A circuit structure diagram of a column scanning sub-circuit provided in Embodiment 2 of the present invention;

[0032] Figure 4 A circuit structure diagram of a row scanning circuit provided in Embodiment 3 of the present invention;

[0033] Figure 5 A circuit structure diagram of a regulating signal generating circuit provided in Embodiment 4 of the present invention;

[0034] Figure 6 A circuit structure diagram of a current regulating circuit provided in Embodiment 4 of the present invention;

[0035] Figure 7 A circuit structure diagram of a decoder circuit provided in Embodiment 4 of the present invention;

[0036] Figure 8 A timing diagram of a column scanning subcircuit provided in Embodiment 5 of the present invention;

[0037] Fig. 9 A timing diagram of a row scanning circuit provided in Embodiment 5 of the present invention;

[0038] Fig.10 A row and column scanning timing diagram of an LED driving circuit provided in Embodiment 5 of the present invention;

[0039] Fig.11 This is a timing diagram of a 120 Hz refresh rate provided in Embodiment 5 of the present invention. DETAILED DESCRIPTION

[0040] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0041] Before discussing the exemplary embodiments in more detail, it should be mentioned that some exemplary embodiments are described as processes or circuits depicted as flow charts. Although the flow charts describe the steps as sequential processes, many of the steps therein can be implemented in parallel, concurrently or simultaneously. In addition, the order of the steps can be rearranged. The process can be terminated when its operation is completed, but it can also have additional steps not included in the accompanying drawings. The process can correspond to a circuit, a function, a procedure, a subroutine, a subprogram, etc.

[0042] In addition, the terms "first", "second", etc. may be used in this article to describe various directions, actions, steps or elements, but these directions, actions, steps or elements are not limited by these terms. These terms are only used to distinguish a first direction, action, step or element from another direction, action, step or element. The terms "first", "second", etc. should not be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "multiple" and "batch" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0043] Embodiment 1

[0044] Figure 1 This is a schematic diagram of an LED driving circuit provided in Example 1 of the present invention. This embodiment can be applied to driving a Micro-LED array with high pixel density and large area, such as driving a Micro-LED matrix with a pixel density of 5000PPI and a resolution of 1920x1080.

[0045] like Figure 1 As shown, the LED driving circuit provided in the first embodiment of the present invention includes: a signal receiving module 10, a signal holding module 20 and an adjustment module 30, the signal receiving module 10 is used to receive a row driving signal, a first column driving signal and a second column driving signal; the signal holding module 20 is used to hold the first column driving signal according to the row driving signal; the adjustment module 30 is connected to the LED chip, the adjustment module 30 is used to receive the adjustment signal, and drive the LED chip to emit light according to the first column driving signal, the second column driving signal and the adjustment signal.

[0046] The row drive signal is the drive signal of the row where the LED chip is located in the LED array, the first column drive signal is the drive signal of the column where the LED chip is located in the LED array, and the second column drive signal is the opposite signal to the first column drive signal. The adjustment signal is used to adjust the luminous brightness of the LED chip. The signal holding module 20 can maintain the first column drive signal for a period of time, thereby extending the luminous time of the LED chip and making the display screen emit light more evenly.

[0047] For further reference, Figure 2 . Figure 2 A circuit diagram of an LED driving circuit provided in Embodiment 1 of the present invention.

[0048] The signal receiving module 10 includes a first NMOS transistor NMOS1 and a second NMOS transistor NMOS2. The gate of the first NMOS transistor NMOS1 is connected and used to receive the row drive signal Row1, the drain of the first NMOS transistor NMOS1 is used to receive the first column drive signal Data1, and the drain of the second NMOS transistor NMOS2 is used to receive the second column drive signal Data_1.

[0049] The signal holding module 20 includes a first PMOS tube PMOS1, a second PMOS tube PMOS2, a third NMOS tube NMOS3 and a fourth NMOS tube NMOS4; the gate of the first PMOS tube PMOS1, the gate of the third NMOS tube NMOS3, the drain of the second PMOS tube PMOS2 and the drain of the fourth NMOS tube NMOS4 are connected; the gate of the second PMOS tube PMOS2, the gate of the fourth NMOS tube NMOS4, the drain of the first PMOS tube PMOS1 and the drain of the third NMOS tube NMOS3 are connected; the gate of the third NMOS tube NMOS3 The gate of the first NMOS tube NMOS1 is connected to the source of the first NMOS tube NMOS1, and the gate of the fourth NMOS tube NMOS4 is connected to the source of the second NMOS tube NMOS2; the drain of the first PMOS tube PMOS1 is connected to the drain of the third NMOS tube NMOS3, and the drain of the second PMOS tube PMOS2 is connected to the drain of the fourth NMOS tube NMOS4; the source of the first PMOS tube PMOS1 and the source of the second PMOS tube PMOS2 are both connected to the positive working power supply VDD; the source of the third NMOS tube NMOS3 and the source of the fourth NMOS tube NMOS4 are both connected to the negative working power supply VSS.

[0050] The regulating module 30 includes a third PMOS tube PMOS3 and a fourth PMOS tube PMOS4, the gate of the third PMOS tube PMOS3 is used to receive the regulating signal Iref, the source of the third PMOS tube PMOS3 is connected to the positive electrode of the working power supply, the drain of the third PMOS tube PMOS3 is connected to the source of the fourth PMOS tube PMOS4, the gate of the fourth PMOS tube PMOS4 is connected to the gate of the third NMOS tube NMOS3, and the drain of the fourth PMOS tube PMOS4 is connected to the LED chip.

[0051] exist Figure 2 In the LED driving circuit shown, when the row driving signal Row1 = 0, the EN signal maintains the original state of 0 or 1.

[0052] When the row driving signal Row1 = 1, the first column driving signal Data1 and the second column driving signal Data_1 are transmitted to the signal holding module 20 , so that the EN signal follows the second column driving signal Data_1 .

[0053] When the row drive signal Row1=1, the first column drive signal Data1=1, and the second column drive signal Data_1=0, EN=0, the fourth PMOS tube PMOS4 is turned on, and the first column drive signal Data1 is combined with the adjustment signal Iref to control the state of the LED chip. The larger the voltage (VDD-Iref) of the adjustment signal Iref, the larger the current flowing through the LED chip, and the greater the brightness of the LED chip, so the brightness of the LED chip can be adjusted by changing the adjustment signal Iref.

[0054] The LED driving circuit provided in the embodiment of the present invention is a driving circuit for a single LED chip. When driving an LED array, each LED chip is connected to the LED driving circuit provided in the embodiment of the present invention. According to the number n of the LED chip in the LED array, the corresponding row driving signal is recorded as Rown, the first column driving signal is recorded as Datan, and the second column driving signal is recorded as Data_n.

[0055] The LED driving circuit provided in the embodiment of the present invention can simultaneously realize the driving of a Micro-LED display screen with high pixel density and large area, and can also realize low power consumption and high efficiency driving, so that the Micro-LED display module has better brightness uniformity and contrast.

[0056] Embodiment 2

[0057] refer to Figure 3 On the basis of the above embodiments, the LED driving circuit provided in the second embodiment of the present invention further includes a column scanning module 40. The column scanning module 40 includes a shift register diff1 and a latch diff_d1, the data input terminal D of the shift register diff1 receives the column control signal Data, the data output terminal of the shift register diff1 is connected to the data input terminal D1 of the latch, and the data output terminal of the latch diff_d1 outputs the first column driving signal Data1.

[0058] The shift register diff1 further includes a reset terminal R and a clock signal terminal C, and the latch diff_d1 also includes a reset terminal R1 and a clock signal terminal C1. The reset terminal R of the shift register diff1 and the reset terminal R1 of the latch diff_d1 are connected to the same reset signal Reset, the clock signal terminal C of the shift register diff1 is connected to the first clock signal CLK_D, and the clock signal terminal C1 of the latch diff_d1 is connected to the second clock signal CLK_L.

[0059] When the column scanning module 40 is working, when the first clock signal CLK_D is a rising edge, the data output end of the shift register diff1 samples the column control signal Data received by its data input end D, and the sampled data is stored at its data output end. At the same time, when the second clock signal CLK_L is a rising edge, the data output end of the latch diff_d1 samples the signal of the data output end of the shift register diff1 and outputs the first column drive signal Data1. The first column drive signal Data1 is input to the drain of the first NMOS tube NMOS1 of the signal receiving module. At the same time, the first column drive signal Data1 is also input to an inverter (not shown in the figure) to obtain a second column drive signal Data_1 opposite to the first column drive signal Data1, and the second column drive signal Data_1 is input to the drain of the second NMOS tube NMOS2 of the signal receiving module.

[0060] In this embodiment, the column scanning module 40 is a column signal generating circuit in the LED driving circuit corresponding to a single LED chip. When driving the LED array, multiple column scanning modules 40 are connected in series to form a column scanning subcircuit, such as Figure 3 As shown, the column scanning subcircuit is a column signal generating circuit for some LED chips in the LED array, and the column scanning circuit composed of multiple parallel column scanning subcircuits is a column signal generating circuit for all LED chips in the LED array.

[0061] refer to Figure 3 In the column scanning sub-circuit, n column scanning modules 40 are included, and the nth column scanning module 40 includes a shift register diffn and a latch diff_dn. The reset terminals R of all shift registers (diff1-diffn) and the reset terminals R1 of all latches (diff_d1-diff_dn) are connected to the same reset signal Reset, the clock signal terminals C of all shift registers (diff1-diffn) are connected to the first clock signal CLK_D, and the clock signal terminals C1 of all latches (diff_d1-diff_dn) are connected to the second clock signal CLK_L. The data input terminal D of the shift register diffi of the i-th column scanning module is connected to the data output terminal of the shift register diffi-1 of the i-1th column scanning module. The data output end of the latch diff_di of the i-th column scanning module outputs the first column driving signal Datai to the drain of the first NMOS tube NMOS1 of the signal receiving module 10 of the i-th LED chip, and at the same time obtains the second column driving signal Data_i through the inverter and inputs it to the drain of the second NMOS tube NMOS2 of the corresponding signal receiving module 10.

[0062] Embodiment 3

[0063] refer to Figure 4On the basis of the above embodiments, the LED driving circuit provided in the third embodiment of the present invention further includes a row scanning module 60. The row scanning module includes a register diff1, which includes an input terminal, a reset terminal, a clock signal terminal and an output terminal, wherein the reset terminal is connected to the reset signal Reset, the clock signal terminal is connected to the clock signal CLK, and the input terminal is connected to the row signal Vscan. When the clock signal CLK is at a rising edge, the register diff1 samples the row signal Vscan at the input terminal, and the output terminal thereof outputs the row driving signal Row1 to the gate of the first NMOS tube NMOS1 and the gate of the second NMOS tube NMOS2 of the signal receiving module 10.

[0064] The row scanning module 60 is a row driving signal generating circuit corresponding to a single LED chip. When driving the LED array, n row scanning modules 60 are connected in series to form a row scanning circuit for the entire LED array. Figure 4 As shown. The reset terminals of all registers (diff1 to diffn) are connected to the reset signal Reset, the clock signal terminals of all registers (diff1 to diffn) are connected to the clock signal CLK, the input terminal of the first register diff1 is connected to the row signal Vscan, the input terminal of the i-th register diffi is connected to the output terminal of the i-1-th register diffi-1, and the output terminal of the i-th register diffi outputs the row drive signal Rowi to the gate of the first NMOS tube NMOS1 and the gate of the second NMOS tube NMOS2 of the signal receiving module 10 corresponding to the i-th LED chip.

[0065] Embodiment 4

[0066] refer to Figure 5 On the basis of the above embodiments, the LED driving circuit provided in the fourth embodiment of the present invention further includes an adjustment signal generating circuit. The adjustment signal generating circuit includes a control circuit 54, a current adjustment circuit 51, a decoder circuit 53 and a mirror circuit 52, and the mirror circuit 52 is connected to the control circuit 54 through the decoder circuit 53.

[0067] The current regulating circuit 51 generates a regulating current Iin. Further, the specific structure of the current regulating circuit 51 can be referred to Figure 5 .like Figure 6As shown, the current regulating circuit 51 includes a power supply 511, a current adder 512, a current subtractor 513 and an NMOS tube NM0. The current adder 512 includes two input terminals: a current input terminal I_plus and a reset terminal I_reset. The current signal of the current input terminal I_plus is valid on the rising edge, and its output current plus signal Ip. The current subtractor 513 includes two input terminals: a current input terminal I_minus and a reset terminal I_reset. The current signal of the current input terminal I_minus is valid on the rising edge, and its output current minus signal In. The current plus signal Ip and the current minus signal In are subtracted to obtain the regulating current Iin, that is, Iin=Ip-In, and then input to the NMOS tube NM0 through the power supply 511. The reset signal of the reset terminal I_reset: 0=0V, 1=vdd, the maximum regulating level of the regulating current Iin is ±20 levels.

[0068] Further, the working principle of the current regulating circuit 51 is as follows: reset signal = 0, the regulating current Iin is reset. Reset signal = 1, the current signal of the current input terminal I_plus of the current adder 512 = 0, and the rising edge of the current signal of the current input terminal I_minus of the current subtractor 513 can reduce the regulating current Iin. Reset signal = 1, the current signal of the current input terminal I_plus of the current adder 512 = 1, and the rising edge of the current signal of the current input terminal I_minus of the current subtractor 513 resets the regulating current Iin. Reset signal = 1, the current signal of the current input terminal I_minus of the current subtractor 513 = 0, and the rising edge of the current signal of the current input terminal I_plus of the current adder 512 can increase the regulating current Iin. Reset signal = 1, the current signal of the current input terminal I_minus of the current subtractor 513 = 1, and the rising edge of the current signal of the current input terminal I_plus of the current adder 512 resets the current Iin.

[0069] The mirror circuit 52 includes a plurality of NMOS transistors (NM1 to NMn), each of which can copy the adjustment current Iin to obtain a mirror current of the same magnitude. The decoder circuit 53 includes a plurality of switches S1 to Sn, and each NMOS transistor in the mirror circuit 52 is connected to a corresponding switch in the decoder circuit 53. When the switch in the decoder circuit 53 is closed, the mirror current of the corresponding NMOS transistor is input to the decoder circuit 53, and the number of closed switches is the number of mirror currents input to the decoder circuit 53. These mirror currents are added together to obtain the adjustment signal Iref. Assuming the number of closed switches is N, Iref = Iin*N.

[0070] For further reference, Figure 7, is a specific circuit diagram of the decoder circuit 53. The decoder circuit 53 includes a plurality of decoders diff1~diffn and a plurality of switches S1~Sn, each of which includes an input terminal D, a reset terminal R, a clock signal terminal C and an output terminal. The reset terminals of all decoders are connected to the reset signal Reset_I, the clock signal terminals of all decoders are connected to the counting signal Data_I, the data input terminal of the first decoder diff1 is connected to the positive electrode of the working power supply VDD, and the input terminal of the i-th decoder diffi is connected to the output terminal of the i-1th decoder diffi-1 through the switch Si-1. When the reset signal Reset_I is at a low level, the reset occurs, and the number of switch closures after reset is 0, then the adjustment signal Iref=0; when the reset signal Reset_I is at a high level, the decoder circuit 53 starts counting, and the rising edge of the counting signal Data_I is increased by 1, then the number of switch closures S is increased by 1, assuming that the number of switch closures is equal to N, then Iref=Iin*N.

[0071] The control circuit 54 includes two PMOS transistors: PMS and PMO, wherein the drains of PMS and PMO are connected and connected to the output end of the decoder circuit 53, the sources of PMS and PMO are connected to the positive electrode VDD of the working current, the gate of PMS is the input end of the control signal Switch_I, and the gate of PMO is the output end of the adjustment signal Iref. The control signal Switch_I is a switch signal for controlling whether the adjustment signal Iref obtained by the decoder circuit 53 is output or not. When the control signal Switch_I is at a high level, the gate of PMO outputs the adjustment signal Iref=Iin*N; when the control signal Switch_I is at a low level, the gate of PMO outputs the adjustment signal Iref=0.

[0072] Embodiment 5

[0073] Combine the following Figure 2-10 The structure of an LED driving circuit according to a specific embodiment of the present invention is described.

[0074] In a specific embodiment, a Micro-LED array with a pixel density of 5000ppi and a resolution of 1920x1080 is driven as an example. Each LED chip in the Micro-LED array is connected as follows. Figure 2 The LED driving circuit shown.

[0075] The column scanning circuit in the LED driving circuit of the Micro-LED array consists of 20 Figure 3The column scanning subcircuit shown is composed of 96 column scanning modules 40, with a total of 96 shift registers and 96 latches. In each column scanning subcircuit, the clock signal terminal C of all shift registers (diff1~diffn) is connected to the first clock signal CLK_D; the clock signal terminal C1 of all latches (diff_d1~diff_dn) is connected to the second clock signal CLK_L; the data input terminal D of the shift register diff1 of the first column scanning module 40 is connected to the column control signal Data, and the data input terminal D of the shift register diffi of the i-th column scanning module 40 is connected to the data output terminal of the shift register diffi-1 of the i-1-th column scanning module (2<i<95). Each column scanning subcircuit has a corresponding column control signal Data, so the column scanning circuit has a total of 20 column control signals Data, which are recorded as Da<1:20>. Each column scanning subcircuit outputs 96 first column driving signals Data1-Data96, which are input into the inverter to obtain 96 first column driving signals Data_1-Data_96. The column scanning circuit composed of 20 column scanning subcircuits outputs 1920 first column driving signals and a first column driving signal.

[0076] When the column scanning sub-circuit is working, the rising edge of the first clock signal CLK_D samples the column control signal Data, and the rising edge of the first clock signal CLK_D is increased by 1, then the column control signal Data is shifted 1 bit from the shift register diffi to diffi+1, first in first out. Every 96 rising edges, the column scanning sub-circuit completes the sampling of 96 bits of data, and the 96 bits of data are recorded from left to right as D<1:96>, and the data D<1:96> is temporarily stored in the output of each latch of the shift register until the next rising edge of the first clock signal CLK_D. The rising edge of the second clock signal CLK_L latches the 96 bits of data D<1:96> stored in the shift register to the output of the latch, and obtains the corresponding first column drive signal, which is recorded from left to right as data<1:96> until the next rising edge of the second clock signal CLK_L. The timing diagram of the column scanning sub-circuit is shown as follows. Figure 8 shown.

[0077] Since the 20 column scanning sub-circuits share the first clock signal CLK_D and the second clock signal CLK_L, 96 rising edges of the first clock signal CLK_D complete the data sampling from the 1st column to the 1920th column, and 1 rising edge of the second clock signal CLK_L stores the sampled data of the 1st column to the 1920th column at the output of the latch.

[0078] The row scanning circuit in the LED driving circuit of the Micro-LED array is as follows Figure 4As shown, it consists of 1080 registers. The reset terminals of all registers (diff1~diffn) are connected to the reset signal Reset, the clock signal terminals of all registers (diff1~diffn) are connected to the clock signal CLK, the input terminal of the first register diff1 is connected to the row signal Vscan, and the input terminal of the i-th register diffi is connected to the output terminal of the i-1-th register diffi-1. The row scanning circuit outputs 1080 row drive signals Row1~Row1080, and each row is 1 in sequence, that is, Row=1 for a row, and Row=0 for the remaining 1079 rows. When Row=1 for a row, the first column drive signal Data<1:1920> of the row is read at the same time and transmitted to the signal receiving module and the signal holding module.

[0079] The row scanning circuit works when the reset signal Reset is at a low level, and after reset, the output Row1-1080=0. When the reset signal Reset is at a high level, the clock signal CLK is sampled at the rising edge, and the data signal at the register input end is transmitted to the output end to form the row drive signal Row1~Row1080. The output signal of the other states is maintained. Fig. 9 This is the timing diagram of the row scanning circuit.

[0080] When the row drive signal Rowi is high, the signal at the latch output (1920 outputs) is transmitted to the signal receiving circuit of the corresponding row i, and finally the Data data is transmitted to the signal holding circuit. This cycle is repeated 1080 times, and then the 1920x1080 pixel matrix reads the adjustment signal Iref at the same time, and the Micro-LED matrix completes a sub-field scan. The sub-field scanning time plus the light-emitting time is a sub-field time, and 8 sub-fields constitute a frame. Fig.10 This is the row and column scanning timing diagram.

[0081] The regulating signal generating circuit includes 512 NMOS tubes, namely NM0 to NM511. NM0 and NM1 to NM511 form a mirror tube to copy the regulating current Iin flowing through NM0 (S1 to S511 are closed). When the control signal Switch_I is at a high level, the regulating signal Iref is equal to the sum of the currents flowing through NM1 to NM511 (Iref = 511 * Iin). When the control signal Switch_I is at a low level, the regulating signal Iref = 0.

[0082] Furthermore, the LED driving circuit provided in this embodiment can realize 256-level grayscale adjustment of an ultra-high-resolution Micro-LED array, for example, 256-level grayscale adjustment of a Micro-LED array with a pixel density of 5000ppi and a resolution of 1920x1080. Grayscale adjustment methods mainly include: PWM (Pulse-Width Modulation), PAM (Pulse-Amplitude Modulation) and PFM (Pulse-Frequency Modulation).

[0083] PWM is to adjust the width of the light-emitting area of ​​each subfield. In this embodiment, 8 subfields (recorded as subfields 1 to 8) form a frame, and the width ratio of the light-emitting area of ​​the 8 subfields is set to 1:2:4:8:16:32:64:128, and the Data input to the 8 subfields is recorded as d1 to d8. Then the grayscale calculation method is: Grayscale (Gray) = 1*d1+2*d2+4*d3+8*d4+16*d5+32*d6+64*d7+128*d8. When the Data input to subfield m is high, dm = 1; when the Data input to the subfield is low, dm = 0. When the Data input to all subfields is high, d1 to d8 are all 1, then Gray = 256; when the Data input to all subfields is low, d1 to d8 are all 0, then Gray = 0.

[0084] PAM is to adjust the amplitude of the light-emitting area adjustment signal Iref of each subfield. Set the amplitude ratio of the light-emitting area adjustment signal Iref of subfields 1 to 8 to 1:2:4:8:16:32:64:128, then 256 levels of gray can be achieved, calculated as follows: Gray (Gray) = 1*d1+2*d2+4*d3+8*d4+16*d5+32*d6+64*d7+128*d8. When the Data input to subfield m is high, dm = 1; when the Data input to the subfield is low, dm = 0. When the Data input to all subfields is high, d1~d8 are all 1, then Gray = 256; when the Data input to all subfields is low, d1~d8 are all 0, then Gray = 0.

[0085] PFM adjusts the scanning area width of each subfield, and fixes the amplitude of the adjustment signal Iref, and sets the width of the light-emitting area to 0, that is, the scanning area width is equal to the subfield width. Then, the width ratio of subfields 1 to 8 is set to 1:2:4:8:16:32:64:128, and 256 levels of gray can be achieved. The calculation method is: Gray (Gray) = 1*d1+2*d2+4*d3+8*d4+16*d5+32*d6+64*d7+128*d8. When the Data input to subfield m is high, dm = 1; when the Data input to the subfield is low, dm = 0. When the Data input to all subfields is high, d1~d8 are all 1, then Gray = 256; when the Data input to all subfields is low, d1~d8 are all 0, then Gray = 0.

[0086] For example, the timing parameters using PAM and 120 Hz refresh rate are as follows:

[0087] For CLK_D, its period T = 5ns, frequency f = 200MHz;

[0088] For CLK_L, its period T = 5*96 = 480ns, frequency f = 2.08MHz;

[0089] For CLK, its period T = 5*96 = 480ns, frequency f = 2.08MHz;

[0090] Among them, the delay between CLK and CLK_L, t = 0 ~ 0.1ns;

[0091] The width of the subfield scanning area is equal to the width of the subfield light emitting area.

[0092] Each frame consists of 8 sub-fields. CLK =5ns, 20 split screens; T frame_sub =T CLK *1080*(1920 / 20)*2=518.4us*2=1.0368ms; the site selection time of each sub-field Micro-LED array is 518.4us, and the light emission time is 518.4us; T frame =T frame_sub *8=8.2944ms≈8.3ms, f frame =120Hz. Its timing diagram is as follows Fig.11 shown.

[0093] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. An LED driving circuit, characterized in that: Used to drive micro light emitting diodes, including: A signal receiving module, the signal receiving module is used to receive a row driving signal, a first column driving signal and a second column driving signal; a signal holding module, the signal holding module being used to hold the first column driving signal according to the row driving signal; an adjusting module, the adjusting module being connected to the LED chip, the adjusting module being used to receive an adjusting signal, and drive the LED chip to emit light according to the first column driving signal, the second column driving signal and the adjusting signal; The signal receiving module includes a first NMOS tube and a second NMOS tube, the gate of the first NMOS tube is connected to the gate of the second NMOS tube and is used to receive a row drive signal, the drain of the first NMOS tube is used to receive a first column drive signal, and the drain of the second NMOS tube is used to receive a second column drive signal; The signal holding module includes a first PMOS tube, a second PMOS tube, a third NMOS tube and a fourth NMOS tube; The gate of the first PMOS tube, the gate of the third NMOS tube, the drain of the second PMOS tube and the drain of the fourth NMOS tube are connected; The gate of the second PMOS tube, the gate of the fourth NMOS tube, the drain of the first PMOS tube and the drain of the third NMOS tube are connected; The gate of the third NMOS tube is connected to the source of the first NMOS tube, and the gate of the fourth NMOS tube is connected to the source of the second NMOS tube; The drain of the first PMOS tube is connected to the drain of the third NMOS tube, and the drain of the second PMOS tube is connected to the drain of the fourth NMOS tube; The source of the first PMOS tube and the source of the second PMOS tube are both connected to the positive electrode of the working power supply; The source of the third NMOS tube and the source of the fourth NMOS tube are both connected to the negative electrode of the working power supply; The regulating module includes a third PMOS tube and a fourth PMOS tube, the gate of the third PMOS tube is used to receive the regulating signal, the source of the third PMOS tube is connected to the positive electrode of the working power supply, the drain of the third PMOS tube is connected to the source of the fourth PMOS tube, the gate of the fourth PMOS tube is connected to the gate of the third NMOS tube, and the drain of the fourth PMOS tube is connected to the LED chip.

2. The LED driving circuit according to claim 1, characterized in that: The LED driving circuit also includes a column scanning module, which includes a shift register and a latch. The data input end of the shift register receives a column control signal, the data output end of the shift register is connected to the data input end of the latch, and the data output end of the latch outputs a first column driving signal.

3. The LED driving circuit according to claim 2, characterized in that: The first column driving signal is input into the inverter to obtain the second column driving signal.

4. The LED driving circuit according to claim 1, characterized in that: The LED driving circuit further includes an adjustment signal generating circuit, and the adjustment signal generating circuit includes a control circuit, a current regulating circuit, a decoder circuit and a mirror circuit; The current regulating circuit is used to generate a regulating current; The mirror circuit is used to replicate the regulated current to generate a plurality of mirror currents; The decoder circuit includes a plurality of switches, and the decoder circuit generates a regulation signal based on a plurality of the mirror currents according to the number of closures of the switches; The control circuit is used for outputting the adjustment signal according to the control signal.

5. The LED driving circuit according to claim 4, characterized in that: The current regulating circuit includes a power supply, a current adder, a current subtractor and an NMOS tube; the current adder is used to generate a current addition signal, the current subtractor is used to generate a current subtraction signal, the current addition signal is subtracted from the current subtraction signal to generate a regulating current, and the regulating current is input into the mirror circuit through the power supply and the NMOS tube.

6. The LED driving circuit according to claim 4, characterized in that: The mirror circuit includes a plurality of NMOS tubes, the base of each NMOS tube is connected to the current regulating circuit, the source of each NMOS tube is grounded, and the drain of each NMOS tube is connected to the corresponding switch in the decoder circuit.

7. The LED driving circuit according to claim 4, characterized in that: The decoder circuit also includes a plurality of decoders connected in series, and the data output end of each decoder is connected to a switch and then connected to the data input end of the next decoder.

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