A pulse width detection circuit

Abstract

The present invention discloses a pulse width detection circuit. The edge conversion circuit in the present application can control the charging and discharging of a capacitor in a capacitor power regulation circuit based on the pulse width of a digital signal, and then the triangular wave generated in the capacitor is processed by a hysteresis comparator. Finally, the pulse width of the digital signal can be judged by the output waveform of the hysteresis comparator. Since the capacitor power regulation circuit and the hysteresis comparator in the present application are both analog circuits, and the edge conversion circuit can also be selected to be an analog circuit, due to the characteristics of the analog circuit itself, the pulse width detection circuit in the present application is less affected by process accuracy, temperature and power supply voltage, thereby improving the accuracy of pulse width detection.

Description

Technical Field

[0001] The invention relates to the field of pulse width detection, in particular to a pulse width detection circuit. Background Art

[0002] In many application scenarios, when processing digital signals, it is necessary to obtain the pulse width of the pulse in the digital signal. The pulse width detection circuits in the prior art are usually all implemented by digital circuits. However, the electrical characteristics of various basic logic devices contained in the digital circuits (gate delay and conversion threshold, etc.) are greatly affected by process accuracy, temperature and power supply voltage. That is, low process accuracy, excessively high or low temperature, and power supply voltage jitter will have a great impact on the working process of the digital circuit, thereby reducing the accuracy of pulse width detection.

[0003] Therefore, how to provide a solution to the above technical problems is a problem that those skilled in the art need to solve at present. Summary of the invention

[0004] The purpose of the present invention is to provide a pulse width detection circuit. The capacitor charge regulation circuit and the hysteresis comparator in the present application are both analog circuits, and the edge conversion circuit can also be selected to be set as an analog circuit. Due to the characteristics of the analog circuit itself, the pulse width detection circuit in the present application is less affected by process accuracy, temperature and power supply voltage, thereby improving the accuracy of pulse width detection.

[0005] In order to solve the above technical problems, the present invention provides a pulse width detection circuit, comprising:

[0006] An edge conversion circuit, configured to generate a first control signal when a rising edge of a digital signal is detected, and to generate a second control signal when a falling edge of the digital signal is detected;

[0007] A capacitor power regulating circuit connected to the edge conversion circuit, used for charging the capacitor inside itself under the control of the first control signal, and discharging the capacitor inside itself under the control of the second control signal, so as to generate a triangular wave on the capacitor;

[0008] A hysteresis comparator connected to the capacitor power regulation circuit, used for outputting a high level when the voltage of the triangular wave is higher than a preset positive flip voltage, and outputting a low level when the voltage of the triangular wave is lower than a preset negative flip voltage;

[0009] The power supply respectively connected to the edge conversion circuit, the capacitor power regulation circuit and the hysteresis comparator is used to supply power to the edge conversion circuit, the capacitor power regulation circuit and the hysteresis comparator.

[0010] Preferably, the capacitor power regulation circuit comprises a capacitor, a first controllable switch, a second controllable switch and a current control circuit;

[0011] The current control circuit is used to adjust the ratio of the charging current to the discharging current of the capacitor to a preset ratio so as to generate a triangular wave on the capacitor;

[0012] The first end of the capacitor is respectively connected to the first end of the first controllable switch, the first end of the second controllable switch and the input end of the hysteresis comparator, the second end of the capacitor is grounded, the control end of the first controllable switch and the control end of the second controllable switch are both connected to the edge conversion circuit, the second end of the first controllable switch and the second end of the second controllable switch are both connected to the current control circuit, the current control circuit is connected to the power supply, and the ground end of the current control circuit is grounded.

[0013] Preferably, the current control circuit comprises a high-precision reference source, a first current mirror and a second current mirror;

[0014] The high-precision reference source is used to generate a current with a high-precision current value and provide a preset positive flip voltage and a preset negative flip voltage for the hysteresis comparator;

[0015] The power supply is respectively connected to the high-precision reference source, the first end and the second end of the first current mirror, the third end of the first current mirror is connected to the high-precision reference source, the fourth end of the first current mirror is connected to the second end of the first controllable switch, the high-precision reference source is connected to the first end of the second current mirror, the second end of the second controllable switch is connected to the second end of the second current mirror, the first ground terminal and the second ground terminal of the second current mirror are both grounded, the positive flip voltage output terminal of the high-precision reference source is connected to the positive flip voltage receiving terminal of the hysteresis comparator, and the negative flip voltage output terminal of the high-precision reference source is connected to the negative flip voltage receiving terminal of the hysteresis comparator.

[0016] Preferably, the first controllable switch is a PMOS tube, and the second controllable switch is an NMOS tube.

[0017] Preferably, the edge conversion circuit includes a positive edge D flip-flop and a first negative edge D flip-flop.

[0018] Preferably, the pulse width detection circuit further includes:

[0019] A reset circuit connected to the output end of the hysteresis comparator, the reset end of the positive edge D flip-flop and the reset end of the first negative edge D flip-flop respectively, is used to control the reset of the positive edge D flip-flop and the first negative edge D flip-flop when a falling edge is detected.

[0020] Preferably, the reset circuit comprises a second negative edge D flip-flop and a delay circuit;

[0021] The input end of the second negative edge D trigger is connected to the output end of the hysteresis comparator, the output end of the second negative edge D trigger is respectively connected to the reset end of the positive edge D trigger, the reset end of the first negative edge D trigger and the first end of the delay circuit, and the second end of the delay circuit is connected to the reset end of the second negative edge D trigger.

[0022] Preferably, the delay circuit is a capacitor.

[0023] Preferably, the power supply is a low dropout linear regulator LDO.

[0024] The present invention provides a pulse width detection circuit. The edge conversion circuit in the present application can control the charging and discharging of the capacitor in the capacitor power regulation circuit based on the pulse width of the digital signal, and then the triangular wave generated in the capacitor is processed by the hysteresis comparator. Finally, the pulse width of the digital signal can be judged by the output waveform of the hysteresis comparator. Since the capacitor power regulation circuit and the hysteresis comparator in the present application are both analog circuits, and the edge conversion circuit can also be selected to be an analog circuit, due to the characteristics of the analog circuit itself, the pulse width detection circuit in the present application is less affected by the process accuracy, temperature and power supply voltage, thereby improving the accuracy of pulse width detection. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the prior art and the drawings required for use in the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0026] Figure 1 A schematic diagram of the structure of a pulse width detection circuit provided by the present invention;

[0027] Figure 2 A schematic diagram of a working waveform of a pulse width detection provided by the present invention;

[0028] Figure 3 A schematic diagram of another working waveform of pulse width detection provided by the present invention;

[0029] Figure 4 A schematic diagram of a working waveform of another pulse width detection provided by the present invention;

[0030] Figure 5A schematic diagram of the structure of another pulse width detection circuit provided by the present invention. DETAILED DESCRIPTION

[0031] The core of the present invention is to provide a pulse width detection circuit. The capacitor charge regulation circuit and the hysteresis comparator in the present application are both analog circuits, and the edge conversion circuit can also be selected to be set as an analog circuit. Due to the characteristics of the analog circuit itself, the pulse width detection circuit in the present application is less affected by process accuracy, temperature and power supply voltage, thereby improving the accuracy of pulse width detection.

[0032] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0033] Please refer to Figure 1 , Figure 1 A schematic diagram of a pulse width detection circuit provided by the present invention, the pulse width detection circuit comprising:

[0034] An edge conversion circuit 1, configured to generate a first control signal when a rising edge of a digital signal is detected, and to generate a second control signal when a falling edge of the digital signal is detected;

[0035] The capacitor power regulating circuit 2 connected to the edge conversion circuit 1 is used to charge the capacitor inside itself under the control of the first control signal and discharge the capacitor inside itself under the control of the second control signal, so as to generate a triangular wave on the capacitor;

[0036] A hysteresis comparator 3 connected to the capacitor power regulation circuit 2 is used to output a high level when the voltage of the triangular wave is higher than a preset positive flip voltage, and output a low level when the voltage of the triangular wave is lower than a preset negative flip voltage;

[0037] The power supply 4 connected to the edge conversion circuit 1 , the capacitor power regulation circuit 2 and the hysteresis comparator 3 respectively is used to supply power to the edge conversion circuit 1 , the capacitor power regulation circuit 2 and the hysteresis comparator 3 .

[0038] Specifically, taking into account the technical problems in the above background technology, the present application intends to realize the detection of the pulse width of the digital signal through the analog circuit as much as possible. Therefore, in the present application, the capacitor power regulation circuit 2 regulates the power of the capacitor inside itself under the control of the first control signal and the second control signal, and the hysteresis comparator 3 itself is also an analog circuit. Due to the characteristics of the analog circuit itself, the pulse width detection circuit in the present application is less affected by the process accuracy, temperature and power supply voltage, thereby improving the accuracy of pulse width detection.

[0039] Specifically, to better illustrate the embodiments of the present invention, please refer to Figures 2 to 4 , Figure 2 A schematic diagram of a pulse width detection working waveform provided by the present invention, Figure 3 Another working waveform diagram of pulse width detection provided by the present invention is shown in FIG. Figure 4 A schematic diagram of a working waveform of another pulse width detection provided by the present invention, in which the charge in the capacitor is zero at the initial moment, and a first control signal (Q1N) can be generated after the edge conversion circuit 1 detects a rising edge circuit to control the charging of the capacitor in the capacitor charge regulating circuit 2, so that the charge in the capacitor increases at a certain slope, and a second control signal (Q2) can be generated when the edge conversion circuit 1 detects a falling edge (at this time the charge in the capacitor reaches V1), and the second control signal can control the capacitor charge regulating circuit 2 to discharge the capacitor inside it, and at this time the first control signal can still exist, so the "charging action" will continue, and the discharge speed can be made greater than the charging speed by adjusting the ratio between the discharge current and the charging current, and the capacitor charge drops to V2 after the preset discharge time, thereby generating three Angle wave (Vcap), and then the triangular wave on the capacitor can be processed by the hysteresis comparator 3, and a high level is output when the voltage of the triangular wave is higher than the preset positive reversal voltage (VP), and a low level is output when it is lower than the preset negative reversal voltage (VN), thereby outputting a waveform with a certain pulse width. It is worth noting that if the amount of electricity on the capacitor still does not exceed the preset positive reversal voltage at the arrival of the falling edge of the original digital signal, it means that the pulse width of the original digital signal has not reached the preset time. By observing the "low level" output by the hysteresis comparator 3 at this time, it can be judged that the current digital signal does not have a pulse signal that reaches the preset time. Only when the hysteresis comparator 3 outputs a "square wave", it means that the current digital signal has a pulse signal that reaches the preset time, thereby realizing the detection of the pulse width.

[0040] Specifically, within a complete pulse signal input cycle, if appropriate values ​​are taken for the current source current, capacitance, flip voltage VP and VN, the relationship between V1 / V2 and VP / VN can be used to accurately characterize whether the input pulse width is not less than the preset time. When the input pulse width is greater than or equal to the preset time, a long square wave will be output, and when the input pulse width is less than the preset time, a low level will be output. If the input pulse has glitches or jitter, a long square wave will also be output, thereby realizing the detection of specific pulse width signals.

[0041] The present invention provides a pulse width detection circuit. The edge conversion circuit in the present application can control the charging and discharging of the capacitor in the capacitor power regulation circuit based on the pulse width of the digital signal, and then the triangular wave generated in the capacitor is processed by the hysteresis comparator. Finally, the pulse width of the digital signal can be judged by the output waveform of the hysteresis comparator. Since the capacitor power regulation circuit and the hysteresis comparator in the present application are both analog circuits, and the edge conversion circuit can also be selected to be an analog circuit, due to the characteristics of the analog circuit itself, the pulse width detection circuit in the present application is less affected by the process accuracy, temperature and power supply voltage, thereby improving the accuracy of pulse width detection.

[0042] To better illustrate the embodiments of the present invention, please refer to Figure 5 , Figure 5 A schematic diagram of the structure of another pulse width detection circuit provided by the present invention, based on the above embodiment:

[0043] As a preferred embodiment, the capacitor power regulation circuit 2 includes a capacitor, a first controllable switch Q3, a second controllable switch Q4 and a current control circuit;

[0044] The current control circuit is used to adjust the ratio of the charging current to the discharging current of the capacitor to a preset ratio so as to generate a triangular wave on the capacitor;

[0045] The first end of the capacitor is respectively connected to the first end of the first controllable switch Q3, the first end of the second controllable switch Q4 and the input end of the hysteresis comparator 3, the second end of the capacitor is grounded, the control end of the first controllable switch Q3 and the control end of the second controllable switch Q4 are both connected to the edge conversion circuit 1, the second end of the first controllable switch Q3 and the second end of the second controllable switch Q4 are both connected to the current control circuit, the current control circuit is connected to the power supply 4, and the ground end of the current control circuit is grounded.

[0046] Specifically, the capacitor power regulation circuit 2 in the present application has a relatively simple structure and low device cost, so that its first controllable switch Q3 and the second controllable switch Q4 can complete the charging and discharging control of the capacitor under the control of the first control signal and the second control signal.

[0047] Among them, the current control circuit can adjust the ratio of the charging current to the discharging current of the capacitor to a preset ratio so as to generate a triangular wave on the capacitor. It is best to adjust the discharging current to twice the charging current, etc., so as to ensure that the rising edge and falling edge of the triangular wave are equal, so as to perform pulse width detection more accurately. The embodiments of the present invention are not limited here.

[0048] Of course, in addition to this specific structure, the capacitor charge regulation circuit 2 can also be of many other types, as long as it can regulate the internal capacitor charge according to two control signals and generate a triangular wave (preferably a triangular wave with equal rising and falling edges), the embodiments of the present invention are not limited here.

[0049] As a preferred embodiment, the current control circuit includes a high-precision reference source, a first current mirror and a second current mirror;

[0050] The high-precision reference source is used to generate a current with a high-precision current value and provide a preset positive flip voltage and a preset negative flip voltage for the hysteresis comparator 3;

[0051] The power supply 4 is respectively connected to the high-precision reference source, the first end and the second end of the first current mirror, the third end of the first current mirror is connected to the high-precision reference source, the fourth end of the first current mirror is connected to the second end of the first controllable switch Q3, the high-precision reference source is connected to the first end of the second current mirror, the second end of the second controllable switch Q4 is connected to the second end of the second current mirror, the first grounding end and the second grounding end of the second current mirror are both grounded, the positive flip voltage output end of the high-precision reference source is connected to the positive flip voltage receiving end of the hysteresis comparator 3, and the negative flip voltage output end of the high-precision reference source is connected to the negative flip voltage receiving end of the hysteresis comparator 3.

[0052] Specifically, a high-precision reference source can generate a current with a precise current value, through which the ratio of charging current to discharging current can be accurately controlled, and the current mirror can mirror the current generated by the high-precision reference source to the charging circuit or the discharging circuit, and the ratio of the mirror can be adjusted through the parameters of the switching tubes in the first current mirror and the second current mirror, so as to better control the ratio of charging current to discharging current.

[0053] Specifically, the hysteresis comparator 3 can also use a high-precision hysteresis comparator 3. In this way, the high-precision reference source and the high-precision hysteresis comparator 3 have the characteristics of high power supply rejection ratio (greater than 60dB), ensuring that when the power supply voltage jitters, the output current and flip voltage change very little; extremely low temperature drift characteristics ensure the stability of key circuit parameters at high and low temperatures; good process deviation compensation, when the process accuracy fluctuates, the internal static operating point can be adjusted autonomously, which also ensures the stability of the output current and flip voltage.

[0054] Specifically, due to the use of a high-precision reference source and a high-precision hysteresis comparator 3, the maximum error of this solution lies in the fluctuation of the capacitance value of the capacitor. Through good layout design and auxiliary means such as laser trimming, the accuracy of the capacitance value can reach a certain level.

[0055] Among them, the above-mentioned current control circuit has the characteristics of strong working stability, simple structure and low cost.

[0056] Of course, in addition to the above-mentioned current control circuit, the current control circuit may also be of other types, which is not limited in the embodiment of the present invention.

[0057] As a preferred embodiment, the first controllable switch Q3 is a PMOS tube, and the second controllable switch Q4 is an NMOS tube.

[0058] Specifically, the first controllable switch Q3 uses a PMOS tube and the second controllable switch Q4 uses an NMOS tube to facilitate the connection and use of the first current mirror and the second current mirror, wherein Q5 and Q6 form the first current mirror, and Q7 and Q8 form the second current mirror.

[0059] Specifically, Q3 uses a PMOS tube and Q4 uses an NMOS tube to ensure that the current mirror has good mirror characteristics, reduce circuit complexity and facilitate wiring. Of course, the first controllable switch Q3 and the second controllable switch Q4 can also be MOS tubes of the same type, or can be other types of controllable switches, which is not limited in the embodiments of the present invention.

[0060] As a preferred embodiment, the edge conversion circuit 1 includes a positive edge D flip-flop D1 and a first negative edge D flip-flop D2.

[0061] Among them, the action characteristics of the positive edge trigger are: when the clock inputs a rising edge, the Q output terminal outputs the state of the D input terminal, the QN output terminal outputs the inverted state of the D input terminal, and the RST terminal forces Q and QN to be set to 0 and 1. The action characteristics of the negative edge trigger are similar, except that Q and QN change states when the clock inputs a falling edge. Specifically, in this embodiment, RST sets the Q terminal and QN to 0 and 1. After the clock receives the rising edge and the falling edge, because the D input terminal is always 1, the Q terminal will be converted from 0 to 1, and the QN terminal will be converted from 1 to 0.

[0062] Specifically, two D flip-flops can be used to convert the positive edge into the first control signal and the negative edge into the second control signal, which has a simple structure and low cost.

[0063] Of course, in addition to the two D flip-flops, the edge conversion circuit 1 may also be of other specific types, which is not limited in the embodiment of the present invention.

[0064] Specifically, in Figure 5 In the initial state, the two first controllable switches Q3 and the second controllable switch Q4 are both in the disconnected state, that is, the capacitor voltage is 0 at this time. The low-level signal output by the positive-edge D trigger D1 after receiving the first control signal will immediately close the first controllable switch Q3, so that the first constant current source (the output end of the first current mirror) charges the capacitor, and the voltage of the capacitor rises steadily at a certain slope. The voltage rising per unit time is equal to the current value of the first constant current source divided by the capacitance value. After time t1, the capacitor voltage rises to V1. After the pulse width time has passed, the high-level signal output by the first negative edge D trigger D2 after receiving the second control signal will close the second controllable switch Q4, allowing the second constant current source (the output end of the second current mirror) to discharge the capacitor. Assuming that the current of the second constant current source is twice that of the first constant current source, after time t2, the voltage of the capacitor will drop to V2 at the same slope as the rising edge, so a pulse signal will eventually generate a triangular wave on the capacitor. This triangular wave is input into a high-precision hysteresis comparator 3. The hysteresis comparator 3 will have several different output waveforms according to the width of the input pulse. By judging whether the output is convenient, it can be determined whether the pulse width is not less than the preset time.

[0065] As a preferred embodiment, the pulse width detection circuit further includes:

[0066] The reset circuit connected to the output end of the hysteresis comparator 3 and the reset end of the positive edge D flip-flop D1 and the reset end of the first negative edge D flip-flop D2 respectively is used to control the reset of the positive edge D flip-flop D1 and the first negative edge D flip-flop D2 when a falling edge is detected.

[0067] Specifically, the reset circuit can automatically reset the positive edge D flip-flop D1 and the first negative edge D flip-flop D2 to their initial states after a pulse of the digital signal ends, so as to detect the pulse width of the next pulse of the digital signal, thereby improving the degree of automation.

[0068] As a preferred embodiment, the reset circuit includes a second negative edge D flip-flop D3 and a delay circuit;

[0069] The input end of the second negative edge D flip-flop D3 is connected to the output end of the hysteresis comparator 3, the output end of the second negative edge D flip-flop D3 is respectively connected to the reset end of the positive edge D flip-flop D1, the reset end of the first negative edge D flip-flop D2 and the first end of the delay circuit, and the second end of the delay circuit is connected to the reset end of the second negative edge D flip-flop D3.

[0070] Specifically, when the second negative edge D trigger D3 receives the falling edge output by the hysteresis comparator 3, it can first control the reset of the positive edge D trigger D1 and the first negative edge D trigger D2. Due to the existence of the delay circuit, it can control its own reset after controlling the reset of the positive edge D trigger D1 and the first negative edge D trigger D2, so as to better prepare for the next round of pulse width detection and reset work.

[0071] Of course, in addition to this structure, the reset circuit may also be of other types, which is not limited in the embodiment of the present invention.

[0072] As a preferred embodiment, the delay circuit is a capacitor.

[0073] Specifically, capacitors have the advantages of stable delay, low cost and long life.

[0074] Of course, in addition to capacitors, the delay circuit may also be of other types, for example, an even number of inverters connected in series, etc., which is not limited in the embodiment of the present invention.

[0075] As a preferred embodiment, the power supply 4 is a LDO (Low Dropout regulator).

[0076] Specifically, the LDO can maintain an extremely stable constant voltage output when its own power supply jitters, and is not affected by ambient temperature changes and process deviation factors. The LDO is used to power a high-precision reference source, a hysteresis comparator 3, and a current mirror, thereby ensuring good voltage stability.

[0077] Of course, in addition to LDO, the power supply 4 can also be of other types, which is not limited in the embodiment of the present invention.

[0078] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same and similar parts between the embodiments can be referred to each other. It should also be noted that in this specification, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements includes not only those elements, but also other elements that are not explicitly listed, or also include elements inherent to such process, method, article or equipment. In the absence of more restrictions, the elements defined by the sentence "including one..." do not exclude the existence of other identical elements in the process, method, article or equipment including the element.

[0079] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A pulse width detection circuit, characterized in that: include: An edge conversion circuit, configured to generate a first control signal when a rising edge of a digital signal is detected, and to generate a second control signal when a falling edge of the digital signal is detected; A capacitor power regulating circuit connected to the edge conversion circuit, used for charging the capacitor inside itself under the control of the first control signal, and discharging the capacitor inside itself under the control of the second control signal, so as to generate a triangular wave on the capacitor; A hysteresis comparator connected to the capacitor power regulation circuit, used for outputting a high level when the voltage of the triangular wave is higher than a preset positive flip voltage, and outputting a low level when the voltage of the triangular wave is lower than a preset negative flip voltage; The power supply respectively connected to the edge conversion circuit, the capacitor power regulation circuit and the hysteresis comparator is used to supply power to the edge conversion circuit, the capacitor power regulation circuit and the hysteresis comparator.

2. The pulse width detection circuit according to claim 1, characterized in that: The capacitor power regulation circuit includes a capacitor, a first controllable switch, a second controllable switch and a current control circuit; The current control circuit is used to adjust the ratio of the charging current to the discharging current of the capacitor to a preset ratio so as to generate a triangular wave on the capacitor; The first end of the capacitor is respectively connected to the first end of the first controllable switch, the first end of the second controllable switch and the input end of the hysteresis comparator, the second end of the capacitor is grounded, the control end of the first controllable switch and the control end of the second controllable switch are both connected to the edge conversion circuit, the second end of the first controllable switch and the second end of the second controllable switch are both connected to the current control circuit, the current control circuit is connected to the power supply, and the ground end of the current control circuit is grounded.

3. The pulse width detection circuit according to claim 2, characterized in that: The current control circuit includes a high-precision reference source, a first current mirror and a second current mirror; The high-precision reference source is used to generate a current with a high-precision current value and provide a preset positive flip voltage and a preset negative flip voltage for the hysteresis comparator; The power supply is respectively connected to the high-precision reference source, the first end and the second end of the first current mirror, the third end of the first current mirror is connected to the high-precision reference source, the fourth end of the first current mirror is connected to the second end of the first controllable switch, the high-precision reference source is connected to the first end of the second current mirror, the second end of the second controllable switch is connected to the second end of the second current mirror, the first ground terminal and the second ground terminal of the second current mirror are both grounded, the positive flip voltage output terminal of the high-precision reference source is connected to the positive flip voltage receiving terminal of the hysteresis comparator, and the negative flip voltage output terminal of the high-precision reference source is connected to the negative flip voltage receiving terminal of the hysteresis comparator.

4. The pulse width detection circuit according to claim 3, characterized in that: The first controllable switch is a PMOS tube, and the second controllable switch is an NMOS tube.

5. The pulse width detection circuit according to claim 3, characterized in that: The edge conversion circuit includes a positive edge D flip-flop and a first negative edge D flip-flop.

6. The pulse width detection circuit according to claim 5, characterized in that: The pulse width detection circuit also includes: A reset circuit connected to the output end of the hysteresis comparator, the reset end of the positive edge D flip-flop and the reset end of the first negative edge D flip-flop respectively, is used to control the reset of the positive edge D flip-flop and the first negative edge D flip-flop when a falling edge is detected.

7. The pulse width detection circuit according to claim 6, characterized in that: The reset circuit includes a second negative edge D flip-flop and a delay circuit; The input end of the second negative edge D trigger is connected to the output end of the hysteresis comparator, the output end of the second negative edge D trigger is respectively connected to the reset end of the positive edge D trigger, the reset end of the first negative edge D trigger and the first end of the delay circuit, and the second end of the delay circuit is connected to the reset end of the second negative edge D trigger.

8. The pulse width detection circuit according to claim 7, characterized in that: The delay circuit is a capacitor.

9. The pulse width detection circuit according to any one of claims 1 to 8, characterized in that: The power supply is a low dropout linear regulator LDO.

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