GaN device driver circuit with integrated overvoltage protection

Abstract

The present invention relates to a gallium nitride device driving circuit with integrated overvoltage protection, comprising: a driving module, a feedback control module and a boost conversion module connected in sequence; the boost conversion module is used to output the output voltage of the driving circuit, and the feedback voltage output terminal of the boost conversion module feeds back the output voltage to the feedback control module; the feedback control module is configured to compare the output voltage with a preset voltage value, and when the output voltage is higher than the preset voltage value, generate a low-level signal and feed it back to the driving module; the driving module is configured to disconnect the internal circuit of the boost conversion module when receiving the low-level signal fed back by the feedback control module. The present invention can realize overvoltage protection of the driving circuit, and solve the problem in the prior art that the integrated driving circuit does not integrate a protection module, which easily causes the output voltage to exceed the rated value, thereby causing device damage.

Description

Technical Field

[0001] The present invention relates to the technical field of power electronics, and in particular to a gallium nitride device driving circuit with integrated overvoltage protection. Background Art

[0002] Gallium nitride (GaN) has been regarded as a next-generation semiconductor material for power electronic devices with high efficiency and high power density.

[0003] Currently, GAN (gallium nitride) devices are ahead of traditional MOSFETs in performance, but due to process limitations, there are requirements for their gate drive voltage, which generally does not exceed 5.6V.

[0004] However, the driving voltage of MOS-driven circuits (including but not limited to controllers, etc.) on the market is mostly around 12V. In circuit applications, GAN cannot directly replace MOSFET, and a dedicated driving circuit for gallium nitride devices needs to be added.

[0005] In the setting of traditional GaN-based drive circuits, a transmission chain is often used, and a multi-stage NMOS logic inverter cascade is used to amplify the output current to achieve gate drive of power devices. The second method is to use a half-bridge structure composed of two E-mode circuits as a buffer-level circuit to achieve the output of gate drive current. Usually, at least two stages of NMOS logic NOT gate cascade are required to isolate the input signal and generate complementary control signals.

[0006] The control circuit is often added outside the drive circuit, which increases the area of ​​the monolithic integrated control circuit and the number of devices, thereby weakening the advantages of the monolithic integrated chip. In addition, because the gate withstand voltage of the control circuit is too low under the conditions of p-GaN or fluorine ion implantation process, the input signal of the drive circuit needs to be stepped down by a level shifter or voltage matching circuit before it can enter the drive circuit.

[0007] Moreover, the current drive circuit does not have an integrated protection circuit, which can easily cause the output voltage to exceed the rated value, thereby causing device damage.

[0008] In addition, many existing control technologies are based on silicon-based technology. For gallium nitride devices, silicon-based technology control circuits will increase the chip area and cannot match gallium nitride devices in high-frequency and high-voltage environments, thereby reducing system stability.

[0009] Therefore, it is necessary to improve the prior art to overcome the above defects in the prior art. Summary of the invention

[0010] The object of the present invention is to provide a gallium nitride device driving circuit with integrated overvoltage protection, so as to solve the problem in the prior art that the protection circuit is not integrated in the driving circuit, which easily causes the output voltage to exceed the rated value, thereby causing device damage.

[0011] The purpose of the present invention is achieved through the following technical solutions:

[0012] The present invention provides a gallium nitride device driving circuit with integrated overvoltage protection, characterized in that it comprises: a driving module, a feedback control module and a boost conversion module connected in sequence;

[0013] The boost conversion module is used to output the output voltage of the driving circuit, and the feedback voltage output terminal of the boost conversion module feeds back the output voltage to the feedback control module;

[0014] The feedback control module is configured to: compare the output voltage with a preset voltage value, and when the output voltage is higher than the preset voltage value, generate a low level signal and feed it back to the driving module;

[0015] The driving module is configured to disconnect the internal circuit of the boost conversion module when receiving a low level signal fed back by the feedback control module.

[0016] Optionally, the driving module includes a NAND gate logic circuit, an inverter and a driving buffer;

[0017] The first input end of the logic NAND gate circuit is connected to the output end of the feedback control module, the second input end of the logic NAND gate circuit is connected to the drive control signal, the output end of the logic NAND gate circuit is connected to the inverter and the drive buffer in sequence, and the output end of the drive buffer is connected to the input end of the boost conversion module.

[0018] Optionally, the NAND gate logic circuit includes a dual-gate gallium nitride enhancement MOS transistor and a single-gate depletion MOS transistor connected in series, one gate of the dual-gate gallium nitride enhancement MOS transistor serves as a first input terminal of the NAND gate logic circuit, the other gate of the dual-gate gallium nitride enhancement MOS transistor serves as a second input terminal of the logic NAND gate circuit, and the series connection point of the dual-gate gallium nitride enhancement MOS transistor and the single-gate depletion MOS transistor serves as an output terminal of the NAND gate logic circuit.

[0019] Optionally, the feedback control module includes a comparator circuit and a two-stage cascade inverter circuit;

[0020] The inverting input terminal of the comparator circuit is connected to the feedback voltage output terminal of the boost conversion module, and the non-inverting input terminal of the comparator circuit is connected to the reference voltage;

[0021] The output end of the comparator circuit is connected to the input end of the inverter circuit, and the output end of the inverter circuit is connected to the first input end of the NAND gate logic circuit.

[0022] Optionally, the boost conversion module includes a power switch tube and a voltage collection circuit, the control end of the power switch tube is connected to the output end of the driving buffer, the input end of the power switch tube is connected to the power supply through a series inductor, and the voltage at the point where the power switch tube and the inductor are connected in series is the output voltage;

[0023] The input end of the voltage acquisition circuit is connected to the output voltage, and the output end of the voltage acquisition circuit serves as the feedback voltage output end of the boost conversion module.

[0024] Optionally, the voltage acquisition circuit is a voltage-dividing resistor circuit, which includes a first resistor and a second resistor connected in series, and a series connection point between the first resistor and the second resistor is connected to a first input terminal of the NAND gate logic circuit.

[0025] Optionally, the dual-gate GaN enhancement-mode MOS tube and the single-gate depletion-mode MOS tube are both N-channel, the drain of the single-gate depletion-mode MOS tube is connected to a power supply, and the source of the single-gate depletion-mode MOS tube is grounded via the dual-gate GaN enhancement-mode MOS tube connected in series.

[0026] Optionally, the dual-gate gallium nitride enhancement mode MOS transistor is obtained by etching two gates at different depths to modulate threshold voltage.

[0027] Optionally, the dual-gate gallium nitride enhancement mode MOS transistor uses aluminum oxide as a dielectric layer.

[0028] Optionally, the dual-gate gallium nitride enhancement-mode MOS transistor and the single-gate depletion-mode MOS transistor are MIS-HEMT devices.

[0029] Compared with the prior art, the present invention has the following beneficial effects: the internal integrated overvoltage protection of the driving circuit of the present invention can directly disconnect the driving circuit when the output voltage exceeds the preset voltage value, thereby avoiding direct input of high voltage to damage the internal circuit, thereby achieving overvoltage protection for the internal circuit.

[0030] The present invention adopts full gallium nitride monolithic integration, and the driving module and the feedback control module are compatible with the gallium nitride power device manufacturing process, thereby increasing the adaptability and stability of the system in a harsh environment of high temperature and high frequency.

[0031] The present invention adopts a NAND gate logic circuit made of a threshold-modulated dual-gate gallium nitride enhancement-mode MOS tube. Compared with the traditional form of two enhancement-mode devices connected in series, the dual-gate structure reduces parasitic parameters and module circuit size, thereby improving the high-frequency performance of the system.

[0032] In order to match the two gate threshold voltages of the enhanced devices of the NAND logic circuit, the two gates are etched at different depths. At the same time, aluminum oxide is used as the dielectric layer to optimize the device's voltage resistance level and the voltage swing of the logic circuit, which improves the output performance of the logic circuit and can adapt to higher operating voltages without the need for additional protection circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 It is a circuit schematic diagram of a gallium nitride device driving circuit with integrated overvoltage protection of the present invention. DETAILED DESCRIPTION

[0034] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0035] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0036] It should be understood that the orientation or position relationship indicated by terms such as "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside" and "outside" are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0037] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0038] The present invention provides a gallium nitride device driving circuit with integrated overvoltage protection, which is used to solve the problems of large circuit size and relatively low system performance of gallium nitride devices in the prior art.

[0039] Thanks to its low manufacturing cost, superior performance and high reliability, the P-type gate structure has become a key technical method for building enhancement-mode GaN devices. In switching applications, the driver circuit provides continuously changing high-level and low-level drive signals to the p-type gate of the GaN device, thereby controlling the device to turn on or off.

[0040] Figure 1 A schematic diagram of a gallium nitride device driving circuit with integrated overvoltage protection provided by an embodiment of the present invention is given, such as Figure 1 As shown, the driving circuit includes: a driving module 1 integrated with feedback control, a feedback control module 2 and a boost conversion module 3.

[0041] The output end of the driving module 1 is connected to the input end of the boost conversion module 3 , the feedback output end of the boost conversion module 3 is connected to the input end of the feedback control module 2 , and the output end of the feedback control module 2 is connected to the input end of the driving module 1 .

[0042] In this embodiment, the output voltage of the boost conversion module 3 is collected and fed back to the feedback control module 2. The feedback control module 2 compares the output voltage with a preset voltage value. When the output voltage is higher than the preset voltage value, a low-level signal is generated and fed back to the drive module 1 to shut down the drive circuit.

[0043] The driving circuit of this embodiment has an internal integrated overvoltage protection. When the output voltage exceeds a preset voltage value, the driving circuit can be directly disconnected, thereby avoiding direct input of high voltage to damage the internal circuit, thereby achieving overvoltage protection for the internal circuit.

[0044] Optionally, the driving module 1 includes a NAND gate logic circuit 101 , an inverter 102 and a driving buffer 103 .

[0045] The input end of the NAND gate logic circuit 101 is used as the input end of the driving module 1 , and the output end of the driving buffer 103 is used as the output end of the driving module 1 .

[0046] The first input terminal V1 of the NAND gate logic circuit 101 is connected to the output terminal of the feedback control module 2, and the second input terminal V2 of the NAND gate logic circuit 101 is connected to the driving control signal. The output terminal of the NAND gate logic circuit 101 is connected to the input terminal of the inverter 102, and the output terminal of the inverter 102 is connected to the input terminal of the driving buffer 103, and the output terminal of the driving buffer 103 is the output terminal of the driving module 1.

[0047] Optionally, the feedback control module 2 includes a comparator circuit 201 and a two-stage cascade inverter circuit 202 .

[0048] The inverting input terminal of the comparator circuit 201 is the input terminal of the feedback control module 2, connected to the feedback voltage output terminal of the boost conversion module 3, and the non-inverting input terminal of the comparator circuit 201 is connected to the reference voltage. The output terminal of the comparator circuit 201 is connected to the input terminal of the inverter circuit 202, and the output terminal of the inverter circuit 202 is used as the output terminal of the feedback control module 2 and connected to the first input terminal V1 of the NAND gate logic circuit 101.

[0049] The feedback control module 2 of this embodiment identifies the output voltage signal of the boost conversion module, compares the output voltage with a given reference voltage VREF, determines whether the output voltage is overvoltage, and outputs an output signal of the comparison result to the driving module 1 .

[0050] The feedback control module 2 compares the output voltage VFEB fed back by the boost conversion module with the reference voltage VREF through the comparator circuit 201. When VFEB is greater than VREF, the comparator circuit 201 outputs a logic low level signal, so that the first input terminal V1 of the NAND gate logic circuit is a logic low level signal, and the drive circuit is disconnected. Until VFEB is less than VREF, the drive circuit is turned on and can operate normally.

[0051] Optionally, the boost conversion module 3 includes a power switch tube, a voltage divider resistor circuit, a capacitor C, an inductor L and a diode D2.

[0052] The voltage-dividing resistor circuit includes resistors R1 and R2 connected in series, wherein the series connection point of the resistors R1 and R2 serves as a feedback voltage output terminal of the boost conversion module and is connected to an inverting input terminal of the comparator circuit 201 .

[0053] The power switch tube is the ninth enhanced NMOS tube E9, the gate of which is the input end of the boost conversion module 3 and connected to the output end of the driving module 1. When the driving module 1 outputs a low level signal, the power switch tube is turned off, otherwise, the power switch tube is turned on.

[0054] In this embodiment, when the output voltage VOUT of the boost converter circuit is higher than the rated value, the control signal generated by the feedback voltage output terminal of the feedback control module 2 is a logic low level. At this time, the first input terminal V1 of the logic NAND gate circuit 101 is a low level. Regardless of whether the output signal state is switched, the output of the NAND gate logic circuit 101 is always a logic high level. In this way, a low level signal is always generated at the output terminal of the driving buffer 103, so that the ninth enhancement mode NMOS tube E9 is turned off to achieve the locking function.

[0055] Furthermore, in this embodiment, if Figure 1As shown, the NAND gate logic circuit 101 includes a first depletion-mode MOS transistor D1 and a dual-gate gallium nitride enhancement-mode MOS transistor E1, wherein the first depletion-mode MOS transistor D1 and the dual-gate gallium nitride enhancement-mode MOS transistor E1 are connected in series.

[0056] Specifically, two gates of the dual-gate gallium nitride enhancement-mode MOS transistor E1 are respectively connected to the input signal V2 and the output signal V1 of the feedback control module 2, the source of the dual-gate gallium nitride enhancement-mode MOS transistor E1 is grounded, the drain of the dual-gate gallium nitride enhancement-mode MOS transistor E1 is connected to the source of the first depletion-mode MOS transistor D1, the drain of the first depletion-mode MOS transistor D1 is connected to the power supply through a reversely connected diode, and the gate of the first depletion-mode MOS transistor D1 is connected to the connection point between the drain of the dual-gate gallium nitride enhancement-mode MOS transistor E1 and the source of the first depletion-mode MOS transistor D1.

[0057] The NAND gate logic circuit 101 of this embodiment uses a dual-gate GaN device and increases the input control signal. The circuit can integrate a feedback control function without increasing the area, that is, it can recognize the output overvoltage signal and lock the gate drive output.

[0058] Furthermore, the inverter 102 includes a second depletion-type NMOS tube D2 and a second enhancement-type NMOS tube E2, the second depletion-type NMOS tube D2 and the second enhancement-type NMOS tube E2 are connected in series, the second depletion-type NMOS tube D2 is connected to the power supply through the inverse connection diode D1, and the series connection point of the second depletion-type NMOS tube D2 and the second enhancement-type NMOS tube E2 is the output of the inverter 102.

[0059] Specifically, the drain of the second depletion-type NMOS tube D2 is connected to the power supply through the inverse connection diode D1, the source of the second depletion-type NMOS tube D2 is connected to the drain of the second enhancement-type NMOS tube E2, the source of the second enhancement-type NMOS tube E2 is grounded, the gate of the second enhancement-type NMOS tube E2 is connected to the output of the NAND gate logic circuit 101, and the gate of the second depletion-type NMOS tube D2 is connected to the source of the second depletion-type NMOS tube D2.

[0060] Furthermore, the driving buffer 103 includes a third enhancement mode NMOS transistor E3 and a fourth enhancement mode NMOS transistor E4.

[0061] Specifically, the third enhancement mode NMOS transistor E3 and the fourth enhancement mode NMOS transistor E4 are connected in series, and the series connection point of the third enhancement mode NMOS transistor E3 and the fourth enhancement mode NMOS transistor E4 is the output of the driving buffer, and the third enhancement mode NMOS transistor E3 is connected to the power supply through the inverse connection diode D1.

[0062] The gate of the third enhancement mode NMOS transistor E3 is connected to the output of the inverter 102 , and the gate of the fourth enhancement mode NMOS transistor E4 is connected to the output of the NAND gate logic circuit 101 .

[0063] Furthermore, the comparator circuit 201 includes a third depletion-type NMOS transistor D3, a fifth enhancement-type NMOS transistor E5, a fourth depletion-type NMOS transistor D4, a sixth enhancement-type NMOS transistor E6, and a fifth depletion-type NMOS transistor D5.

[0064] Specifically, the third depletion-mode NMOS transistor D3 and the fifth enhancement-mode NMOS transistor E5 are connected in series to form a first branch. The gate of the fifth enhancement-mode NMOS transistor E5 serves as the non-inverting input terminal of the comparator circuit 201 and is connected to a reference voltage.

[0065] The fourth depletion-mode NMOS transistor D4 and the sixth enhancement-mode NMOS transistor E6 are connected in series to form a second branch. The gate of the sixth enhancement-mode NMOS transistor E6 serves as the inverting input terminal of the comparator circuit 201 and is connected to the feedback output terminal of the boost converter circuit 3 .

[0066] The first branch and the second branch are connected in parallel and then connected in series with the fifth depletion-type NMOS transistor D5.

[0067] The gate of the fourth depletion-type NMOS transistor D4 is connected to the gate of the third depletion-type NMOS transistor D3, and the gate of the fourth depletion-type NMOS transistor D4 is also connected to the source of the fourth depletion-type NMOS transistor D4, and the series connection point of the fourth depletion-type NMOS transistor D4 and the sixth enhancement-type NMOS transistor E6 serves as the output of the comparator circuit 201.

[0068] Furthermore, the two-stage cascade inverter circuit 202 includes a first-stage inverter circuit and a second-stage inverter circuit that are cascaded.

[0069] Specifically, the first-stage inverter circuit includes a sixth depletion-type NMOS transistor D6 and a seventh enhancement-type NMOS transistor E7, and the second-stage inverter circuit includes a seventh depletion-type NMOS transistor D7 and an eighth enhancement-type NMOS transistor E8. Wherein:

[0070] The sixth depletion-type NMOS transistor D6 and the seventh enhancement-type NMOS transistor E7 are connected in series, the seventh depletion-type NMOS transistor D7 and the eighth enhancement-type NMOS transistor E8 are connected in series, and the series connection point of the sixth depletion-type NMOS transistor D6 and the seventh enhancement-type NMOS transistor E7 is connected to the gate of the eighth enhancement-type NMOS transistor E8. The series connection point of the seventh depletion-type NMOS transistor D7 and the eighth enhancement-type NMOS transistor E8 is connected to the first input terminal V1 of the NAND gate logic circuit 101 as the output of the feedback control module 2.

[0071] The specific type of MOS tube switch device selected in this embodiment is only a preferred implementation of this embodiment. In other embodiments, other different types of power switch tubes can also be selected to implement circuit modules with corresponding functions. This embodiment does not limit the specific type of power switch tube.

[0072] Furthermore, the MOS switch devices in this embodiment are all MIS-HEMT devices.

[0073] HEMT (High Electron Mobility Transistor), the leakage problem of traditional Schottky gate HEMT devices is relatively serious, which can easily cause the deterioration of key performance of the device such as breakdown voltage, efficiency, gain, etc.

[0074] In order to effectively suppress the gate current, this embodiment introduces a metal-insulator-semiconductor (MIS) structure into the gate of the traditional compound HEMT structure to form a MIS-HEMT device, which is an effective solution.

[0075] In order to match the two gate threshold voltages of the dual-gate NMOS tubes of each NAND gate logic circuit, this embodiment uses a reactive ion etcher to perform slow etching on the two gates to different depths. At the same time, aluminum oxide is used as a dielectric layer to optimize the device's withstand voltage level and the voltage swing of the logic circuit, thereby improving the output performance of the logic circuit and being able to adapt to higher operating voltages without the need for additional protection circuits.

[0076] This embodiment adopts full gallium nitride monolithic integration, and the driving circuit and feedback control circuit are compatible with the gallium nitride power device manufacturing process, thereby increasing the adaptability and stability of the system in a harsh environment of high temperature and high frequency.

[0077] In summary, the internal integrated overvoltage protection of the driving circuit of the present invention can directly disconnect the driving circuit when the output voltage exceeds the preset voltage value, thereby avoiding direct input of high voltage to damage the internal circuit, thereby achieving overvoltage protection for the internal circuit.

[0078] The present invention adopts full gallium nitride monolithic integration, and the driving module and the feedback control module are compatible with the gallium nitride power device manufacturing process, thereby increasing the adaptability and stability of the system in a harsh environment of high temperature and high frequency.

[0079] The present invention adopts a NAND gate logic circuit made of a threshold-modulated dual-gate gallium nitride enhancement-mode MOS tube. Compared with the traditional form of two enhancement-mode devices connected in series, the dual-gate structure reduces parasitic parameters and module circuit size, thereby improving the high-frequency performance of the system.

[0080] In order to match the two gate threshold voltages of the enhanced devices of the NAND logic circuit, the two gates are etched at different depths. At the same time, aluminum oxide is used as the dielectric layer to optimize the device's voltage resistance level and the voltage swing of the logic circuit, which improves the output performance of the logic circuit and can adapt to higher operating voltages without the need for additional protection circuits.

[0081] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0082] The above-mentioned embodiments only express several implementation methods of the present invention, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the scope of the invention patent. It should be pointed out that for ordinary technicians in this field, several modifications and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the attached claims.

Claims

1. A gallium nitride device driving circuit with integrated overvoltage protection, characterized in that: include: A driving module, a feedback control module and a boost conversion module connected in sequence; The boost conversion module is used to output the output voltage of the driving circuit, and the feedback voltage output terminal of the boost conversion module feeds back the output voltage to the feedback control module; The feedback control module is configured to: compare the output voltage with a preset voltage value, and when the output voltage is higher than the preset voltage value, generate a low level signal and feed it back to the driving module; The driving module is configured to: disconnect the internal circuit of the boost conversion module when receiving the low level signal fed back by the feedback control module; It is characterized in that the driving module includes a NAND gate logic circuit, an inverter and a driving buffer; The first input end of the NAND gate logic circuit is connected to the output end of the feedback control module, the second input end of the NAND gate logic circuit is connected to the drive control signal, the output end of the NAND gate logic circuit is connected to the inverter and the drive buffer in sequence, and the output end of the drive buffer is connected to the input end of the boost conversion module; The NAND gate logic circuit comprises a dual-gate gallium nitride enhancement-mode MOS transistor and a single-gate depletion-mode MOS transistor connected in series, one gate of the dual-gate gallium nitride enhancement-mode MOS transistor serves as a first input terminal of the NAND gate logic circuit, the other gate of the dual-gate gallium nitride enhancement-mode MOS transistor serves as a second input terminal of the NAND gate logic circuit, and a series connection point of the dual-gate gallium nitride enhancement-mode MOS transistor and the single-gate depletion-mode MOS transistor serves as an output terminal of the NAND gate logic circuit.

2. The driving circuit according to claim 1, characterized in that: The feedback control module includes a comparator circuit and a two-stage cascade inverter circuit; The inverting input terminal of the comparator circuit is connected to the feedback voltage output terminal of the boost conversion module, and the non-inverting input terminal of the comparator circuit is connected to the reference voltage; The output end of the comparator circuit is connected to the input end of the inverter circuit, and the output end of the inverter circuit is connected to the first input end of the NAND gate logic circuit.

3. The driving circuit according to claim 2, characterized in that: The boost conversion module includes a power switch tube and a voltage collection circuit, the control end of the power switch tube is connected to the output end of the driving buffer, the input end of the power switch tube is connected to the power supply through a series inductor, and the voltage at the point where the power switch tube and the inductor are connected in series is the output voltage; The input end of the voltage acquisition circuit is connected to the output voltage, and the output end of the voltage acquisition circuit serves as the feedback voltage output end of the boost conversion module.

4. The driving circuit according to claim 3, characterized in that: The voltage acquisition circuit is a voltage-dividing resistor circuit, which includes a first resistor and a second resistor connected in series, and a series connection point between the first resistor and the second resistor is connected to the inverting input terminal of the comparator circuit.

5. The driving circuit according to claim 1, characterized in that: The dual-gate GaN enhancement-mode MOS tube and the single-gate depletion-mode MOS tube are both N-channels, the drain of the single-gate depletion-mode MOS tube is connected to a power supply, and the source of the single-gate depletion-mode MOS tube is grounded via the dual-gate GaN enhancement-mode MOS tube connected in series.

6. The driving circuit according to claim 5, characterized in that: The dual-gate gallium nitride enhancement mode MOS transistor is obtained by etching two gates at different depths to modulate the threshold voltage.

7. The driving circuit according to claim 6, characterized in that: The dual-gate gallium nitride enhancement mode MOS transistor uses aluminum oxide as a dielectric layer.

8. The driving circuit according to claim 1, characterized in that: The dual-gate gallium nitride enhancement-mode MOS tube and the single-gate depletion-mode MOS tube adopt MIS-HEMT devices.

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