Silicon carbide wafer and preparation method thereof

Abstract

The present invention provides a silicon carbide wafer and a preparation method thereof. The silicon carbide wafer has no small-angle grain boundaries formed by aggregation of basal plane dislocation defects within an area of ​​5 mm from the edge of the silicon carbide wafer, and the curvature of the silicon carbide wafer is less than 15 μm.

Description

Technical Field

[0001] The present invention relates to a silicon carbide wafer, and in particular to a silicon carbide wafer with high flatness and a preparation method thereof. Background Art

[0002] Silicon carbide wafers are generally formed by growing seed crystals into crystals / ingots through a crystal growth process, and then cutting the crystals / ingots. If the surface of the seed crystal used is uneven, or is damaged or has basal plane dislocation defects (BPD), this can easily lead to inconsistent growth directions of the crystal, thereby generating more defects. If the basal plane dislocation defects of the grown crystal are concentrated in stripes and form low-angle grain boundaries, this will cause strain and stress to be unable to disperse. Generally speaking, low-angle grain boundaries refer to the interfaces between sub-grains with slightly different phase differences within the grains, which are composed of adjacent grains with a phase difference of less than 15°.

[0003] The inventors have discovered through experiments that, after cutting and processing crystals with low-angle grain boundaries, the resulting silicon carbide wafer / chip geometry becomes larger. For example, the wafer's warp and bow can easily exceed 50μm. Consequently, controlling basal plane dislocation defects to reduce or prevent the formation of low-angle grain boundaries and providing highly flat silicon carbide wafers remains a pressing issue. Summary of the Invention

[0004] The present invention provides a silicon carbide wafer and a preparation method thereof, which can prepare a silicon carbide wafer with only a small amount of or no small-angle grain boundaries, so that the wafer can still achieve high flatness after processing.

[0005] The present invention provides a silicon carbide wafer, wherein within an area of ​​5 mm from the edge of the silicon carbide wafer, there are no small-angle grain boundaries formed by the aggregation of basal plane dislocation defects, and the curvature of the silicon carbide wafer is less than 15 μm.

[0006] In an embodiment of the present invention, the warpage of the silicon carbide wafer after the grinding and polishing is less than 30 μm.

[0007] In an embodiment of the present invention, within an area of ​​10 mm from the edge of the silicon carbide wafer, the low-angle grain boundaries formed by the aggregation of basal plane dislocation defects account for less than 7% of the area.

[0008] In an embodiment of the present invention, within an area of ​​10 mm from the edge of the silicon carbide wafer, there are no low-angle grain boundaries formed by aggregation of basal plane dislocation defects.

[0009] In an embodiment of the present invention, within an area of ​​15 mm from the edge of the silicon carbide wafer, the low-angle grain boundaries formed by the aggregation of basal plane dislocation defects account for less than 10% of the area.

[0010] In an embodiment of the present invention, within an area of ​​15 mm from the edge of the silicon carbide wafer, there are no low-angle grain boundaries formed by aggregation of basal plane dislocation defects.

[0011] In an embodiment of the present invention, within an area of ​​20 mm from the edge of the silicon carbide wafer, low-angle grain boundaries formed by aggregation of basal plane dislocation defects account for less than 30% of the area.

[0012] In an embodiment of the present invention, within an area of ​​20 mm from the edge of the silicon carbide wafer, the low-angle grain boundaries formed by the aggregation of basal plane dislocation defects account for less than 20% of the area.

[0013] In an embodiment of the present invention, within an area of ​​20 mm from the edge of the silicon carbide wafer, there are no low-angle grain boundaries formed by aggregation of basal plane dislocation defects.

[0014] In an embodiment of the present invention, the density of basal plane dislocation defects in the silicon carbide wafer is 210 / cm 2 Up to 450 pieces / cm 2 .

[0015] The present invention further provides a method for preparing a silicon carbide wafer, comprising the following steps: providing a seed crystal, the seed crystal comprising a first face and a second face opposite the first face; contacting the seed crystal with a raw material of silicon carbide powder to perform a crystal growth process, wherein the silicon carbide powder contains less than 0.5 ppm of impurities; forming a crystal through the crystal growth process, and cutting the crystal to form a silicon carbide wafer.

[0016] In an embodiment of the present invention, the difference in the number of basal plane dislocation defects between the first surface and the second surface in the seed crystal is less than 25%.

[0017] Based on the foregoing, the silicon carbide wafer formed by the method of the present invention can be controlled to have no low-angle grain boundaries within a specific area within the silicon carbide wafer. Consequently, after lapping and polishing, the curvature and warpage of the silicon carbide wafer of the present invention can be controlled within ideal ranges, resulting in a highly flat silicon carbide wafer. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a flow chart of a method for preparing a silicon carbide wafer according to an embodiment of the present invention;

[0019] Figures 2A to 2CThese are the measurement results of silicon carbide wafers according to some comparative examples of the present invention using a wafer defect inspection device;

[0020] Figures 3A to 3D These are the measurement results of silicon carbide wafers according to some embodiments of the present invention using a wafer defect inspection device.

[0021] Description of reference numerals (optional, may be deleted or retained)

[0022] BPD: Basal Plane Dislocation Defect

[0023] S10, S20, S30, S40: Steps DETAILED DESCRIPTION

[0024] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0025] Figure 1 FIG. 1 is a flow chart of a method for preparing a silicon carbide wafer according to an embodiment of the present invention. Figure 1 As shown, a crystal is provided in step S10. The seed crystal includes a first surface and a second surface opposite thereto. For example, the first surface may be a carbon surface, and the second surface may be a silicon surface. In an embodiment of the present invention, the difference between the number of basal plane dislocation defects (BPD) in the first surface and the number of basal plane dislocation defects (BPD) in the second surface is less than 25%. In some embodiments, the difference between the number of basal plane dislocation defects (BPD) in the first surface and the number of basal plane dislocation defects (BPD) in the second surface is less than 20%. In other words, the defect distribution of the first surface and the second surface is similar, and the smaller the difference between the two, the better. When the basal plane dislocation defects (BPD) of the first surface and the second surface in the seed crystal are controlled to be within the above range, since the basal plane dislocation defects are not easily deformed due to thermal stress during crystal growth, thereby deteriorating the seed crystal, the generation of low-angle grain boundaries can be reduced or avoided.

[0026] Furthermore, in some embodiments, the smaller the difference in local thickness variation (LTV) and stacking fault (SF) between the first and second surfaces of the seed crystal, the better. For example, the local thickness variation (LTV) of the seed crystal on both sides can be controlled to be less than 1.0 μm, and the stacking fault (SF) can be controlled to be less than 10 ea / cm. 2 Thus, the generation of low-angle grain boundaries can be further reduced or avoided.

[0027] In the embodiment of the present invention, the seed crystal is placed in a high temperature furnace, and silicon carbide powder is placed at the bottom of the high temperature furnace as a solid evaporation source, and the high temperature furnace is heated by an induction coil. Figure 1 As shown in step S20, the seed crystal is contacted with silicon carbide powder raw material to perform a crystal growth process. In some embodiments, the impurity content in the silicon carbide powder is less than 0.5 ppm. In other words, the total detectable impurity content of all metal elements in the silicon carbide powder is less than 0.5 ppm.

[0028] In the crystal growth process, the silicon carbide powder raw material will sublime in the heat field of a high-temperature furnace, and the radial temperature gradient of the heat field is less than 50°C / cm. In other words, the seed crystal will receive the raw material (the silicon carbide powder) that is transferred from the gaseous state and solidified again, and slowly form semiconductor material on the surface of the seed crystal until a crystal / ingot of the desired size is obtained. The crystal / ingot can have different crystalline structures depending on the manufacturing method, manufacturing raw materials, and seed crystal orientation. For example, silicon carbide ingots include 4H-silicon carbide, 6H-silicon carbide, etc. 4H-silicon carbide and 6H-silicon carbide belong to the hexagonal system.

[0029] Then, if Figure 1 As shown in step S30, after the crystal / ingot is formed by the above-mentioned crystal growth process, the crystal / ingot is cut to form a silicon carbide wafer. For example, in some embodiments, the corners of the crystal are cut into equal-diameter cylinders and ground into rounded corners to prevent the corners of the wafer from breaking due to collision. Next, the crystal is sliced ​​to separate multiple wafers. The slicing method of the crystal includes cutting with a tool or steel wire in combination with abrasive particles (abrasive particles such as diamond particles).

[0030] In an embodiment of the present invention, in a silicon carbide wafer formed after slicing, within an area of ​​5 mm from the edge of the silicon carbide wafer, there are no low-angle grain boundaries formed by aggregation of basal plane dislocation defects. In some embodiments, within an area of ​​10 mm from the edge of the silicon carbide wafer, the low-angle grain boundaries formed by aggregation of basal plane dislocation defects are less than 7% of the area. In some embodiments, within an area of ​​10 mm from the edge of the silicon carbide wafer, there are no low-angle grain boundaries formed by aggregation of basal plane dislocation defects. In some embodiments, within an area of ​​15 mm from the edge of the silicon carbide wafer, the low-angle grain boundaries formed by aggregation of basal plane dislocation defects are less than 10% of the area. In some embodiments, within an area of ​​15 mm from the edge of the silicon carbide wafer, there are no low-angle grain boundaries formed by aggregation of basal plane dislocation defects. In some embodiments, within an area of ​​20 mm from the edge of the silicon carbide wafer, the low-angle grain boundaries formed by aggregation of basal plane dislocation defects are less than 30% of the area. In some embodiments, within an area of ​​20 mm from the edge of the silicon carbide wafer, low-angle grain boundaries formed by aggregation of basal plane dislocation defects account for less than 20% of the area. In some embodiments, within an area of ​​20 mm from the edge of the silicon carbide wafer, no low-angle grain boundaries formed by aggregation of basal plane dislocation defects exist.

[0031] In some embodiments, the crystal formed by the above-mentioned crystal growth process and the resulting wafers after slicing may meet at least one of the conditions in Table 1 below:

[0032] Table 1

[0033]

[0034] Then, if Figure 1 Step S40 is shown in which the silicon carbide wafer obtained after slicing is subjected to grinding and polishing processes. In an embodiment of the present invention, when the proportion of low-angle grain boundaries in the silicon carbide wafer meets the above conditions, the bow of the silicon carbide wafer after grinding and polishing can be less than 15μm, and the warp of the silicon carbide wafer after grinding and polishing can be less than 30μm.

[0035] In order to demonstrate that the method for preparing silicon carbide wafers of the present invention can reduce low-angle grain boundaries and control the bow and warp of the processed wafer within a certain range, the following comparative examples and experimental examples are provided for illustration.

[0036] Comparative Example

[0037] In the comparative example, the crystal growth process was performed using a seed crystal in which the difference in the number of basal plane dislocation defects between the first and second surfaces of the seed crystal was greater than 25%, and the impurity content in the silicon carbide powder was greater than 0.5 ppm. After the crystal obtained in the comparative example was cut into wafers, the wafers were measured using a wafer defect inspection device Lasertec SICA 88. The experimental results are shown as follows: Figures 2A to 2C shown.

[0038] Figures 2A to 2C These are the results of measurements of silicon carbide wafers of some comparative examples according to the present invention using a wafer defect inspection device. Figures 2A to 2C As shown in FIG, the results of the measurement by the wafer defect inspection device show that the silicon carbide wafers in each comparative example all have obvious stripe-shaped low-angle grain boundaries formed by the aggregation of basal plane dislocation defects (BPD). Figures 2A to 2C After processing the silicon carbide wafer, the values ​​of its bow and warp are both high. Figure 2A As shown in the comparative example of , the curvature of the silicon carbide wafer is 39.5 μm and the warpage is 60.5 μm. Figure 2B As shown in the comparative example of , the curvature of the silicon carbide wafer is 49.5 μm and the warpage is 90.5 μm. Figure 2C As shown in the comparative example, the curvature of the silicon carbide wafer is 79.5 μm and the warpage is 105.5 μm. Therefore, the silicon carbide wafer obtained according to the comparative example does not meet the requirements of the present invention that the curvature of the silicon carbide wafer after grinding and polishing is less than 15 μm and the warpage is less than 30 μm.

[0039] Experimental example

[0040] In the experimental example, the crystal growth process was performed using a seed crystal in which the difference in the number of basal plane dislocation defects between the first and second surfaces was less than 25%, and a raw material containing less than 0.5 ppm of impurities in the silicon carbide powder. After the crystal obtained in the experimental example was cut into wafers, the wafers were measured using a wafer defect inspection device Lasertec SICA 88, photoluminescence spectroscopy (PL), or other optical instruments. The experimental results are shown below. Figures 3A to 3D shown.

[0041] Figures 3A to 3D The results of measuring silicon carbide wafers by a wafer defect inspection device according to some embodiments of the present invention are as follows. Figures 3A to 3D As shown in FIG, the results of the measurement by the wafer defect inspection device showed that no obvious low-angle grain boundaries formed by the aggregation of basal plane dislocation defects (BPD) were found in the silicon carbide wafers of each experimental example. Figures 3A to 3DAfter the silicon carbide wafer is processed, the values ​​of its bow and warp both meet the requirements of the present invention that the bow of the silicon carbide wafer after grinding and polishing is less than 15 μm and the warp is less than 30 μm.

[0042] like Figure 3A As shown in the experimental example of , the curvature of the silicon carbide wafer is 12.5 μm and the warpage is 28.7 μm. Figure 3B As shown in the experimental example of , the curvature of the silicon carbide wafer is 3.5 μm and the warpage is 15.5 μm. Figure 3C As shown in the experimental example of , the curvature of the silicon carbide wafer is 9.2 μm and the warpage is 20.5 μm. Figure 3D As shown in the experimental example of the present invention, the curvature of the silicon carbide wafer is 10.5 μm and the warpage is 25.5 μm. Figures 3A to 3D In an experimental example, wafers were measured using the PL function of the Lasertec SICA 88 wafer defect inspection system, confirming that the density of basal plane dislocation defects (BPDs) in the silicon carbide wafer ranged from 210 to 450 BPDs / cm². When the density in the silicon carbide wafer falls within this range, it is expected that basal plane dislocation defects (BPDs) will not aggregate to form low-angle grain boundaries. Therefore, the silicon carbide wafers obtained in this embodiment of the present invention can have ideal flatness.

[0043] In summary, the silicon carbide wafer formed using the methods of the present invention can be controlled to have no low-angle grain boundaries within a specific area of ​​the silicon carbide wafer. Consequently, after lapping and polishing, the curvature and warpage of the silicon carbide wafer of the present invention can be controlled within ideal ranges, resulting in a highly flat silicon carbide wafer.

Claims

1. A silicon carbide wafer, characterized in that The silicon carbide wafer is formed by contacting a seed crystal with a raw material of silicon carbide powder to grow the crystal, wherein the seed crystal includes a first surface and a second surface opposite to the first surface, the difference in the number of basal plane dislocation defects between the first surface and the second surface of the seed crystal is less than 25%, and within an area of ​​5 mm from the edge of the silicon carbide wafer, there are no small-angle grain boundaries formed by the aggregation of basal plane dislocation defects, and the curvature of the silicon carbide wafer is less than 15 μm. The impurities in the silicon carbide powder are less than 0.5 ppm.

2. The silicon carbide wafer according to claim 1, wherein The warpage of the silicon carbide wafer is less than 30 μm.

3. The silicon carbide wafer according to claim 1, wherein Within an area of ​​10 mm from the edge of the silicon carbide wafer, low-angle grain boundaries formed by aggregation of basal plane dislocation defects account for less than 7% of the area.

4. The silicon carbide wafer according to claim 3, wherein Within an area of ​​10 mm from the edge of the silicon carbide wafer, there are no low-angle grain boundaries formed by aggregation of basal plane dislocation defects.

5. The silicon carbide wafer according to claim 1, wherein Within an area of ​​15 mm from the edge of the silicon carbide wafer, low-angle grain boundaries formed by aggregation of basal plane dislocation defects account for less than 10% of the area.

6. The silicon carbide wafer according to claim 5, wherein Within an area of ​​15 mm from the edge of the silicon carbide wafer, there are no low-angle grain boundaries formed by aggregation of basal plane dislocation defects.

7. The silicon carbide wafer according to claim 1, wherein Within an area of ​​20 mm from the edge of the silicon carbide wafer, low-angle grain boundaries formed by aggregation of basal plane dislocation defects account for less than 30% of the area.

8. The silicon carbide wafer according to claim 7, wherein Within an area of ​​20 mm from the edge of the silicon carbide wafer, low-angle grain boundaries formed by aggregation of basal plane dislocation defects account for less than 20% of the area.

9. The silicon carbide wafer according to claim 7, wherein Within an area of ​​20 mm from the edge of the silicon carbide wafer, there are no low-angle grain boundaries formed by aggregation of basal plane dislocation defects.

10. The silicon carbide wafer according to claim 1, wherein The density of basal plane dislocation defects in the silicon carbide wafer is 210 / cm 2 Up to 450 pieces / cm 2 .

11. A method for preparing a silicon carbide wafer, characterized in that: include: providing a seed crystal, the seed crystal comprising a first side and a second side opposite to the first side; Using a raw material of silicon carbide powder to contact the seed crystal to perform a crystal growth process, wherein the impurities in the silicon carbide powder are less than 0.5 ppm, and the difference in the number of basal plane dislocation defects between the first surface and the second surface of the seed crystal is less than 25%; and A crystal is formed through the crystal growth process, and the crystal is cut to form a silicon carbide wafer.

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