Method for manufacturing a semiconductor structure and semiconductor structure

Abstract

The present disclosure provides a semiconductor structure manufacturing method and a semiconductor structure, and relates to the technical field of semiconductors. The semiconductor structure manufacturing method comprises the following steps: providing a substrate; forming a plurality of silicon columns on the substrate, wherein the plurality of silicon columns are arranged in an array; performing a preset treatment on the silicon columns to form active columns, wherein the active columns comprise a first segment, a second segment and a third segment; forming a first gate oxide layer on the sidewalls of the second segment and the third segment; and forming a second gate oxide layer on the first gate oxide layer, wherein the length of the second gate oxide layer is less than the length of the first gate oxide layer, and the thickness of the second gate oxide layer is greater than the thickness of the first gate oxide layer. The present disclosure forms two layers of gate oxide layers with different thicknesses at different positions on the second segment of the active column, and the thickness of the gate oxide layer formed on the third segment is the same as the thickness of the thicker end of the gate oxide layer on the second segment, thereby effectively reducing gate-induced drain leakage current, and further improving the performance and yield of the semiconductor structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a method for fabricating a semiconductor structure and the semiconductor structure itself. Background Technology

[0002] Dynamic random access memory (DRAM) is a semiconductor memory that allows for high-speed, random data writing and reading, and is widely used in data storage devices. DRAM consists of multiple repeatedly arranged memory cells, each including a transistor and a capacitor. The capacitor is connected to the source and drain of the transistor through capacitor contact areas and structures. As electronic products increasingly strive for lighter, thinner, shorter, and smaller designs, the design of DRAM components is also evolving towards higher integration, higher density, and miniaturization.

[0003] With the development of semiconductor technology, the size of semiconductor devices is getting smaller and smaller. Problems such as gate-induced drain leakage (GIDL) will have a significant adverse impact on the formation of semiconductor structures, reducing the performance and yield of semiconductor structures. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0005] This disclosure provides a method for fabricating a semiconductor structure and the semiconductor structure itself.

[0006] A first aspect of this disclosure provides a method for fabricating a semiconductor structure, the method comprising: providing a substrate;

[0007] A plurality of silicon pillars are formed on the substrate, and the plurality of silicon pillars are arranged in an array;

[0008] The silicon pillar is subjected to a preset process to form an active pillar, wherein, along the first direction, the active pillar includes a first segment, a second segment, and a third segment connected in sequence;

[0009] A first gate oxide layer is formed on the sidewalls of the second and third segments;

[0010] A second gate oxide layer is formed on the first gate oxide layer. Along the first direction, the length of the second gate oxide layer is less than the length of the first gate oxide layer. The top surface of the second gate oxide layer is flush with the top surface of the third segment. The thickness of the second gate oxide layer is greater than the thickness of the first gate oxide layer.

[0011] According to some embodiments of this disclosure, the thickness of the second gate oxide layer is 1 to 2 times the thickness of the first gate oxide layer.

[0012] According to some embodiments of this disclosure, the cross-sectional shape of the silicon pillar includes a square shape, with a plane perpendicular to the first direction as the cross-section;

[0013] The step of pre-processing the silicon pillar to form an active pillar includes:

[0014] The silicon pillar is subjected to an oxidation process to form an active pillar, the cross-sectional shape of which includes a circle and / or an ellipse.

[0015] According to some embodiments of this disclosure, forming a plurality of silicon pillars on the substrate includes:

[0016] Multiple bit line isolation trenches are formed in the substrate, and the multiple bit line isolation trenches are spaced apart along the second direction. The substrate between adjacent bit line isolation trenches forms a strip.

[0017] Multiple word line isolation trenches are formed within the substrate, and the multiple word line isolation trenches are spaced apart along a third direction to divide the strip into multiple silicon pillars, wherein, along the first direction, the depth of the word line isolation trenches is less than the depth of the bit line isolation trenches.

[0018] According to some embodiments of this disclosure, the method for fabricating the semiconductor structure further includes:

[0019] A bit line isolation structure is formed within the substrate, and a plurality of the bit line isolation structures are spaced apart along the second direction.

[0020] According to some embodiments of this disclosure, forming a bit-line isolation structure within the substrate includes:

[0021] A first initial dielectric layer, an initial bit line, and a second initial dielectric layer are formed stacked within the bit line isolation trench and the word line isolation trench.

[0022] Along a first direction, a portion of the second initial dielectric layer, a portion of the initial bit line, and a portion of the first initial dielectric layer are removed to form a first trench. The retained second initial dielectric layer forms a second intermediate dielectric layer, the retained initial bit line forms a bit line, and the retained first initial dielectric layer forms a first dielectric layer.

[0023] A first initial isolation layer is formed within the first trench;

[0024] A portion of the second intermediate dielectric layer and a portion of the first initial isolation layer are removed, and the remaining second intermediate dielectric layer forms the second dielectric layer, while the remaining first initial isolation layer forms the first isolation layer.

[0025] The first isolation layer and the first dielectric layer form the bit line isolation structure, and the junction of the first segment and the second segment is flush with the top surface of the second dielectric layer.

[0026] According to some embodiments of this disclosure, forming a first gate oxide layer on the sidewalls of the second and third segments includes:

[0027] A first gate oxide layer is formed on the sidewalls of the second and third segments using atomic layer deposition (ALD) technology.

[0028] A filling region is formed between the top surface of the second dielectric layer and the sidewall of the first gate oxide layer.

[0029] According to some embodiments of this disclosure, forming a second gate oxide layer on the first gate oxide layer includes:

[0030] A sacrificial layer is formed within the filling area, and the top surface of the sacrificial layer is flush with the preset position of the second segment;

[0031] Remove a portion of the first gate oxide layer to expose the top surface of the active pillar;

[0032] A second gate oxide layer is formed, the bottom surface of the second gate oxide layer is connected to the top surface of the sacrificial layer, and the second gate oxide layer is located outside the first gate oxide layer that wraps around a portion of the sidewalls of the second segment and the third segment;

[0033] After removing the sacrificial layer, the sidewall of the second gate oxide layer forms a second trench with the sidewall of the first gate oxide layer that was originally covered by the sacrificial layer.

[0034] According to some embodiments of this disclosure, forming the second gate oxide layer includes:

[0035] The second gate oxide layer is formed using an atomic layer deposition process.

[0036] According to some embodiments of this disclosure, the method for fabricating the semiconductor structure further includes:

[0037] A word line isolation structure is formed in the second trench, and a plurality of the word line isolation structures are spaced apart along a third direction.

[0038] According to some embodiments of this disclosure, forming a word line isolation structure within the second trench includes:

[0039] An initial word line is formed in the second groove, and the plurality of the initial word lines are spaced apart along a third direction;

[0040] Along the first direction, a portion of the initial word line is removed, and the remaining initial word line forms an intermediate word line. A third trench is formed between the intermediate word line and the sidewall of the second gate oxide layer.

[0041] A third initial dielectric layer is formed within the third trench;

[0042] Along the first direction, a portion of the third initial dielectric layer and a portion of the intermediate word lines are removed to form a fourth trench spaced along the third direction. The bottom of the fourth trench exposes the top surface of the second dielectric layer. The remaining third initial dielectric layer forms the third dielectric layer, and the remaining intermediate word lines form two word lines.

[0043] The word line isolation structure is formed within the fourth groove.

[0044] A second aspect of this disclosure provides a semiconductor structure, the semiconductor structure comprising:

[0045] Base;

[0046] An active column, wherein there are multiple active columns arranged in an array within the substrate, wherein, along a first direction, the active column comprises a first segment, a second segment, and a third segment connected in sequence;

[0047] A first gate oxide layer is applied to the sidewalls of the second and third segments.

[0048] A second gate oxide layer is disposed outside the first gate oxide layer along a first direction. The length of the second gate oxide layer is less than the length of the first gate oxide layer. The top surface of the second gate oxide layer is flush with the top surface of the third segment. The thickness of the second gate oxide layer is greater than the thickness of the first gate oxide layer.

[0049] According to some embodiments of this disclosure, the thickness of the second gate oxide layer is 1 to 2 times the thickness of the first gate oxide layer.

[0050] According to some embodiments of this disclosure, the semiconductor structure further includes a plurality of bit lines, which are spaced apart along a second direction, and the bit lines are located at the bottom end of the active pillar;

[0051] The top surface of the bit line is provided with a second dielectric layer.

[0052] According to some embodiments of this disclosure, the semiconductor structure further includes a bit line isolation structure;

[0053] The bit line isolation structure includes a first dielectric layer and a first isolation layer, wherein the first dielectric layer is located between the substrate and the bottom surface of the bit line, and the first isolation layer is located between adjacent bit lines.

[0054] According to some embodiments of this disclosure, the semiconductor structure further includes word lines, which are disposed around the second segment of the active pillar. The word lines include a first word line and a second word line. The bottom surface of the first word line is close to the first segment, and the top surface of the second word line is close to the third segment. With a plane perpendicular to the second direction as the longitudinal section, the area of ​​the longitudinal section of the first word line is greater than the area of ​​the longitudinal section of the second word line.

[0055] According to some embodiments of this disclosure, the semiconductor structure further includes a plurality of word line isolation structures located between adjacent word lines, wherein a third dielectric layer is provided on the top surface of the word line, and the top surface of the third dielectric layer is flush with the top surface of the active pillar.

[0056] In the semiconductor structure fabrication method and semiconductor structure provided in this disclosure, a first gate oxide layer is formed on the sidewalls of the second and third segments of the active pillar, and a second gate oxide layer is formed on the first gate oxide layer. This increases the thickness of the gate oxide layer of the active pillar, thereby increasing the charge storage capacity of the gate oxide layer and effectively reducing the problems of gate-induced drain leakage current and inter-band tunneling. On the other hand, by making the length of the second gate oxide layer shorter than the length of the first gate oxide layer, and the thickness of the second gate oxide layer greater than the thickness of the first gate oxide layer, and making the top surface of the second gate oxide layer flush with the top surface of the third segment, two gate oxide layers of different thicknesses are formed at different positions on the second segment. The thickness of the gate oxide layer formed on the third segment is the same as the thickness of the gate oxide layer at the thicker end of the second segment, so that the potentials at both ends of the second segment are different. This is beneficial for controlling the turn-off current of the semiconductor structure, thereby effectively improving the performance and yield of the semiconductor structure.

[0057] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0058] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of these embodiments. In these drawings, similar reference numerals are used to denote similar elements. The drawings described below are some embodiments of the present disclosure, but not all embodiments. Other drawings will be readily available to those skilled in the art based on these drawings without inventive effort.

[0059] Figure 1 This is a flowchart illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0060] Figure 2 This is a schematic diagram illustrating the formation of a strip in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0061] Figure 3 This is a top view of a method for fabricating a semiconductor structure according to an exemplary embodiment, showing the formation of silicon pillars.

[0062] Figure 4 This is a top view of a method for fabricating a semiconductor structure according to an exemplary embodiment, showing the formation of an active pillar.

[0063] Figure 5 yes Figure 4 A cross-sectional view of the character line isolation groove formed in the AA direction.

[0064] Figure 6 yes Figure 4 A cross-sectional view of the isolation trench formed in the BB direction.

[0065] Figure 7 This is a schematic diagram illustrating the formation of a second initial dielectric layer along the Z-direction in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0066] Figure 8 This is a schematic diagram illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment, in which a second initial dielectric layer, an initial word line, and a first initial dielectric layer are formed along the Y direction.

[0067] Figure 9 This is a schematic diagram illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment, in which a second intermediate dielectric layer, word lines, a first dielectric layer, and a first trench are formed along the Y direction.

[0068] Figure 10 This is a schematic diagram illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment, in which a first initial isolation layer is formed along the Y direction.

[0069] Figure 11 This is a schematic diagram illustrating the formation of a second dielectric layer along the Z-direction in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0070] Figure 12 This is a schematic diagram illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment, in which a second dielectric layer and a bit line isolation structure are formed along the Y direction.

[0071] Figure 13 This is a schematic diagram illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment, in which a first gate oxide layer is formed along the Z direction.

[0072] Figure 14This is a schematic diagram illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment, in which a first gate oxide layer is formed along the Y direction.

[0073] Figure 15 This is a schematic diagram illustrating the formation of a sacrificial layer along the Z-direction in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0074] Figure 16 This is a schematic diagram illustrating the formation of a sacrificial layer along the Y direction in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0075] Figure 17 This is a schematic diagram illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment, in which a second gate oxide layer is formed along the Z-direction.

[0076] Figure 18 This is a schematic diagram illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment, in which a second gate oxide layer is formed along the Y direction.

[0077] Figure 19 This is a schematic diagram illustrating the formation of a second trench along the Z-direction in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0078] Figure 20 This is a schematic diagram illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment, in which a second trench is formed along the Y direction.

[0079] Figure 21 This is a schematic diagram illustrating the formation of initial word lines along the Z direction in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0080] Figure 22 This is a schematic diagram illustrating the formation of initial word lines along the Y direction in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0081] Figure 23 This is a schematic diagram illustrating the formation of an intermediate word line along the Z direction in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0082] Figure 24 This is a schematic diagram illustrating the formation of an intermediate word line along the Y direction in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0083] Figure 25 This is a schematic diagram illustrating the formation of a third initial dielectric layer along the Z-direction in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0084] Figure 26 This is a schematic diagram illustrating the formation of a third initial dielectric layer along the Y direction in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0085] Figure 27 This is a schematic diagram illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment, in which a third dielectric layer and a fourth trench are formed along the Z direction.

[0086] Figure 28 This is a schematic diagram illustrating a method for fabricating a semiconductor structure in which a word line isolation structure is formed along the Z direction, according to an exemplary embodiment.

[0087] Figure label:

[0088] 10. Substrate; 20. Silicon pillar; 30. Bit line isolation trench; 40. Strip; 50. Word line isolation trench; 60. Active pillar; 70. Bit line isolation structure; 80. First dielectric layer; 81. First initial dielectric layer; 90. Bit line; 91. Initial bit line; 100. Second dielectric layer; 101. Second initial dielectric layer; 102. Second intermediate dielectric layer; 110. First trench; 120. First isolation layer; 121. First initial Isolation layer; 130, First gate oxide layer; 140, Second gate oxide layer; 150, Fill region; 160, Sacrificial layer; 170, Second trench; 180, Word line isolation structure; 190, Word line; 191, Initial word line; 192, Intermediate word line; 200, Third trench; 210, Third dielectric layer; 211, Third initial dielectric layer; 220, Fourth trench; 601, First segment; 602, Second segment; 603, Third segment. Detailed Implementation

[0089] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions in the disclosed embodiments will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0090] Dynamic random access memory (DRAM) is a semiconductor memory that allows for high-speed, random data writing and reading, and is widely used in data storage devices. DRAM consists of multiple repeatedly arranged memory cells, each including a transistor and a capacitor. The capacitor is connected to the source and drain of the transistor through capacitor contact areas and structures. As electronic products increasingly strive for lighter, thinner, shorter, and smaller designs, the design of DRAM components is also evolving towards higher integration, higher density, and miniaturization.

[0091] In semiconductor structures, a transistor can be understood as a current-switching structure made of semiconductor material. A metal gate is placed between the source and drain of the transistor, and this metal gate is used to control the flow of current between the source and drain. One type of transistor is the GAA transistor (Gate-All-Around), which uses gate-all-around technology. With the development of semiconductor technology, the size of semiconductor devices is becoming smaller and smaller. During the fabrication of GAA transistors, there is a problem of gate-induced drain leakage (GIDL), which reduces the performance and yield of the semiconductor structure.

[0092] In the semiconductor structure fabrication method and semiconductor structure provided in this disclosure, a first gate oxide layer is formed on the sidewalls of the second and third segments of the active pillar, and a second gate oxide layer is formed on the first gate oxide layer. This increases the thickness of the gate oxide layer of the active pillar, thereby increasing the charge storage capacity of the gate oxide layer and effectively reducing the problems of gate-induced drain leakage current and inter-band tunneling. On the other hand, by making the length of the second gate oxide layer shorter than the length of the first gate oxide layer, and the thickness of the second gate oxide layer greater than the thickness of the first gate oxide layer, and making the top surface of the second gate oxide layer flush with the top surface of the third segment, two gate oxide layers of different thicknesses are formed at different positions on the second segment. The thickness of the gate oxide layer formed on the third segment is the same as the thickness of the gate oxide layer at the thicker end of the second segment, so that the potentials at both ends of the second segment are different. This is beneficial for controlling the turn-off current of the semiconductor structure, thereby effectively improving the performance and yield of the semiconductor structure.

[0093] This disclosure provides a method for fabricating a semiconductor structure in exemplary embodiments, which will be described below in conjunction with... Figures 1-28 The methods for fabricating semiconductor structures are introduced.

[0094] This embodiment does not limit the semiconductor structure. The following description will take dynamic random access memory (DRAM) as an example, but this embodiment is not limited to this. The semiconductor structure in this embodiment can also be other structures, such as GAA transistors or vertical gate ring transistors.

[0095] like Figure 1 As shown, an exemplary embodiment of this disclosure provides a method for fabricating a semiconductor structure, comprising the following steps:

[0096] Step S100: Provide a substrate.

[0097] Step S200: Multiple silicon pillars are formed on the substrate, and the multiple silicon pillars are arranged in an array.

[0098] Step S300: Perform a preset process on the silicon pillar to form an active pillar. Along the first direction, the active pillar includes a first segment, a second segment, and a third segment connected in sequence.

[0099] Step S400: Form a first gate oxide layer on the sidewalls of the second and third segments.

[0100] Step S500: A second gate oxide layer is formed on the first gate oxide layer. Along the first direction, the length of the second gate oxide layer is less than the length of the first gate oxide layer. The top surface of the second gate oxide layer is flush with the top surface of the third segment. The thickness of the second gate oxide layer is greater than the thickness of the first gate oxide layer.

[0101] According to an exemplary embodiment, this embodiment is a further explanation of step S100 above.

[0102] like Figure 2 As shown, a substrate 10 is provided. The substrate 10 serves as a support component for the dynamic random access memory (DRAM), supporting other components disposed thereon. The substrate 10 can be made of a semiconductor material, which can be one or more of silicon, germanium, silicon-germanium compounds, and silicon-carbide compounds. In this embodiment, the substrate 10 uses silicon. However, the use of silicon as the substrate 10 in this embodiment is for the convenience of those skilled in the art in understanding the subsequent formation method and does not constitute a limitation. In practical applications, a suitable substrate material can be selected according to requirements.

[0103] According to an exemplary embodiment, this embodiment is a further explanation of step S200 above.

[0104] like Figure 3 As shown, silicon pillars 20 are formed on the substrate 10. Multiple silicon pillars 20 are arranged in an array on the substrate 10, that is, multiple silicon pillars 20 can be arranged in a multi-row, multi-column manner. Taking a plane perpendicular to the first direction X as a cross-section, the cross-sectional shape of the silicon pillar 20 includes square shapes. (Refer to...) Figure 3 As shown in the figure, taking the orientation shown as an example, the first direction X is the extension direction from the bottom surface of the base 10 to the top surface of the base 10.

[0105] Reference Figure 2 and Figure 3 As shown, in some embodiments, the silicon pillars 20 arranged in an array on the substrate 10 can be formed using the following methods:

[0106] First, a plurality of bit line isolation trenches 30 are formed within the substrate 10, and the plurality of bit line isolation trenches 30 are spaced apart along the second direction Y. A strip-shaped body 40 is formed between adjacent bit line isolation trenches 30.

[0107] During the process of forming bit line isolation trenches 30 on the substrate 10, a mask layer with a mask pattern can be formed on the substrate 10. The direction from the top surface of the substrate 10 to the bottom surface of the substrate 10 is taken as the extension direction. Along the extension direction, a portion of the substrate 10 is removed according to the mask pattern to form a plurality of bit line isolation trenches 30 spaced apart along the second direction Y.

[0108] Then, a plurality of word line isolation trenches 50 are formed within the substrate 10. The plurality of word line isolation trenches 50 are spaced apart along a third direction Z. The strip 40 is divided into a plurality of silicon pillars 20 by the word line isolation trenches 50 arranged along the third direction Z. In this embodiment, the depth of the word line isolation trenches 50 along the first direction X is less than the depth of the bit line isolation trenches 30.

[0109] Reference Figure 2 As shown in the figure, taking the orientation shown as an example, the third direction Z is an extension direction parallel to the front side of the base 10. The second direction Y and the third direction Z intersect on the same horizontal plane. The second direction Y can be set to intersect the third direction Z at a predetermined angle, for example, the second direction Y and the third direction Z can be set to be perpendicular to each other.

[0110] During the process of forming word line isolation trenches 50 on the substrate 10, a mask layer with a mask pattern can be formed on the substrate 10. The direction from the top surface of the substrate 10 to the bottom surface of the substrate 10 is taken as the extension direction. Along the extension direction, a portion of the substrate 10 is removed according to the mask pattern to form a plurality of word line isolation trenches 50 spaced at intervals along the third direction Z.

[0111] By forming multiple bit line isolation trenches 30 and multiple word line isolation trenches 50 on the substrate 10, multiple silicon pillars 20 arranged in a multi-row, multi-column manner are formed on the substrate 10. The word line isolation trenches 50 and bit line isolation trenches 30 facilitate the subsequent formation of other functional layers of the semiconductor structure on the substrate 10, and the formation process of the silicon pillars 20 is simple, making it easy to control the formation size of the subsequent active pillars 60.

[0112] It should be noted that in some embodiments, the silicon pillars 20 may also be formed on the top surface of the substrate 10 by a silicon epitaxial growth process, or they may be formed by depositing multiple functional layers on the top surface of the substrate 10 and then etching away some of the functional layers, so that multiple silicon pillars 20 are arranged in multiple rows and columns on the substrate 10.

[0113] According to an exemplary embodiment, this embodiment is a further explanation of step S300 above.

[0114] like Figures 4 to 6 As shown, the silicon pillar 20 is pre-processed to form an active pillar 60.

[0115] The pre-processing includes an oxidation process, where the silicon pillar 20 is oxidized followed by etching or cleaning to form an active pillar 60. The oxidation process passivates the edges of the silicon pillar 20, changing its cross-sectional shape from square to circular or elliptical. It should be noted that in some embodiments, the oxidation process includes thermal oxidation or steam oxidation. In this process, the silicon pillar 20 is exposed to the environment, and an oxide layer, such as silicon oxide, is formed on its surface through thermal or steam oxidation. This oxide layer can then be removed by etching or cleaning, thereby passivating the edges of the silicon pillar 20.

[0116] After the oxidation process of the silicon pillar 20 is completed, an ion implantation process is performed on the silicon pillar 20, which has a circular or elliptical cross-sectional shape, to form an active pillar 60. As an example, the method of using ion implantation to process the silicon pillar 30 to form the drain and source of the subsequent active pillar 60 is known to those skilled in the art and will not be described in detail here. It should be noted that in this step, the silicon pillar 20 treated by the ion implantation process forms the active pillar 60. Along the first direction X, the active pillar 60 includes a first segment 601, a second segment 602, and a third segment 603 connected in sequence, with the bottom surface of the first segment 601 connected to the substrate 10. The first segment 601 can form a source or drain, the second segment 602 can form a gate, and the third segment 603 can form a source or drain. In this embodiment, the first segment 601 forms the drain, and the third segment 603 forms the source.

[0117] In this embodiment, the edges of the silicon pillar 20 are passivated by an oxidation process, which can improve the adhesion of the subsequent active pillar 60, so that the functional layers formed later, such as dielectric layers, word lines, bit lines, etc., can be well connected with the active pillar 60, thereby improving the performance and yield of the semiconductor structure.

[0118] like Figure 12 As shown, in some embodiments, after the silicon pillar 20 is processed by an oxidation process to form an active pillar 60, in order to facilitate the subsequent formation of multiple bit lines spaced along the second reverse Y interval in the substrate 10 and to achieve insulation between adjacent bit lines, a bit line isolation structure 70 can be formed in the substrate 10.

[0119] In some embodiments, the bit line isolation structure 70 can be formed using the following methods:

[0120] First, refer to Figure 7 and Figure 8 As shown, a first initial dielectric layer 81, an initial bit line 91, and a second initial dielectric layer 101 are sequentially formed in the bit line isolation trench 30 and the word line isolation trench 50.

[0121] A first sacrificial dielectric layer (not shown in the figure) can be deposited in the bit line isolation trench 30 and word line isolation trench 50 using atomic layer deposition, physical vapor deposition, or chemical vapor deposition. The first sacrificial dielectric layer completely fills the bit line isolation trench 30 and word line isolation trench 50. A portion of the first sacrificial dielectric layer is etched away along the first direction X, and the remaining first sacrificial dielectric layer forms a first initial dielectric layer 81. The top surface of the first initial dielectric layer 81 is lower than the bottom surface of the word line isolation trench 50.

[0122] After the first initial dielectric layer 81 is formed, a first bit line (not shown in the figure) is formed on the first initial dielectric layer 81 using atomic layer deposition, physical vapor deposition, or chemical vapor deposition. The top surface of the first bit line is flush with the top surface of the bit line isolation trench 30. A portion of the first bit line is etched away along the first direction X, wherein the etching endpoint of the first bit line is flush with the bottom surface of the word line isolation trench 50. The retained first bit line forms the initial bit line 91, that is, the initial bit line 91 only fills the bit line isolation trench 30.

[0123] After the initial bit line 91 is formed, a second initial dielectric layer 101 is formed on the initial bit line 91 using atomic layer deposition, physical vapor deposition, or chemical vapor deposition. The top surface of the second initial dielectric layer 101 is flush with the top surface of the bit line isolation trench 30.

[0124] Then, refer to Figure 9 As shown, along the first direction X, a portion of the second initial dielectric layer 101, a portion of the initial bit line 91, and a portion of the first initial dielectric layer 81 are etched away to form a plurality of first trenches 110 spaced apart along the second direction Y. The retained first initial dielectric layer 81 forms a first dielectric layer 80, the retained initial bit line 91 forms a bit line 90, and the retained second initial dielectric layer 101 forms a second intermediate dielectric layer 102. The material of the first dielectric layer 80 includes, but is not limited to, silicon nitride, silicon dioxide, or silicon oxynitride. The material of the bit line 90 includes, but is not limited to, cobalt silicide or platinum-nickel silicide.

[0125] Then, refer to Figure 10 As shown, a first initial isolation layer 121 is formed in the first trench 110 by atomic layer deposition, physical vapor deposition or chemical vapor deposition.

[0126] Finally, refer to Figure 11 and Figure 12As shown, along the first direction X, a portion of the second intermediate dielectric layer 102 and a portion of the first initial isolation layer 121 are etched away. It should be noted that the etching endpoints of the second intermediate dielectric layer 102 and the first initial isolation layer 121 can be flush with the boundary between the second segment 602 and the first segment 601 of the active pillar 60. The retained second intermediate dielectric layer 102 forms the second dielectric layer 100. The retained first initial isolation layer 121 forms the first isolation layer 120.

[0127] The material of the second dielectric layer 100 includes, but is not limited to, silicon nitride, silicon dioxide, or silicon oxynitride. It should be noted that, in one embodiment, the material of the first dielectric layer 80 can be the same as the material of the second dielectric layer 100, thereby reducing process complexity and cost.

[0128] The material of the first isolation layer 120 includes, but is not limited to, silicon oxide or silicon nitride. In this embodiment, the first dielectric layer 80 and the first isolation layer 120 form a bit line isolation structure 70.

[0129] In some embodiments, the bit line isolation structure 70 may also be a silicon oxide-silicon nitride-silicon oxide structure, i.e., an "ONO" structure, but is not limited thereto.

[0130] The bit line isolation structure 70 formed within the substrate 10 can achieve insulation between adjacent bit lines 90, ensuring the performance and yield of the semiconductor structure.

[0131] On the other hand, the bit line formation method in this embodiment is simple and easy to control and operate. It should be noted that the bit line can be connected to the drain in the subsequently formed active pillar 60, the gate of the transistor is connected to the word line, and the source is connected to the capacitor structure. The voltage signal on the word line can control the transistor to turn on or off, thereby reading the data information stored in the capacitor structure through the bit line, or writing the data information into the capacitor structure for storage through the bit line.

[0132] According to an exemplary embodiment, this embodiment is a further explanation of step S400 above.

[0133] like Figure 13 and Figure 14 As shown, a first gate oxide layer 130 is formed on the sidewalls of the second segment 602 and the third segment 603 of the active pillar 60.

[0134] After the bit line isolation structure 70 is formed as described above, the first gate oxide layer 130 is formed on the sidewall of the second section 602 of the active pillar 60, and on the sidewall and top surface of the third section 603 using an atomic layer deposition process.

[0135] In some embodiments, an initial gate oxide layer (not shown) can be formed on the second segment 602 and the third segment 603 of the active pillar 60 using an atomic layer deposition process. The first initial gate oxide layer is formed on the sidewalls of the second segment 602, the sidewalls and top surface of the third segment 603, and the top surface of the second dielectric layer 100 and the bit line isolation structure 70. Then, the first initial gate oxide layer on the top surface of the second dielectric layer 100 and the bit line isolation structure 70 is etched away, leaving the first initial gate oxide layer on the sidewalls of the second segment 602, the sidewalls and top surface of the third segment 603. The retained first initial gate oxide layer forms the first gate oxide layer 130. The material of the first gate oxide layer 130 may include, but is not limited to, silicon dioxide, silicon monoxide, hafnium oxide or titanium oxide.

[0136] In this embodiment, atomic layer deposition (ALD) is characterized by a slow deposition rate, high film density, and good step coverage. The first gate oxide layer 130 formed by ALD can effectively isolate and protect the second segment 602 of the active pillar, i.e., the gate, even with a relatively thin thickness, avoiding occupying a large space and facilitating the subsequent filling or formation of other structural layers.

[0137] According to an exemplary embodiment, this embodiment is a further explanation of step S500 above.

[0138] like Figure 19 and Figure 20 As shown, a second gate oxide layer 140 is formed on the first gate oxide layer 130. Along the first direction X, the length of the second gate oxide layer 140 is less than the length of the first gate oxide layer 130, the top surface of the second gate oxide layer 140 is flush with the top surface of the third segment 603, and the thickness of the second gate oxide layer 140 is greater than the thickness of the first gate oxide layer 130.

[0139] In some embodiments, the second gate oxide layer 140 may be formed using the following methods:

[0140] First, refer to Figure 14 As shown, after the first gate oxide layer 130 is formed, a filling region 150 is formed between the top surface of the second dielectric layer 100 and the sidewall of the first gate oxide layer 130.

[0141] Among them, reference Figure 15 and Figure 16As shown, an initial sacrificial layer (not shown) is formed in the fill region 150 using atomic layer deposition, physical vapor deposition, or chemical vapor deposition, completely filling the fill region 150. Then, a portion of the initial sacrificial layer is removed by etching, wherein the etching endpoint of the initial sacrificial layer is flush with a predetermined position of the second segment 602. The retained initial sacrificial layer forms the sacrificial layer 160. In this step, the predetermined position of the second segment 602 can be one-third to two-thirds of its height. In one embodiment, the predetermined position of the second segment 602 is at half its height. In this embodiment, along the first direction X, the portion of the second segment 602 corresponding to the height of the sacrificial layer 160 forms a first sub-segment, and the remaining portion of the second segment 602 not corresponding to the sacrificial layer 160 forms a second sub-segment, thereby facilitating the formation of a second gate oxide layer 140 of different thicknesses at different positions in the second segment 602.

[0142] Then, as Figure 17 and Figure 18 As shown, the first gate oxide layer 130 located on top of the third segment 603 is removed by chemical mechanical polishing or etching, exposing the top surface of the active pillar 60.

[0143] Then, continue to refer to Figure 17 and Figure 18 As shown, a second gate oxide layer 140 is formed on a portion of the sidewall of the second segment 602 and the sidewall of the third segment 603. That is, the second gate oxide layer 140 is disposed outside the portion of the first gate oxide layer 130 corresponding to the second sub-segment and outside the portion of the first gate oxide layer 130 on the sidewall of the third segment 603. The bottom surface of the second gate oxide layer 140 is connected to the top surface of the sacrificial layer 160.

[0144] In some embodiments, a second gate oxide layer 140 may be formed on the sidewalls of the second sub-segment of the second segment 602 and the sidewalls of the third segment 603 by an atomic layer deposition process.

[0145] Finally, refer to Figure 19 and Figure 20 As shown, the sacrificial layer 160 is removed by etching. The sidewall of the second gate oxide layer 140 forms a second trench 170 with the sidewall of the first gate oxide layer 130 that was originally covered by the sacrificial layer 160.

[0146] In this embodiment, a second gate oxide layer 140 is formed on the sidewalls of the first gate oxide layer 130 corresponding to the second sub-segment of the second segment 602 and the third segment 603 using an atomic layer deposition process. The material of the second gate oxide layer 140 may include, but is not limited to, silicon dioxide, silicon monoxide, hafnium oxide, or titanium oxide. The material of the second gate oxide layer 140 may be the same as that of the first gate oxide layer 130, or the material of the second gate oxide layer 140 may be different from that of the first gate oxide layer 130.

[0147] Because a sacrificial layer 160 is formed in the filling region 150 before the second gate oxide layer 140 is formed, and the sacrificial layer 160 partially blocks the second segment 602, the formation length of the second gate oxide layer 140 in the first direction X is less than the length of the first gate oxide layer 130. Simultaneously, during the formation of the second gate oxide layer 140, the formation thickness of the second gate oxide layer 140 is controlled to be greater than the thickness of the first gate oxide layer 130.

[0148] In semiconductor structures, GAA transistors suffer from gate-induced drain current (GIDL). This GIDL occurs because the thin gate oxide layer reduces its charge storage capacity. When the GAA transistor is in a static state, electrons generated at the gate or a small number of current carriers can pass through the gate oxide layer into the drain, creating a high electric field and causing leakage current. In this embodiment, a first gate oxide layer 130 and a second gate oxide layer 140 are sequentially formed on the sidewall of the second segment 602 of the active pillar 60, resulting in varying gate oxide thicknesses at different locations on the second segment 602. This increases the charge storage capacity of the gate oxide layer, preventing electrons generated at the gate or a small number of current carriers from passing through the gate oxide layer into the source or drain of the semiconductor structure, thus reducing GIDL and improving the performance and yield of the semiconductor structure.

[0149] like Figure 28 As shown, after the second gate oxide layer 140 is formed, a word line isolation structure 180 can also be formed in the second trench 170. Multiple word line isolation structures 180 are provided and spaced apart along the third direction Z.

[0150] In some embodiments, the word line isolation structure 180 can be formed using the following methods:

[0151] Reference Figure 21 and Figure 22As shown, initial word lines 191 are formed in the second trench 170 using atomic layer deposition, physical vapor deposition, or chemical vapor deposition. The initial word lines 191 fill the second trench 170 completely, and there are multiple initial word lines 191 spaced apart along the third direction Z.

[0152] Reference Figure 23 and Figure 24 As shown, a portion of the initial word line 191 is removed by etching along the first direction X. The etching endpoint of the initial word line 191 is flush with the boundary between the second segment 602 and the third segment 603. The retained initial word line 191 forms an intermediate word line 192. A third trench 200 is formed between the intermediate word line 192 and the sidewall of the second gate oxide layer 140.

[0153] Reference Figure 25 and Figure 26 As shown, a third initial dielectric layer 211 is formed in the third trench 200 by atomic layer deposition, physical vapor deposition or chemical vapor deposition.

[0154] like Figure 27 As shown, along the first direction X, a portion of the third initial dielectric layer 211 and a portion of the intermediate word lines 192 are etched away to form a plurality of fourth trenches 220 spaced apart along the third direction Z. The bottom of the fourth trenches 220 exposes the top surface of the second dielectric layer 100. The retained third initial dielectric layer 211 forms the third dielectric layer 210. The retained intermediate word lines 192 form two spaced word lines 190. The material of the third dielectric layer 210 includes, but is not limited to, silicon nitride, silicon dioxide, or silicon oxynitride. The material of the word lines 190 includes, but is not limited to, tungsten or polysilicon. It should be noted that the thickness of the word lines formed by materials such as tungsten or polysilicon does not affect the potential of the word lines.

[0155] like Figure 28 As shown, a word line isolation structure 180 is formed within the fourth trench 220 using atomic layer deposition, physical vapor deposition, or chemical vapor deposition. The material of the word line isolation structure 180 includes nitrides, oxides, high-k dielectric materials, or other suitable insulating materials.

[0156] In some embodiments, the gate structure of the duplex function is generally obtained by depositing word line metal layers of different materials at the gate. However, the process required to deposit metal layers of different materials is relatively complex, and an isolation layer is required between metal layers of different materials due to diffusion issues.

[0157] In this embodiment, the word line 190 is formed by a single deposition, using tungsten metal or polycrystalline silicon. Simultaneously, a first gate oxide layer 130 is formed on the sidewalls of the second segment 602 and the third segment 603. Then, a second gate oxide layer 140 is formed on the first gate oxide layer 130 on the sidewalls corresponding to the second sub-segment of the second segment 602 and the sidewalls corresponding to the third segment 603. This results in different thicknesses of the gate oxide layer at different locations in the second segment 602, achieving a duplex function effect. This not only simplifies the manufacturing process but also makes it easier to control and implement. Specifically, the thickness of the gate oxide layer near the third segment 603 in the second segment 602 is greater than the thickness of the gate oxide layer near the first segment 601 in the second segment 602. Therefore, when the transistor formed by the semiconductor structure of this embodiment, such as the GAA transistor, is used, the gate oxide layer thickness near the source is increased. In order for the transistor to conduct, the turn-on voltage VT applied at this end will increase, which will correspondingly increase the potential of the word line 190 near the third segment 603, thereby forming a potential difference between the corresponding word lines 190 at both ends of the second segment 602.

[0158] Furthermore, as the turn-on voltage VT of the source terminal increases, the source voltage Vs at the source terminal will also increase. The turn-off current (Ioff) and the source voltage Vs are related as shown in the following formula:

[0159] I off∝e -(Vs*ε / kt)

[0160] Where ε / kt is a constant, approximately 0.0256. Therefore, when the source voltage Vs at the source terminal increases, the turn-off current (Ioff) decreases. Since the turn-off current and the source voltage Vs satisfy an exponential relationship of e, when the thickness of the gate oxide layer at the source terminal of the transistor increases, the turn-off current decreases exponentially. This facilitates the control of the turn-off current of the semiconductor structure, thereby reducing the gate-induced drain leakage current and inter-band tunneling of the semiconductor structure, and improving the performance and yield of the semiconductor structure.

[0161] Among them, reference Figure 28 As shown, in some embodiments, the thickness of the second gate oxide layer 140 is 1 to 2 times the thickness of the first gate oxide layer 130. Therefore, in this embodiment, the thickness of the gate oxide layer of the second segment 602 near the third segment 603 is 2 to 3 times the thickness of the gate oxide layer of the second segment 602 near the first segment 601. In one specific embodiment, the thickness of the second gate oxide layer 140 is 1.5 times the thickness of the first gate oxide layer 130. By setting the above thickness ratio, the turn-off current of the semiconductor structure can be reduced by 6 orders of magnitude, and the induced drain leakage current and inter-band tunneling of the semiconductor structure are also reduced, thereby improving the performance and yield of the semiconductor structure.

[0162] like Figure 26 and Figure 28 As shown, an exemplary embodiment of this disclosure provides a semiconductor structure, wherein the semiconductor structure includes: a substrate 10, an active pillar 60, a first gate oxide layer 130, and a second gate oxide layer 140.

[0163] For example, there are multiple active pillars 60, and the multiple active pillars 60 are arranged in an array within the substrate 10. Along the first direction X, the active pillar 60 includes a first segment 601, a second segment 602, and a third segment 603 connected in sequence.

[0164] The first gate oxide layer 130 is wrapped around the sidewalls of the second section 602 and the third section 603.

[0165] The second gate oxide layer 140 is disposed outside the first gate oxide layer 130, and its length along the first direction X is less than that of the first gate oxide layer 130. The top surface of the second gate oxide layer 140 is flush with the top surface of the third segment 603. The thickness of the second gate oxide layer 140 is greater than that of the first gate oxide layer 130. In some embodiments, the thickness of the second gate oxide layer 140 is 1 to 2 times the thickness of the first gate oxide layer 130.

[0166] In this embodiment, by forming a first gate oxide layer on the sidewalls of the second and third segments of the active pillar, and then forming a second gate oxide layer on top of the first gate oxide layer, the thickness of the gate oxide layer of the active pillar is increased, thereby increasing the charge storage capacity of the gate oxide layer and effectively reducing the problems of gate-induced drain leakage current and inter-band tunneling. On the other hand, the length of the second gate oxide layer is shorter than that of the first gate oxide layer, while the thickness of the second gate oxide layer is greater than that of the first gate oxide layer. The top surface of the second gate oxide layer is flush with the top surface of the third segment. Thus, two gate oxide layers of different thicknesses are formed at different positions on the second segment, and the thickness of the gate oxide layer formed on the third segment is the same as the thickness of the gate oxide layer at the thicker end of the second segment. This results in different potentials at both ends of the second segment, which is beneficial for controlling the turn-off current of the semiconductor structure and thus effectively improving the performance and yield of the semiconductor structure.

[0167] like Figure 26 As shown, in some embodiments, the semiconductor structure further includes a plurality of bit lines 90 disposed on the substrate 10. The plurality of bit lines 90 are spaced apart along a second direction Y, and the bit lines 90 are located below the active pillars 60. The bit lines 90 are connected to the first segment 601 of the plurality of active pillars 60 along a third direction Z and on the same straight line. A second dielectric layer 100 is disposed on the top surface of the bit lines 90.

[0168] like Figure 26As shown, in some embodiments, the semiconductor structure further includes a plurality of bit line isolation structures 70 disposed on the substrate 10. The plurality of bit line isolation structures 70 are spaced apart along the second direction Y. Each bit line isolation structure 70 includes a first dielectric layer 80 and a first isolation layer 120. The first dielectric layer 80 is located between the substrate 10 and the bit lines 90. The first isolation layer 120 is located between adjacent bit lines 90. The bit line isolation structures 70 are used to achieve insulation between adjacent bit lines 90 subsequently formed within the substrate 10, ensuring the performance and yield of the semiconductor structure.

[0169] like Figure 28 As shown, in some embodiments, the semiconductor structure further includes word lines 190 disposed within the substrate 10. Word lines 190 surround the second segment 602 of the active pillar 60. Word lines 190 include a first word line and a second word line, with the bottom surface of the first word line close to the first segment 601 and the top surface of the second word line close to the third segment 603. Taking a plane perpendicular to the second direction Y as a longitudinal section, the longitudinal cross-sectional area of ​​the first word line is larger than that of the second word line. It should be noted that the junction of the first and second word lines can be flush with the bottom surface of the second gate oxide layer 140.

[0170] The first and second letter lines can be formed by a single deposition or by multiple depositions. In some embodiments, the first and second letter lines are made of the same material.

[0171] like Figure 28 As shown, in some embodiments, the semiconductor structure further includes a plurality of word line isolation structures 180 disposed within the substrate 10. The word line isolation structures 180 are located between adjacent word lines 190, and a third dielectric layer 210 is disposed on the top surface of the word line 190, the top surface of the third dielectric layer 210 being flush with the top surface of the active pillar 60. The word line isolation structures 180 are used to achieve insulation between adjacent word lines 190, thereby ensuring the performance and yield of the semiconductor structure.

[0172] In the description of this disclosure, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this disclosure.

[0173] It is understood that the terms "first," "second," etc., as used in this disclosure may be used to describe various structures, but these structures are not limited by these terms. These terms are only used to distinguish one structure from another.

[0174] In one or more accompanying drawings, the same elements are represented by similar reference numerals. For clarity, many parts in the drawings are not drawn to scale. Furthermore, certain well-known parts may not be shown. For simplicity, a structure obtained after several steps may be depicted in a single drawing. Many specific details of this disclosure, such as the structure, materials, dimensions, processing methods, and techniques of the devices, are described below to provide a clearer understanding of the disclosure. However, as those skilled in the art will understand, this disclosure may be implemented without adhering to these specific details.

[0175] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, The method for fabricating the semiconductor structure includes: Provide a base; A plurality of silicon pillars are formed on the substrate, and the plurality of silicon pillars are arranged in an array; The silicon pillar is subjected to a preset process to form an active pillar, wherein, along the first direction, the active pillar includes a first segment, a second segment, and a third segment connected in sequence; A first gate oxide layer is formed on the sidewalls of the second and third segments; A second gate oxide layer is formed on the first gate oxide layer. Along the first direction, the length of the second gate oxide layer is less than the length of the first gate oxide layer. The top surface of the second gate oxide layer is flush with the top surface of the third segment. The thickness of the second gate oxide layer is greater than the thickness of the first gate oxide layer. A second trench is formed between the second gate oxide layer and the first gate oxide layer, and a word line isolation structure is formed within the second trench.

2. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The thickness of the second gate oxide layer is 1 to 2 times the thickness of the first gate oxide layer.

3. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The cross-sectional shape of the silicon pillar includes a square shape, with a plane perpendicular to the first direction as its cross-section; The step of pre-processing the silicon pillar to form an active pillar includes: The silicon pillar is subjected to an oxidation process to form an active pillar, the cross-sectional shape of which includes a circle and / or an ellipse.

4. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The formation of a plurality of silicon pillars on the substrate includes: Multiple bit line isolation trenches are formed in the substrate, and the multiple bit line isolation trenches are spaced apart along the second direction. The substrate between adjacent bit line isolation trenches forms a strip. Multiple word line isolation trenches are formed within the substrate, and the multiple word line isolation trenches are spaced apart along a third direction to divide the strip into multiple silicon pillars, wherein, along the first direction, the depth of the word line isolation trenches is less than the depth of the bit line isolation trenches.

5. The method for fabricating a semiconductor structure according to claim 4, characterized in that, The method for fabricating the semiconductor structure further includes: A bit line isolation structure is formed within the substrate, and a plurality of the bit line isolation structures are spaced apart along the second direction.

6. The method for fabricating a semiconductor structure according to claim 5, characterized in that, The formation of a bit-line isolation structure within the substrate includes: A first initial dielectric layer, an initial bit line, and a second initial dielectric layer are formed stacked within the bit line isolation trench and the word line isolation trench. Along a first direction, a portion of the second initial dielectric layer, a portion of the initial bit line, and a portion of the first initial dielectric layer are removed to form a first trench. The retained second initial dielectric layer forms a second intermediate dielectric layer, the retained initial bit line forms a bit line, and the retained first initial dielectric layer forms a first dielectric layer. A first initial isolation layer is formed within the first trench; A portion of the second intermediate dielectric layer and a portion of the first initial isolation layer are removed, and the remaining second intermediate dielectric layer forms the second dielectric layer, while the remaining first initial isolation layer forms the first isolation layer. The first isolation layer and the first dielectric layer form the bit line isolation structure, and the junction of the first segment and the second segment is flush with the top surface of the second dielectric layer.

7. The method for fabricating a semiconductor structure according to claim 6, characterized in that, The formation of a first gate oxide layer on the sidewalls of the second and third segments includes: A first gate oxide layer is formed on the sidewalls of the second and third segments using atomic layer deposition (ALD) technology. A filling region is formed between the top surface of the second dielectric layer and the sidewall of the first gate oxide layer.

8. The method for fabricating a semiconductor structure according to claim 7, characterized in that, The formation of a second gate oxide layer on the first gate oxide layer includes: A sacrificial layer is formed within the filling area, and the top surface of the sacrificial layer is flush with the preset position of the second segment; Remove a portion of the first gate oxide layer to expose the top surface of the active pillar; A second gate oxide layer is formed, the bottom surface of the second gate oxide layer is connected to the top surface of the sacrificial layer, and the second gate oxide layer is located outside the first gate oxide layer that wraps around a portion of the sidewalls of the second segment and the third segment; After removing the sacrificial layer, the sidewall of the second gate oxide layer forms a second trench with the sidewall of the first gate oxide layer that was originally covered by the sacrificial layer.

9. The method for fabricating a semiconductor structure according to claim 8, characterized in that, The formation of the second gate oxide layer includes: The second gate oxide layer is formed using an atomic layer deposition process.

10. The method for fabricating a semiconductor structure according to claim 8, characterized in that, The multiple word line isolation structures are spaced apart along a third direction.

11. The method for fabricating a semiconductor structure according to claim 10, characterized in that, The formation of a word line isolation structure within the second trench includes: An initial word line is formed in the second groove, and the plurality of the initial word lines are spaced apart along a third direction; Along the first direction, a portion of the initial word line is removed, and the remaining initial word line forms an intermediate word line. A third trench is formed between the intermediate word line and the sidewall of the second gate oxide layer. A third initial dielectric layer is formed within the third trench; Along the first direction, a portion of the third initial dielectric layer and a portion of the intermediate word lines are removed to form a fourth trench spaced along the third direction. The bottom of the fourth trench exposes the top surface of the second dielectric layer. The remaining third initial dielectric layer forms the third dielectric layer, and the remaining intermediate word lines form two word lines. The word line isolation structure is formed within the fourth groove.

12. A semiconductor structure, characterized in that, include: Base; An active column, wherein there are multiple active columns arranged in an array within the substrate, wherein, along a first direction, the active column comprises a first segment, a second segment, and a third segment connected in sequence; A first gate oxide layer is applied to the sidewalls of the second and third segments. A second gate oxide layer is disposed outside the first gate oxide layer. Along the first direction, the length of the second gate oxide layer is less than the length of the first gate oxide layer, and the top surface of the second gate oxide layer is flush with the top surface of the third segment. The thickness of the second gate oxide layer is greater than the thickness of the first gate oxide layer. A word line isolation structure is located between the second gate oxide layer and the first gate oxide layer.

13. The semiconductor structure according to claim 12, characterized in that, The thickness of the second gate oxide layer is 1 to 2 times the thickness of the first gate oxide layer.

14. The semiconductor structure according to claim 12, characterized in that, The semiconductor structure further includes a plurality of bit lines, which are spaced apart along a second direction, and the bit lines are located at the bottom end of the active pillar; The top surface of the bit line is provided with a second dielectric layer.

15. The semiconductor structure according to claim 14, characterized in that, The semiconductor structure also includes a bit line isolation structure; The bit line isolation structure includes a first dielectric layer and a first isolation layer, wherein the first dielectric layer is located between the substrate and the bottom surface of the bit line, and the first isolation layer is located between adjacent bit lines.

16. The semiconductor structure according to claim 12, characterized in that, The semiconductor structure also includes word lines, which are arranged around the second segment of the active pillar. The word lines include a first word line and a second word line. The bottom surface of the first word line is close to the first segment, and the top surface of the second word line is close to the third segment. The longitudinal section is a plane perpendicular to the second direction, and the area of ​​the longitudinal section of the first word line is greater than the area of ​​the longitudinal section of the second word line.

17. The semiconductor structure according to claim 16, characterized in that, The word line isolation structure is located between adjacent word lines, and a third dielectric layer is provided on the top surface of the word line, the top surface of the third dielectric layer being flush with the top surface of the active column.

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