High-speed current sampling circuit based on buck converter

Abstract

This invention discloses a high-speed current sampling circuit based on a buck converter. The high-speed current sampling circuit includes: a bias current generation unit for generating a bias current Ib; a voltage mirror unit including several MOSFETs for generating a voltage signal with equal voltage values ​​at the second node Vsw and the first node Vx based on the bias current Ib; a power transistor Mp for generating a first current Ip during the sampling phase; a sampling transistor Mps for generating a second current Ips during the sampling phase; a source follower unit including a first transistor Ms1 electrically connected between the first node Vx and a reference potential, a sixth MOSFET M6, and a seventh MOSFET M7 electrically connected between the first node Vx and the reference potential; and a sampling current output unit for outputting the sampling current Io. This invention increases the loop gain of the circuit, improves sampling accuracy, increases the non-dominant pole, improves the circuit bandwidth, and enhances the response speed.

Description

Technical Field

[0001] The present invention belongs to the technical field of buck converters, and in particular relates to a high-speed current sampling circuit based on a buck converter. Background Art

[0002] With the continuous development of electronic technology, power integrated circuits have gradually become a mature and important branch of electronic products. Among them, switching power supplies have always occupied a dominant position in power products due to their high efficiency, thus deriving different functional topologies and control architectures.

[0003] Compared with the voltage mode control scheme, the current mode control architecture is increasingly favored by designers and the industry due to its fast response capability, cycle-by-cycle inductor current limiting characteristics and other design advantages. Among them, the inductor current sampling module is a crucial part of the current mode control architecture, and its response speed and sampling accuracy directly affect the performance of the entire voltage converter.

[0004] The high-speed current sampling circuit is a low-latency, high-precision, low-power solution, including power tubes, sampling tubes, voltage mirrors, and switch tubes, which can perform high-speed current sampling to obtain sampling signals. The two indicators that affect the performance of the sampling circuit are loop gain and bandwidth. The larger the loop gain, the more accurate the sampling current; at the same time, the higher the bandwidth, the faster the circuit response speed.

[0005] In the high-speed current sampling circuit in the prior art, the low loop gain Ts limits the current sampling accuracy; in addition, there is still room for improvement of the non-main poles in the loop, and the bandwidth after improvement is higher and the circuit response is faster.

[0006] Therefore, in view of the above technical problems, it is necessary to provide a high-speed current sampling circuit based on a buck converter. Summary of the invention

[0007] In view of this, an object of the present invention is to provide a high-speed current sampling circuit based on a buck converter to improve the loop gain and bandwidth of the high-speed current sampling circuit.

[0008] In order to achieve the above purpose, the technical solution provided by an embodiment of the present invention is as follows:

[0009] A high-speed current sampling circuit based on a buck converter, the high-speed current sampling circuit comprising:

[0010] A bias current generating unit, used for generating a bias current Ib;

[0011] A voltage mirror unit, comprising a plurality of MOS tubes, for generating a voltage signal having an equal voltage value at the second node sw and the first node x according to the bias current Ib;

[0012] The power tube Mp is electrically connected to the input voltage V IN and a second node sw of the voltage mirror unit, for generating a first current Ip in a sampling phase;

[0013] The sampling tube Mps is electrically connected to the input voltage V IN and a first node x of the voltage mirror unit, for generating a second current Ips in a sampling phase;

[0014] A source follower unit, comprising a first transistor Ms1 and a sixth MOS transistor M6 electrically connected between the first node x and a reference potential, and a seventh MOS transistor M7 electrically connected between the first node x and the reference potential;

[0015] The sampling current output unit is used to output the sampling current Io.

[0016] In one embodiment, the voltage mirror unit includes a first MOS tube M1, a second MOS tube M2, a third MOS tube M3 and a fourth MOS tube M4, the first MOS tube M1 and the second MOS tube M2 are NMOS tubes, the third MOS tube M3 and the fourth MOS tube M4 are PMOS tubes, wherein:

[0017] The source of the fourth MOS transistor M4 is connected to the first node x, the gate and the drain are short-circuited, the drain is connected to the drain of the second MOS transistor M2, and the source of the second MOS transistor M2 is connected to the reference potential;

[0018] The source of the third MOS tube M3 is connected to the second node sw, the gate is connected to the gate of the fourth MOS tube M4, the drain is connected to the drain of the first MOS tube M1 and the gate of the transistor Ms, the gate of the first MOS tube M1 is connected to the gate of the second MOS tube M2, and the source is connected to the reference potential.

[0019] In one embodiment, the bias current generating unit includes a current source and a fifth MOS transistor M5, and the fifth MOS transistor M5 is an NMOS transistor;

[0020] The first end of the current source is connected to the power supply voltage Vdd, and the second end is connected to the drain of the fifth MOS tube;

[0021] The drain of the fifth MOS tube M5 is connected to the second end of the current source, the gate is short-circuited with the drain, the gate is connected to the gate of the first MOS tube M1 and the gate of the second MOS tube M2, and the source is connected to the reference potential.

[0022] In one embodiment, the first MOS transistor M1 and the fifth MOS transistor M5, the second MOS transistor M2 and the fifth MOS transistor M5 respectively form a current mirror;

[0023] In the voltage mirror unit, the current flowing through the fourth MOS transistor M4 and the second MOS transistor M2, and the current flowing through the third MOS transistor M3 and the first MOS transistor M1 are all bias currents Ib.

[0024] In one embodiment, the power tube Mp is a PMOS tube, and the source is connected to the input voltage V IN connected, the drain is connected to the second node sw, and the gate is connected to the reference potential;

[0025] The sampling tube Mps is a PMOS tube, and its source is connected to the input voltage V IN connected, the drain is connected to the first node x, and the gate is connected to the reference potential.

[0026] In one embodiment, the first transistor Ms1 in the source follower unit is a PMOS transistor, and the sixth MOS transistor M6 and the seventh MOS transistor M7 are NMOS transistors;

[0027] The source of the first transistor Ms1 is connected to the first node x, the gate is connected to the drain of the third MOS transistor M3 and the drain of the first MOS transistor M1, and the drain is connected to the drain of the sixth MOS transistor M6;

[0028] The gate and drain of the sixth MOS tube M6 are short-circuited, and the source is connected to the reference potential;

[0029] The drain of the seventh MOS transistor M7 is connected to the first node x, the gate is connected to the gate of the sixth MOS transistor M6, and the source is connected to the reference potential.

[0030] In one embodiment, the sampling current output unit includes an eighth MOS tube M8, and the eighth MOS tube M8 is an NMOS tube;

[0031] The gate of the eighth MOS tube M8 is connected to the gate of the sixth MOS tube M6 and the gate of the seventh MOS tube M7 , the source is connected to the reference potential, and the drain is used to output the sampling current Io.

[0032] In one embodiment, the gate of the first transistor Ms1 is connected to the third node i, and the gain from the third node i to the first node x is:

[0033]

[0034] The pole size of the first node x is:

[0035]

[0036] Among them, g msis the transconductance of the first transistor Ms1 when the current is Ips-Ib, Rx is the equivalent on-resistance of the sampling tube Mps, n is the size ratio of the seventh MOS tube M7 to the sixth MOS tube M6, and Cx is the size of all capacitors at the first node x.

[0037] In one embodiment, the sampling current output unit includes a second transistor Ms2 and a sampling resistor Rs, the second transistor Ms2 is a PMOS transistor, and the first transistor Ms1 and the second transistor Ms2 have the same size;

[0038] The source of the second transistor Ms2 is connected to the first node x, the gate is connected to the drain of the third MOS transistor M3 and the drain of the first MOS transistor M1, the drain is connected to the first end of the sampling resistor Rs, and the second end of the sampling resistor Rs is connected to the reference potential;

[0039] The sampling resistor Rs is used to generate a sampling voltage Vs according to the sampling current Io, and the sampling voltage Vs=Io*Rs.

[0040] In one embodiment, the gate of the first transistor Ms1 is connected to the third node i, and the gain from the third node i to the first node x is:

[0041]

[0042] The pole size of the first node x is:

[0043]

[0044] Among them, g ms is the transconductance of the first transistor Ms1 when the current is Ips-Ib and the transconductance of the second transistor Ms2 when the current is Ips-Ib, Rx is the equivalent on-resistance of the sampling tube Mps, n is the size ratio of the seventh MOS tube M7 to the sixth MOS tube M6, and Cx is the size of all capacitors at the first node x.

[0045] The present invention has the following beneficial effects:

[0046] The present invention can improve the equivalent transconductance of the source follower unit, thereby improving the gain from the third node i to the first node x, increasing the loop gain of the overall circuit, and improving the accuracy of current sampling;

[0047] The present invention can reduce the equivalent resistance of the first node x, thereby increasing the pole amplitude of the first node x, increasing the bandwidth of the overall circuit, and improving the response speed of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0049] Figure 1 A circuit diagram of a medium- and high-speed current sampling circuit according to the present invention;

[0050] Figure 2 is a circuit diagram of a high-speed current sampling circuit in a first embodiment of the present invention;

[0051] Figure 3 FIG. 4 is a circuit diagram of a high-speed current sampling circuit in a second embodiment of the present invention. DETAILED DESCRIPTION

[0052] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0053] Ginseng Figure 1 The circuit diagram of a high-speed current sampling circuit based on a buck converter in a ratio of the present invention is shown, which includes:

[0054] A bias current generating unit, including a current mirror and a fifth MOS tube M5, for generating a bias current Ib;

[0055] A voltage mirror unit, comprising a first MOS tube M1, a second MOS tube M2, a third MOS tube M3 and a fourth MOS tube M4, for generating a voltage signal having an equal voltage value at the second node sw and the first node x according to the bias current Ib;

[0056] The power tube Mp is electrically connected to the input voltage V IN and a second node sw of the voltage mirror unit, for generating a first current Ip in a sampling phase;

[0057] The sampling tube Mps is electrically connected to the input voltage V IN and a first node x of the voltage mirror unit, for generating a second current Ips in a sampling phase;

[0058] A source follower unit, comprising a transistor Ms electrically connected to the first node x;

[0059] The sampling current output unit includes a sampling resistor Rs electrically connected between the transistor Ms and a reference potential, and is used for outputting a sampling voltage Vs according to the sampling current Is, where Vs=Is*Rs.

[0060] The reference potential in each example of the present invention is described by taking the ground potential (GND) as an example, and may be other potentials in other examples.

[0061] The second node sw is connected to the SW node in the buck converter, the first current Ip is approximately equal to the inductor current IL in the buck converter, and assuming that the size ratio of the sampling tube Mps to the power tube Mp is 1:N, then the final sampling current Is can be obtained as:

[0062]

[0063] The two parameters that affect the performance of the circuit are loop gain and bandwidth. The larger the loop gain, the more accurate the sampling current; at the same time, the higher the bandwidth, the faster the circuit responds.

[0064] The loop is disconnected at the gate of transistor Ms (a breakpoint is set between the third node i and the fourth node Vf), and the loop gain is the gain from the third node i to the fourth node Vf. At the same time, the bandwidth refers to the frequency point where the voltage gain amplitude is "1" on the gain path. The size of the loop gain is:

[0065]

[0066] Wherein, gm3 and gms are the transconductance of the third MOS tube M3 and the transistor Ms respectively, ro1 is the drain-source resistance of the first MOS tube M1, R X and R Y are the equivalent on-resistances of the sampling tube Mps and the power tube Mp respectively. The gain from the third node i to the first node x is:

[0067]

[0068] The main factor affecting the loop bandwidth is the pole on the path. The larger the pole, the higher the bandwidth. The main pole is located at the gate of transistor Ms, and one of the non-main poles is at the first node x. The size of the non-main pole is:

[0069]

[0070] Where Cx is the size of all the capacitances at the first node x. Obviously, the smaller the RC time constant of this node, the larger the pole and the higher the corresponding bandwidth.

[0071] It can be seen that the high-speed current sampling circuit in this comparative example is a current sampling solution with a faster response, but it still has the following shortcomings or room for improvement:

[0072] (1) The low loop gain Ts limits the current sampling accuracy;

[0073] (2) There is still room for improvement in non-dominant poles. After improvement, the bandwidth will be higher and the circuit response will be faster.

[0074] Ginseng Figure 2 The circuit diagram of the high-speed current sampling circuit based on the buck converter in the first embodiment of the present invention is shown. The basic idea is to replace the simple source follower Ms with a super source follower (a combination of Ms, M6 and M7), thereby increasing the gain from the third node i to the first node x and reducing the equivalent resistance of the first node x. The final sampling current Io can be taken from the drain of M8.

[0075] Specifically, the high-speed current sampling circuit in this embodiment includes:

[0076] A bias current generating unit, used for generating a bias current Ib;

[0077] A voltage mirror unit, comprising a plurality of MOS tubes, for generating a voltage signal having an equal voltage value at the second node sw and the first node x according to the bias current Ib;

[0078] The power tube Mp is electrically connected to the input voltage V IN and a second node sw of the voltage mirror unit, for generating a first current Ip in a sampling phase;

[0079] The sampling tube Mps is electrically connected to the input voltage V IN and a first node x of the voltage mirror unit, for generating a second current Ips in a sampling phase;

[0080] A source follower unit, comprising a first transistor Ms1 and a sixth MOS transistor M6 electrically connected between the first node x and a reference potential, and a seventh MOS transistor M7 electrically connected between the first node x and the reference potential;

[0081] The sampling current output unit is used to output the sampling current Io.

[0082] The voltage mirror unit in this embodiment includes a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3 and a fourth MOS transistor M4. The first MOS transistor M1 and the second MOS transistor M2 are NMOS transistors, and the third MOS transistor M3 and the fourth MOS transistor M4 are PMOS transistors, wherein:

[0083] The source of the fourth MOS transistor M4 is connected to the first node x, the gate and the drain are short-circuited, the drain is connected to the drain of the second MOS transistor M2, and the source of the second MOS transistor M2 is connected to the reference potential;

[0084] The source of the third MOS tube M3 is connected to the second node sw, the gate is connected to the gate of the fourth MOS tube M4, the drain is connected to the drain of the first MOS tube M1 and the gate of the transistor Ms, the gate of the first MOS tube M1 is connected to the gate of the second MOS tube M2, and the source is connected to the reference potential.

[0085] The bias current generating unit in this embodiment includes a current source and a fifth MOS transistor M5, and the fifth MOS transistor M5 is an NMOS transistor;

[0086] A first end of the current source is connected to a power supply voltage Vdd, and a second end is connected to a drain of the fifth MOS tube;

[0087] The drain of the fifth MOS tube M5 is connected to the second end of the current source, the gate is short-circuited with the drain, the gate is connected to the gate of the first MOS tube M1 and the gate of the second MOS tube M2, and the source is connected to the reference potential.

[0088] The first MOS tube M1 and the fifth MOS tube M5, the second MOS tube M2 and the fifth MOS tube M5 respectively form current mirrors. The first MOS tube M1 and the second MOS tube M2 can respectively copy the bias current Ib in the fifth MOS tube M5. Therefore, the current flowing through the fourth MOS tube M4 and the second MOS tube M2, and the current flowing through the third MOS tube M3 and the first MOS tube M1 are all bias currents Ib.

[0089] Furthermore, the power tube Mp is a PMOS tube, and the source is connected to the input voltage V IN connected, the drain is connected to the second node sw, and the gate is connected to the reference potential;

[0090] The sampling tube Mps is a PMOS tube, and its source is connected to the input voltage V IN connected, the drain is connected to the first node x, and the gate is connected to the reference potential.

[0091] Specifically, in the source follower unit in this embodiment, the first transistor Ms1 is a PMOS transistor, and the sixth MOS transistor M6 and the seventh MOS transistor M7 are NMOS transistors;

[0092] The source of the first transistor Ms1 is connected to the first node x, the gate is connected to the drain of the third MOS transistor M3 and the drain of the first MOS transistor M1, and the drain is connected to the drain of the sixth MOS transistor M6;

[0093] The gate and drain of the sixth MOS tube M6 are short-circuited, and the source is connected to the reference potential;

[0094] The drain of the seventh MOS transistor M7 is connected to the first node x, the gate is connected to the gate of the sixth MOS transistor M6, and the source is connected to the reference potential.

[0095] The sampling current output unit includes an eighth MOS tube M8, and the eighth MOS tube M8 is an NMOS tube;

[0096] The gate of the eighth MOS tube M8 is connected to the gate of the sixth MOS tube M6 and the gate of the seventh MOS tube M7 , the source is connected to the reference potential, and the drain is used to output the sampling current Io.

[0097] Combination Figure 2 As shown, when the input voltage Vi of the breakpoint increases, I1 decreases, and I2 decreases at the same time through the action of the current mirror. According to KCL (Kirchhoff's Current Law), the circuit satisfies Is=I1+I2. Since I1 and I2 decrease at the same time, the excess current in Is will quickly increase the voltage of the first node x until the circuit reaches a stable state again. On the contrary, if Vi decreases, I1 and I2 increase at the same time, and the increased current quickly reduces the voltage of the first node x, so that the circuit returns to a stable state. If the width-to-length ratio of the first transistor Ms1 is kept unchanged, the gain from the third node i to the first node x (first stage) is:

[0098]

[0099] Among them, g ms is the transconductance of the first transistor Ms1 (ie, the transconductance of the transistor Ms in the comparative example) when the current is Ips-Ib (ie, Is in the comparative example), Rx is the equivalent on-resistance of the sampling tube Mps, and n is the size ratio of the seventh MOS tube M7 to the sixth MOS tube M6.

[0100] Through the function of the super source follower (source follower unit) in this embodiment, the transconductance from the third node i to the first node x is increased to the original times, making the loop gain value closer to "1".

[0101] In order not to increase the capacitance of the first node x too much, the width and length of the sixth MOS tube M6 and the seventh MOS tube M7 can be selected to be relatively small. The drain of the seventh MOS tube M7 is connected in parallel to the first node x, which can intuitively reduce the equivalent resistance of the first node x. After derivation and calculation, the equivalent resistance of the first node x becomes:

[0102]

[0103] Due to the increase in transconductance, the second term in the above equation is reduced to the original times, the overall equivalent resistance is reduced. The corresponding non-main pole (first node x) pole size is:

[0104]

[0105] Wherein, Cx is the size of all capacitances at the first node x.

[0106] Obviously, the pole is enlarged as a whole, so that the bandwidth and speed can be improved.

[0107] Ginseng Figure 3 The circuit diagram of the high-speed current sampling circuit based on the buck converter in the second embodiment of the present invention is shown. Although the high-speed current sampling circuit in the first embodiment has a certain improvement on the loop gain and bandwidth of the circuit, the final sampling current still needs to be processed by the current mirror before it can generate a sampling voltage at both ends of the resistor connected to the reference potential. On the one hand, this will increase power consumption, and on the other hand, the signal passes through the current mirror, and the response speed of the final sampling voltage will be affected. Therefore, this circuit will have a greater advantage in circuit applications where the sampling current needs to be processed to generate a voltage signal. In view of the above disadvantages, this embodiment is based on the same principle. On the one hand, it can simultaneously improve the loop gain and bandwidth, and on the other hand, the sampling current can be directly generated through the output resistor to generate a voltage signal.

[0108] Specifically, the configuration of the bias current generating unit, the voltage mirror unit, the power tube Mp, the sampling tube Mps, and the source follower unit in this embodiment is exactly the same as that in the first embodiment, and will not be repeated here.

[0109] Different from the first embodiment, the sampling current output unit in this embodiment includes a second transistor Ms2 and a sampling resistor Rs, the second transistor Ms2 is a PMOS transistor, and the sizes of the first transistor Ms1 and the second transistor Ms2 are equal;

[0110] The source of the second transistor Ms2 is connected to the first node x, the gate is connected to the drain of the third MOS transistor M3 and the drain of the first MOS transistor M1, the drain is connected to the first end of the sampling resistor Rs, and the second end of the sampling resistor Rs is connected to the reference potential;

[0111] The sampling resistor Rs is used to generate a sampling voltage Vs according to the sampling current Io, and the sampling voltage Vs=Io*Rs.

[0112] In this embodiment, the first transistor Ms1 and the second transistor Ms2 have the same size, so since the two transistors have the same gate-source voltage, the currents I1 and Io are equal. The sampling current Io can directly generate the sampling voltage Vs at the sampling resistor Rs. In order to keep the total capacitance of the first node x almost unchanged, the width W of the first transistor Ms1 and the second transistor Ms2 can be reduced to 1 / 2 of that in the first embodiment.

[0113] After calculation, the gain from the third node i to the first node x (first stage) in this embodiment is:

[0114]

[0115] Among them, g ms is the transconductance of the first transistor Ms1 when the current is Ips-Ib (i.e., Is in the comparative example) and the transconductance of the second transistor Ms2 when the current is Ips-Ib (i.e., Is in the comparative example) (i.e., the transconductance of the transistor Ms in the comparative example), Rx is the equivalent on-resistance of the sampling tube Mps, and n is the size ratio of the seventh MOS tube M7 to the sixth MOS tube M6.

[0116] The pole size of the first node x is:

[0117]

[0118] Wherein, Cx is the size of all capacitances at the first node x.

[0119] It can be seen that the loop gain and bandwidth in this embodiment are improved to a certain extent. Compared with the first embodiment, the effect of the amplification factor n of the current mirror (M6 and M7) in this embodiment is weakened.

[0120] In addition, in this embodiment, the sampling voltage Vs can be directly generated on the sampling resistor Rs, which can reduce current consumption and bandwidth loss.

[0121] It can be seen from the above technical solutions that the present invention has the following advantages:

[0122] The present invention can improve the equivalent transconductance of the source follower unit, thereby improving the gain from the third node i to the first node x, increasing the loop gain of the overall circuit, and improving the accuracy of current sampling;

[0123] The present invention can reduce the equivalent resistance of the first node x, thereby increasing the pole amplitude of the first node x, increasing the bandwidth of the overall circuit, and improving the response speed of the circuit.

[0124] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

[0125] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

Claims

1. A high-speed current sampling circuit based on a buck converter, characterized in that: The high-speed current sampling circuit comprises: A bias current generating unit, used for generating a bias current Ib; A voltage mirror unit, comprising a plurality of MOS tubes, for generating a voltage signal having an equal voltage value at the second node sw and the first node x according to the bias current Ib; The power tube Mp is electrically connected to the input voltage V IN and a second node sw of the voltage mirror unit, for generating a first current Ip in a sampling phase; The sampling tube Mps is electrically connected to the input voltage V IN and a first node x of the voltage mirror unit, for generating a second current Ips in a sampling phase; A source follower unit, comprising a first transistor Ms1 and a sixth MOS transistor M6 electrically connected between the first node x and a reference potential, and a seventh MOS transistor M7 electrically connected between the first node x and the reference potential; A sampling current output unit, used for outputting a sampling current Io; The voltage mirror unit includes a first MOS tube M1, a second MOS tube M2, a third MOS tube M3 and a fourth MOS tube M4, the first MOS tube M1 and the second MOS tube M2 are NMOS tubes, the third MOS tube M3 and the fourth MOS tube M4 are PMOS tubes, wherein: The source of the fourth MOS transistor M4 is connected to the first node x, the gate and the drain are short-circuited, the drain is connected to the drain of the second MOS transistor M2, and the source of the second MOS transistor M2 is connected to the reference potential; The source of the third MOS transistor M3 is connected to the second node sw, the gate is connected to the gate of the fourth MOS transistor M4, the drain is connected to the drain of the first MOS transistor M1 and the gate of the first transistor Ms1, the gate of the first MOS transistor M1 is connected to the gate of the second MOS transistor M2, and the source is connected to the reference potential.

2. The high-speed current sampling circuit according to claim 1, characterized in that: The bias current generating unit includes a current source and a fifth MOS tube M5, and the fifth MOS tube M5 is an NMOS tube; The first end of the current source is connected to the power supply voltage Vdd, and the second end is connected to the drain of the fifth MOS tube; The drain of the fifth MOS tube M5 is connected to the second end of the current source, the gate is short-circuited with the drain, the gate is connected to the gate of the first MOS tube M1 and the gate of the second MOS tube M2, and the source is connected to the reference potential.

3. The high-speed current sampling circuit according to claim 2, characterized in that: The first MOS tube M1 and the fifth MOS tube M5, the second MOS tube M2 and the fifth MOS tube M5 respectively form a current mirror; In the voltage mirror unit, the current flowing through the fourth MOS transistor M4 and the second MOS transistor M2, and the current flowing through the third MOS transistor M3 and the first MOS transistor M1 are all bias currents Ib.

4. The high-speed current sampling circuit according to claim 3, characterized in that: The power tube Mp is a PMOS tube, the source of which is connected to the input voltage V IN connected, the drain is connected to the second node sw, and the gate is connected to the reference potential; The sampling tube Mps is a PMOS tube, and its source is connected to the input voltage V IN connected, the drain is connected to the first node x, and the gate is connected to the reference potential.

5. The high-speed current sampling circuit according to claim 1, characterized in that: The first transistor Ms1 in the source follower unit is a PMOS transistor, and the sixth MOS transistor M6 and the seventh MOS transistor M7 are NMOS transistors; The source of the first transistor Ms1 is connected to the first node x, the gate is connected to the drain of the third MOS transistor M3 and the drain of the first MOS transistor M1, and the drain is connected to the drain of the sixth MOS transistor M6; The gate and drain of the sixth MOS tube M6 are short-circuited, and the source is connected to the reference potential; The drain of the seventh MOS transistor M7 is connected to the first node x, the gate is connected to the gate of the sixth MOS transistor M6, and the source is connected to the reference potential.

6. The high-speed current sampling circuit according to claim 5, characterized in that: The sampling current output unit includes an eighth MOS tube M8, and the eighth MOS tube M8 is an NMOS tube; The gate of the eighth MOS tube M8 is connected to the gate of the sixth MOS tube M6 and the gate of the seventh MOS tube M7 , the source is connected to the reference potential, and the drain is used to output the sampling current Io.

7. The high-speed current sampling circuit according to claim 6, characterized in that: The gate of the first transistor Ms1 is connected to the third node i, and the gain from the third node i to the first node x is: The pole size of the first node x is: Among them, g ms is the transconductance of the first transistor Ms1 when the current is Ips-Ib, Rx is the equivalent on-resistance of the sampling tube Mps, n is the size ratio of the seventh MOS tube M7 to the sixth MOS tube M6, Cx is the size of all capacitors at the first node x, Vx is the voltage value of the first node x, and Vi is the voltage value of the third node i.

8. The high-speed current sampling circuit according to claim 5, characterized in that: The sampling current output unit includes a second transistor Ms2 and a sampling resistor Rs, the second transistor Ms2 is a PMOS tube, and the first transistor Ms1 and the second transistor Ms2 have the same size; The source of the second transistor Ms2 is connected to the first node x, the gate is connected to the drain of the third MOS transistor M3 and the drain of the first MOS transistor M1, the drain is connected to the first end of the sampling resistor Rs, and the second end of the sampling resistor Rs is connected to the reference potential; The sampling resistor Rs is used to generate a sampling voltage Vs according to the sampling current Io, and the sampling voltage Vs=Io*Rs.

9. The high-speed current sampling circuit according to claim 8, characterized in that: The gate of the first transistor Ms1 is connected to the third node i, and the gain from the third node i to the first node x is: The pole size of the first node x is: Among them, g ms is the transconductance of the first transistor Ms1 when the current is Ips-Ib and the transconductance of the second transistor Ms2 when the current is Ips-Ib, Rx is the equivalent on-resistance of the sampling tube Mps, n is the size ratio of the seventh MOS tube M7 to the sixth MOS tube M6, Cx is the size of all capacitors at the first node x, Vx is the voltage value of the first node x, and Vi is the voltage value of the third node i.

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