Ternary content addressable memory and its storage unit

Abstract

A three-state content addressable memory and a storage unit thereof are proposed. The three-state content addressable storage unit includes a first transistor and a second transistor. The first transistor has a gate terminal for receiving a selection signal, a first terminal of the first transistor is coupled to a matching line, and a second terminal of the first transistor is coupled to a source line. The second transistor has a gate terminal for receiving a reverse selection signal, a first terminal of the second transistor is coupled to a matching line, and a second terminal of the second transistor is coupled to a source line. The first transistor and the second transistor both have a charge storage structure.

Description

Technical Field

[0001] The present invention belongs to the field of storage technology, and relates to a ternary content addressable memory and a storage unit thereof, and in particular to a ternary content addressable memory in the form of a flash memory and a storage unit thereof. Background Art

[0002] In the prior art, ternary content addressable memory is often configured based on the architecture of static random access memory and is often used in network switches. In this case, the ternary content addressable memory unit requires multiple (16) transistors to construct, consumes a large amount of circuit area, and results in relatively high power consumption. Thus, it is limited to applications with power consumption constraints.

[0003] In some prior art, a resistive memory can be used to construct a three-state content addressable memory. In such an application, the voltage difference of the matching signals in different states is not obvious enough due to the difference between the on and off resistances of the transistors is not large enough, resulting in difficulty in judging the sensing results. This reduces the working efficiency of the three-state content addressable memory. Summary of the invention

[0004] The invention provides a three-state content addressable storage unit and a storage unit thereof, which can improve the high density of the storage unit and reduce the required static power consumption.

[0005] The tri-state content addressable memory cell of the present invention comprises a first transistor and a second transistor. The first transistor has a gate terminal for receiving a selection signal, a first terminal of the first transistor is coupled to a matching line, and a second terminal of the first transistor is coupled to a source line. The second transistor has a gate terminal for receiving a reverse selection signal, a first terminal of the second transistor is coupled to a matching line, and a second terminal of the second transistor is coupled to a source line. The first transistor and the second transistor both have a charge storage structure.

[0006] The three-state content addressable memory of the present invention comprises a plurality of selection lines, a plurality of matching lines and a memory cell array. The memory cell array has a plurality of memory cells, and forms a plurality of memory cell rows and a plurality of memory cell columns. Each memory cell has a first transistor and a second transistor connected in parallel, and both the first transistor and the second transistor have a charge storage structure. The memory cell columns are respectively coupled to the selection lines, and the memory cell rows are respectively coupled to the matching lines.

[0007] Based on the above, the present invention provides a flash memory cell structure to construct a three-state content addressable memory cell. As a result, the structure of the three-state content addressable memory cell is effectively simplified, and a high-density layout can be achieved. In addition, the three-state content addressable memory cell of the embodiment of the present invention can maintain a low current consumption under matching conditions and reduce static power consumption. Under non-matching conditions, it can react quickly and provide a correct matching signal immediately. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 Schematic diagram of a ternary content addressable storage unit according to an embodiment of the present invention.

[0009] Figure 2A A waveform diagram of a match signal of a three-state content addressable memory cell implemented in the present invention.

[0010] Figure 2B Graph showing characteristics of transistors in a ternary content addressable memory cell according to an embodiment of the present invention.

[0011] Figure 3 FIG. 1 is a schematic diagram of an implementation of a ternary content addressable memory cell according to an embodiment of the present invention.

[0012] Figure 4 FIG. 2 is a schematic diagram of another embodiment of a ternary content addressable memory cell according to an embodiment of the present invention.

[0013] Figure 5 For the present invention Figure 4 Characteristic curve diagram of transistors in a ternary content addressable memory cell of an embodiment.

[0014] Fig. 6A as well as Figure 6B They are schematic diagrams of ternary content addressable storage units according to different embodiments of the present invention.

[0015] Figure 7 FIG. 1 is a schematic diagram of a ternary content addressable memory according to an embodiment of the present invention.

[0016] Figure 8 For the present invention Figure 7 A schematic diagram of a search operation of a ternary content addressable memory according to an embodiment.

[0017] Fig. 9 For the present invention Figure 7 A schematic diagram of an erase operation of a ternary content addressable memory according to an embodiment.

[0018]

Explanation of symbols

[0019] 100, 300, 400, 600: ternary content addressable storage cells

[0020] 301, 401, 601: Sense amplifier

[0021] 310, 410, 611: Pre-charge circuit

[0022] 700: Ternary Content Addressable Memory

[0023] 710: Memory Cell Array

[0024] 721~72n: Precharge circuit

[0025] 730: Sense Amplifier

[0026] 740: Buffer

[0027] 750: Source line driver

[0028] 760: Encoder

[0029] EG1: Erase Gate

[0030] G1~G4:Gate

[0031] MC11~MCnm: storage unit

[0032] ML, ML1~MLn: Matching line

[0033] MLS1, MLS2, 201, 202, 510, 520: Curve

[0034] SA_ OUT : Sensing results

[0035] SEL, SEL1~SELm: selection signal

[0036] SELB, SEL1B~SELmB: Reverse selection signal

[0037] SL, SL1~SLn: Source lines

[0038] ST: Start signal

[0039] T1, T2, T3, T41, T42, T61~T64, T11, T12, T21, T22: transistors

[0040] VM: pre-charge voltage

[0041] Vref: reference voltage

[0042] VSH: Search Voltage

[0043] WL1, WL1': word line signal DETAILED DESCRIPTION

[0044] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0045] Please refer to Figure 1 , Figure 1 1 is a schematic diagram of a three-state content addressable memory cell according to an embodiment of the present invention. The three-state content addressable memory cell 100 includes transistors T1 and T2. The transistor T1 has a gate terminal for receiving a selection signal SEL, a first terminal (e.g., a drain terminal) of the transistor T1 is coupled to a matching line ML, and a second terminal (e.g., a source terminal) of the transistor T1 is coupled to a source line SL. In addition, the transistor T2 has a gate terminal for receiving a reverse selection signal SELB, a first terminal (e.g., a drain terminal) of the transistor T2 is coupled to a matching line ML, and a second terminal (e.g., a source terminal) of the transistor T1 is coupled to a source line SL, wherein the transistors T1 and T2 form a parallel state. In this embodiment, both the transistors T1 and T2 have a charge storage structure. The transistors T1 and T2 can form a floating gate flash memory cell, a ferroelectric field-effect transistor memory cell, a charge storage type (SONOS) flash memory cell, or a floating dot flash memory cell.

[0046] When storing data, for the ternary content addressable memory cell 100, when the data to be written is logic 0, logic 0 and 1 can be written to the transistors T2 and T1 respectively; when the data to be written is logic 1, logic 1 and 0 can be written to the transistors T2 and T1 respectively. In addition, if the data to be written to the ternary content addressable memory cell 100 is don't care, logic 1 and 1 can be written to the transistors T2 and T1.

[0047] When performing a data search operation on the tri-state content addressable memory cell 100, a precharge operation may be performed on the match line ML first, and the match signal on the match line ML may be set to a precharge voltage. When searching for logic 0, the reverse selection signal SELB may be set to logic 0, and the selection signal SEL may be set to a search voltage. At this time, if the data stored in the transistors T2 and T1 are logic 0 and 1 respectively (indicating that the tri-state content addressable memory cell 100 stores logic 0), the transistors T1 and T2 are not turned on (both are turned off), and the match signal on the match line ML may maintain the precharge voltage, indicating that the search result is a match.

[0048] In contrast, if the data stored in transistors T2 and T1 are logic 1 and 0 respectively (indicating that the tri-state content addressable memory cell 100 stores logic 1), transistor T1 can be turned on and the match signal on the match line ML is pulled down to a source signal with a relatively low voltage on the source line SL. At this time, the match signal on the match line ML indicates that the search result is mismatch.

[0049] In this embodiment, the search voltage may be between 0.5 V and 1.5 V, and the pre-charge voltage may be between 0.6 V and 1.0 V. Of course, the above voltage ranges may be set according to the actual operating voltage received by the memory cell and the process parameters of the wafer, and there is no fixed limit.

[0050] On the other hand, when searching for logic 1, the reverse selection signal SELB can be set to logic 1, and the selection signal SEL can be set to the search voltage. At this time, if the data stored in the transistors T2 and T1 are logic 1 and 0 respectively (indicating that the tri-state content addressable memory cell 100 stores logic 1), the transistors T1 and T2 are not turned on (both are turned off), and the match signal on the match line ML can maintain the pre-charge voltage, indicating that the search result this time is a match.

[0051] In contrast, if the data stored in transistors T2 and T1 are logic 0 and 1 respectively (indicating that the tri-state content addressable memory cell 100 stores logic 0), transistor T2 can be turned on and the match signal on the match line ML is pulled down to a source signal with a relatively low voltage on the source line SL. At this time, the match signal on the match line ML indicates that the search result is mismatch.

[0052] In addition, if the data stored in transistors T2 and T1 are logic 1 and 1 respectively (indicating that the data stored in the ternary content addressable memory cell 100 is don't care), transistors T1 and T2 will be turned off, and the match signal on the match line ML will maintain the pre-charge voltage, indicating that the search result is a match.

[0053] Incidentally, the operation of writing logic 1 and 0 to transistors T1 and T2 can be completed by performing a program operation or an erase operation on transistors T1 and T2. The program operation can be completed by channel hot electron injection (CHE), source side injection or FN tunneling. The erase operation can be completed by FN tunneling or band-to-band hot hole (BTBHH) injection.

[0054] It is worth mentioning that in the embodiment of the present invention, the ratio of the off resistance to the on resistance of any one of the transistors T1 and T2 is greater than 10. 6 Therefore, when both transistors T1 and T2 are turned off, the matching signal on the matching line ML will not be unstable due to the leakage of transistors T1 and T2. In addition, when one of the transistors T1 and T2 is turned on, the matching signal on the matching line ML can also be quickly pulled down and a correct matching signal can be generated immediately. Figure 2A , Figure 2A The waveform diagram of the matching signal of the tri-state content addressable memory cell implemented in the present invention. When the search result is a match, the matching signal can be curve MLS1 and maintain substantially equal to the pre-charge voltage. Conversely, when the search result is not a match, the matching signal can be curve MLS2 and is quickly pulled down to the source voltage. Here, the source voltage can be a reference ground voltage.

[0055] It is worth noting that by determining whether the voltage value of the matching signal is greater than or less than a preset reference voltage Vref, it is possible to quickly and clearly determine whether the search result is consistent.

[0056] In addition, please refer to Figure 2B , Figure 2B 2 is a characteristic curve diagram of a transistor in a three-state content addressable memory cell according to an embodiment of the present invention. Curve 201 represents a characteristic curve when data 0 is written to the transistor, and curve 202 represents a characteristic curve when data 1 is written to the transistor. If a search voltage VSH of, for example, 1.5 volts is applied to the gate of the transistor, the transistor to which data 0 is written is turned on and can generate a relatively high current ION. The transistor to which data 1 is written is turned off and can generate a relatively low current IOFF, wherein the current ION / IOFF is approximately equal to 10 6 .

[0057] Please refer to the following Figure 3 , Figure 3 FIG. 1 is a schematic diagram of an implementation of a ternary content addressable storage unit according to an embodiment of the present invention. Figure 3 In the embodiment, the three-state content addressable memory cell 300 is coupled to the precharge circuit 310 through the match line ML, and is coupled to the sense amplifier 301. The three-state content addressable memory cell 300 includes transistors T1 and T2 coupled in parallel. The structure and operation of the three-state content addressable memory cell 300 in this embodiment are similar to those of the embodiment of the present invention. Figure 1 The embodiments are the same and will not be described in detail here.

[0058] The pre-charging circuit 310 is constructed by a transistor T3. In this embodiment, the transistor T3 can be a P-type transistor, and according to the start signal ST, it is turned on in the initial time interval of the search action to pull up the match signal on the match line ML to the pre-charging voltage VM. After completing the pre-charging action of the match signal, the transistor T3 can be turned off.

[0059] The sense amplifier 301 is used to compare the match signal on the match line ML with the reference voltage Vref during the search operation to generate a sense result SA_ indicating whether the search operation is a match or a mismatch. OUT When the matching signal on the matching line ML is greater than the reference voltage Vref, the search action is consistent; conversely, when the matching signal on the matching line ML is less than the reference voltage Vref, the search action is inconsistent.

[0060] The sense amplifier 301 can be implemented by using any sense amplifier circuit known to those skilled in the art. The sense amplifier 301 can also be implemented by using a logic inverter, wherein the threshold voltage of the logic inverter can be used as the reference voltage Vref.

[0061] Please refer to the following Figure 4 , Figure 4 FIG. 1 is a schematic diagram of another embodiment of a ternary content addressable storage unit according to an embodiment of the present invention. Figure 4 In the embodiment, the three-state content addressable memory cell 400 is coupled to a precharge circuit 410 and a sense amplifier 401. The three-state content addressable memory cell 400 includes transistors T41 and T42. Both transistors T41 and T42 are dual-gate transistors. The first gate G1 of transistor T41 is a floating gate and receives a selection signal SEL. The second gate G2 of transistor T41 receives a word line signal WL1. The first gate G3 of transistor T42 is a floating gate and receives a reverse selection signal SELB. The second gate G4 of transistor T42 receives a word line signal WL1'. The first gates G1 and G3 have a charge storage structure.

[0062] The drain terminals of the transistors T41 and T42 are both coupled to the matching line ML, and the source terminals of the transistors T41 and T42 are both coupled to the source line SL1 .

[0063] The tri-state content addressable memory cell 400 has an erase gate EG1 for receiving an erase voltage.

[0064] When performing a search operation, the word line signals WL1 and WL1' can be pulled high, and the transistors T41 and T42 can be turned on. By receiving the selection signal SEL and the reverse selection signal SELB, the transistors T41 and T42 can be turned on or off according to the stored logic value, and correspondingly generate a match signal on the match line ML.

[0065] The pre-charging circuit 410 is constructed by the transistor T3. In this embodiment, the transistor T3 is turned on in the initial time interval of the search action according to the start signal ST to pull up the match signal on the match line ML to the pre-charging voltage VM. After completing the pre-charging action of the match signal, the transistor T3 can be turned off.

[0066] The sense amplifier 401 is used to compare the match signal on the match line ML with the reference voltage Vref during the search operation to generate a sense result SA_ indicating whether the search operation is a match or a mismatch. OUT .

[0067] The judgment mechanism of whether the transistors T41 and T42 are turned on or off is as follows: Figure 1 The contents described in the embodiments are similar and will not be repeated here.

[0068] Also, please refer to Figure 5 , Figure 5 For the present invention Figure 4 Characteristic curves of transistors in a three-state content addressable memory cell of an embodiment. Curve 510 represents the characteristic curve when data 0 is written into the transistor, and curve 520 represents the characteristic curve when data 1 is written into the transistor. When a search voltage VSH of, for example, 0.5 volts is applied to the gate of the transistor, the transistor into which data 0 is written is turned on, the transistor into which data 1 is written is turned off, and the current ratio between the two transistors (the turned-on transistor and the turned-off transistor) is approximately equal to 10 6 .

[0069] In this embodiment, the transistor for writing data 0 can be erased by over erasing. Under this condition, the threshold voltage of the transistor for writing data 0 can be lower than 0V, for example, -3V.

[0070] Please refer to the following Fig. 6A as well as Figure 6B , Fig. 6A as well as Figure 6B They are schematic diagrams of ternary content addressable storage units according to different embodiments of the present invention. Fig. 6AIn the embodiment, the three-state content addressable memory cell 600 includes transistors T61 to T64. The three-state content addressable memory cell 600 is coupled to the precharge circuit 611 and the sense amplifier 601 through the match line ML. In the three-state content addressable memory cell 600, the transistors T61 and T62 have a charge storage structure. The transistor T61 and the transistor T63 are coupled in series between the match line ML and the source line SL1, and the transistor T62 and the transistor T64 are coupled in series between the match line ML and the source line SL1. The gates of the transistors T61 and T63 receive the selection signal SEL and the word line signal WL, respectively, and the gates of the transistors T62 and T64 receive the reverse selection signal SELB and the word line signal WL', respectively.

[0071] When the search operation is performed, the transistors T63 and T64 act as switches and are turned on according to the word line signals WL and WL', respectively. At this time, the transistors T61 and T62 can be turned on or off according to the selection signal SEL and the reverse selection signal SLEB received respectively based on the stored data, and when one of the transistors T61 and T62 is turned on, the match signal on the match line ML is pulled down, or, when the transistors T61 and T62 are turned off, the match signal on the match line ML is maintained at the precharge voltage VM. In this way, the sense amplifier 601 can generate a sensing result according to the comparison reference voltage Vref and the match signal on the match line ML.

[0072] The transistors T61 to T64 may be arranged in a direction parallel to the match line ML.

[0073] The judgment mechanism of whether the transistors T61 and T62 are turned on or off is as follows: Figure 1 The contents described in the embodiments are similar and will not be repeated here.

[0074] The pre-charging circuit 611 is constructed by the transistor T3. In this embodiment, the transistor T3 is turned on in the initial time interval of the search action according to the start signal ST to pull up the match signal on the match line ML to the pre-charging voltage VM. After completing the pre-charging action of the match signal, the transistor T3 can be turned off.

[0075] exist Figure 6B In, with Fig. 6A Differently, the transistors T64 and T62 can be arranged in sequence along a direction orthogonal to the match line ML. The transistors T63 and T61 can also be arranged in sequence along a direction orthogonal to the match line ML. Fig. 6A , 6B As can be seen from the illustration, the ternary content addressable storage unit 600 can be laid out in a two-dimensional or three-dimensional manner.

[0076] Please refer to Figure 7 , Figure 7 Schematic diagram of a ternary content addressable memory according to an embodiment of the present invention. The ternary content addressable memory 700 includes a memory cell array 710, precharge circuits 721-72n, a sense amplifier 730, a buffer 740, a source line driver 750, and an encoder 760. The memory cell array 710 includes a plurality of ternary content addressable memory cells MC11-MCnm. The memory cells MC11-MCnm can be divided into n memory cell rows and m memory cell columns. The memory cells MC11-MCnm can be divided into n memory cell rows and m memory cell columns according to Figure 1 , 4 , and 6 are implemented by the ternary content addressable storage cell 100, 400 or 600 in the embodiments of FIG.

[0077] The tri-state content addressable memory 700 has a plurality of source lines SL1-SLn, which are respectively coupled to n memory cell rows in the memory cell array 710. The m memory cell columns in the memory cell array 710 receive selection signals SEL1-SELm through a plurality of selection lines, and receive reverse selection signals SEL1B-SELmB through a plurality of selection lines. The n memory cell rows in the memory cell array 710 are respectively coupled to a plurality of match lines ML1-MLn, and are coupled to the precharge circuits 721-72m and the sense amplifier 730 through the match lines ML1-MLn. The sense amplifier 730 is coupled to the encoder 760. The encoder 760 is used to encode the sensing result generated by the sense amplifier 730 and generate a matching result.

[0078] The source line driver 750 is coupled to the source lines SL1-SLn. The source line driver 750 is used to generate a plurality of source driving signals. The buffer 740 is coupled to a plurality of selection lines in the memory cell array 710, and provides a plurality of write data or a plurality of selection signals SEL1-SELm and reverse selection signals SEL1B-SELmB to m memory cell columns in the memory cell array 710 respectively.

[0079] For details on performing a search, see Figure 8 . Figure 8 For the present invention Figure 7 Schematic diagram of the search action of the ternary content addressable memory of the embodiment. In the initial state, an erase action can be performed on all memory cells MC11-MCnm. Then, a programming action is performed on the memory cells MC11-MCnm, and for example, data of logic 0, 1, 1 are written into the memory cells MC11, MC12, MC1m respectively; data of logic 1, 0, 0 are written into the memory cells MC21, MC22, MC2m respectively; and data of logic 0, 1, 0 are written into the memory cells MCn1, MCn2, MCnm respectively.

[0080] During the search operation, the precharge circuits 721-72n can precharge the match lines ML1-MLn in advance. For example, the memory cell array 710 is searched according to the data of logic 1, 0, 0. The selection signals SEL1, SEL2, and SELm can be logic 1, 0, 0 respectively, and the reverse selection signals SEL1B, SEL2B, and SELmB can be logic 0, 1, 1 respectively. Among them, the match signal on the match line ML1 will be pulled down by the memory cell MC1m that generates the conduction path, and a match signal indicating non-compliance will be generated. The transistors of the memory cells MC21, MC22, and MC2m coupled to the match line ML2 are all kept off, and the match signal on the match line ML2 can be maintained as a match signal indicating compliance (substantially equal to the precharge voltage). The match line MLn will be pulled down by the memory cells MCn1 and MCn2 that generate the conduction path, and a match signal indicating non-compliance will be generated.

[0081] It is particularly worth mentioning that when the data stored in the memory cell is a don't care, the search operation can still operate normally. For example, when the data stored in the memory cell MCn2 is changed to a don't care, when searching for data of logic 0, 1, 0, the match signal on the match line MLn can be maintained as a match signal indicating a match (substantially equal to the pre-charge voltage).

[0082] Please refer to the following Fig. 9 , Fig. 9 For the present invention Figure 7Schematic diagram of the erasing action of the three-state content addressable memory of the embodiment. In the embodiment of the present invention, all the memory cells in the memory cell array 710 can be erased to a state with a low threshold voltage by FN tunneling. That is, the erased memory cell is equivalent to storing data of logic 0. In addition, the embodiment of the present invention can also perform an erasing action on a specific memory cell. For example, the memory cell MC11 originally stores data of don't care (both transistors T11 and T12 store logic 1), and the memory cell MC22 originally stores data of logic 1 (the two transistors T21 and T22 store logic 1 and 0 respectively). By band-to-band hot hole (BTBHH) injection, the erasing action can be performed one by one on the memory cell MC11 and the memory cell MC22. Among them, by providing a reverse selection signal SEL1B of, for example, -3V to -10V, a selection signal SEL1 of 0 volts, and a source signal SL1 of, for example, 3V to 10V, the data in the transistor T11 can be erased to logic 0. By providing a selection signal SEL1 of, for example, -3V to -10V, a reverse selection signal SEL1B of 0V, and a source signal SL1 of, for example, 3V to 10V, the data in the transistor T12 can be erased to logic 0. For the memory cell MC22, a reverse selection signal SEL2B of, for example, -3V to -10V, a selection signal SEL2 of 0V, and a source signal SL2 of, for example, 3V to 10V can be provided, and the data in the transistor T21 can be erased to logic 0.

[0083] According to the above description, in the embodiment of the present invention, the architecture of the memory cell array 710 can enable transistors in a plurality of memory cells therein to perform erasing operations one by one, thereby effectively improving the access performance of the ternary content addressable memory.

[0084] In summary, the present invention forms a three-state content addressable storage unit by using two transistors with a charge storage structure. It effectively reduces the leakage that may be generated on the match line and stabilizes the match signal indicating compliance. The present invention can also accelerate the speed of lowering the match signal indicating non-compliance. In this way, the stability of the match result determined by the three-state content addressable storage unit can be improved.

[0085] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A ternary content addressable storage unit, characterized in that: include: A first transistor having a gate terminal receiving a selection signal, a first terminal of the first transistor coupled to a matching line, and a second terminal of the first transistor coupled to a source line; as well as a second transistor having a gate terminal receiving a reverse selection signal, a first terminal of the second transistor coupled to the matching line, and a second terminal of the second transistor coupled to the source line, Wherein, the first transistor and the second transistor both have a charge storage structure; The first transistor and the second transistor are floating gate transistors, and the tri-state content addressable memory cell further comprises: a first switch connected in series with the first transistor between the matching line and the source line and controlled by a first word line signal; and A second switch is connected in series with the second transistor between the matching line and the source line and is controlled by a second word line signal.

2. The three-state content addressable memory cell according to claim 1, wherein the ratio of the off resistance to the on resistance of any one of the first transistor and the second transistor is greater than 10 6 .

3. The three-state content addressable memory cell according to claim 1, wherein the first transistor is a dual-gate transistor, a first gate of the first transistor is a floating gate and receives the selection signal, a second gate of the first transistor receives the first word line signal, the second transistor is a dual-gate transistor, a first gate of the second transistor is a floating gate and receives the reverse selection signal, and a second gate of the second transistor receives the second word line signal.

4. A ternary content addressable memory, characterized in that: include: Multiple selection lines; Multiple matching lines; as well as A memory cell array has a plurality of memory cells, forming a plurality of memory cell rows and a plurality of memory cell columns, wherein each of the memory cells has a first transistor and a second transistor connected in parallel, and the first transistor and the second transistor both have a charge storage structure, The memory cell columns are respectively coupled to the selection lines, and the memory cell rows are respectively coupled to the matching lines; Each of the storage units further comprises: a first switch connected in series with the first transistor between the corresponding matching line and the corresponding source line, and controlled by a first word line signal; as well as a second switch connected in series with the second transistor between the corresponding matching line and the corresponding source line, and controlled by a second word line signal; The first transistor and the second transistor are floating gate transistors.

5. The ternary content addressable memory according to claim 4, wherein the ratio of the off resistance to the on resistance of any one of the first transistor and the second transistor is greater than 10 6 .

6. A three-state content addressable memory according to claim 4, wherein the first transistor is a dual-gate transistor, a first gate of the first transistor is a floating gate and receives a selection signal, a second gate of the first transistor receives the first word line signal, the second transistor is a dual-gate transistor, a first gate of the second transistor is a floating gate and receives a reverse selection signal, and a second gate of the second transistor receives the second word line signal.

7. The ternary content addressable memory according to claim 4, further comprising: A plurality of pre-charging circuits are respectively coupled to the matching lines for performing pre-charging operations on a plurality of matching signals on the matching lines.

8. The ternary content addressable memory according to claim 4, further comprising: a sense amplifier coupled to the match lines, sensing the match signals to generate a plurality of sensing results respectively; a source driver coupled to the source lines to generate a plurality of source driving signals; a buffer coupled to the selection lines to provide a plurality of write data or a plurality of selection signals to the memory cell columns; as well as An encoder, coupled to the sense amplifier, encodes the sensing results to generate a matching result.

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