A dynamic index measurement system and method of ADC chip based on FPGA

Abstract

The present invention discloses an ADC dynamic index measurement system and method based on FPGA, which is used to solve the problems of frequent manual intervention and slow test speed in traditional methods. The system only needs simple operation during measurement to realize the measurement and display of ADC dynamic index, which can effectively shorten the measurement time. The measurement system includes a host computer, a software module and a hardware logic module. The host computer is used to measure the distribution of system control parameters and the dynamic observation of parameter indicators; the software module is implemented based on Microblaze soft core or ARM hard core, including an ADC chip configuration module and an ADC index calculation module; the hardware logic module is implemented using the logic resources of FPGA, including a clock distribution module, an IO transmission module, a data buffer conversion module, a self-test signal generation module, a data preprocessing module and a RAM storage control module.

Description

Technical Field

[0001] The present invention relates to the technical field of radar signal analysis and testing, and in particular to a dynamic index measurement system and method of an ADC chip based on FPGA. Background Art

[0002] Currently, in the field of radar signal acquisition systems, radar signal acquisition systems mainly use ADC combined with FPGA system architecture to collect and preprocess radar signals. In the process of acquisition system development and testing, it is often necessary to measure and analyze the dynamic indicators of ADC. The traditional method is that engineers use FPGA to develop debugging software to capture the data collected by ADC online, perform preliminary processing on the data, and then import it into MATLAB to perform indicator analysis using MATLAB. The test process is as follows: Figure 1 shown.

[0003] The main problem with this method is that the testing speed is slow. When multiple sets of data need to be tested, testers are required to operate frequently, which is extremely time-consuming and energy-consuming, and has a high error rate. Summary of the invention

[0004] In view of this, the present invention provides a dynamic index measurement system and method for an ADC chip based on FPGA, which can solve the technical problems of slow test speed, frequent operation by testers and high error rate.

[0005] In order to solve the above technical problems, the present invention is implemented as follows.

[0006] An ADC dynamic index measurement system based on FPGA, the system comprising: the dynamic index measurement system of the ADC chip based on FPGA, including a host computer, a software module and a hardware logic module;

[0007] The host computer is used to issue instruction information and dynamically display the calculated ADC chip indicators; the host computer interacts with the hardware logic module through an external transmission interface;

[0008] The software module receives the processing result data of the hardware logic module and sends the data after the operation is completed to the hardware logic module; the software module is used to configure the ADC chip and calculate the ADC index;

[0009] The hardware logic module receives the control information of the host computer and the operation result of the software module for data forwarding and data preprocessing.

[0010] Preferably, the software module includes an ADC chip configuration module and an ADC chip index calculation module; the ADC chip configuration module is used to set the register configuration parameters of the ADC chip and control the working mode of the ADC chip, and forward the configuration parameters to the ADC chip through the hardware logic module; the ADC chip index calculation module is used to read the preprocessed data stored in the hardware logic module, calculate the index of the ADC chip, and forward the calculation result to the host computer through the hardware logic module.

[0011] Preferably, the indicators of the ADC chip include spurious free dynamic range SFDR, total harmonic distortion YHD, signal-to-noise ratio SINAD, signal-to-noise ratio and effective number of bits.

[0012] Preferably, the software module and the hardware logic module are connected via an AXI bus.

[0013] Preferably, the hardware logic module includes a clock distribution module, an IO transmission module, a data buffer conversion module, a self-test signal generation module, a data preprocessing module and a RAM storage control module;

[0014] The clock distribution module converts the FPGA external clock into an internal clock and distributes the internal clock, and the clock distribution module distributes the internal clock to other modules in the hardware logic module;

[0015] The IO transmission module receives the instruction information sent by the host computer and the operation result sent by the software module, and transmits the calculated ADC chip index data to the host computer;

[0016] The data buffer conversion module uses the IBUFDS differential signal buffer and the IDDR single-ended dual-edge converter to convert the original signal output by the ADC chip, synchronizes it with the internal sampling clock, and outputs the synchronized ADC signal;

[0017] The self-test signal generating module is used to generate a self-test signal, which is used to perform a self-test on the dynamic index measurement system and calibrate the output ADC index of the dynamic index measurement system;

[0018] The data preprocessing module is used to receive the signal from the data buffer conversion module or the self-test signal generation module, and preprocess the self-test signal or the raw data collected by the ADC chip according to the mode information set by the IO transmission module, and the preprocessing includes conversion from fixed-point to floating-point and FFT processing;

[0019] The RAM storage control module is used to store the preprocessed data into the RAM, and the ADC chip index calculation module reads the preprocessed data from the RAM to calculate the index of the ADC chip.

[0020] A method for measuring ADC dynamic indicators based on FPGA, the method is based on the system as described above, and the method includes:

[0021] Step S31: The ADC chip converts the collected analog signal into a digital signal and sends it to the FPGA, and then uses the IBUFDS differential signal buffer and the IDDR single-ended dual-edge converter to perform preliminary conversion processing;

[0022] Step S32: the host computer issues a mode control command to select the working mode of the measurement system and obtain raw data; the working mode includes a measurement mode and a self-test mode; in the measurement mode, the raw data comes from the ADC chip, and in the self-test mode, the raw data comes from the data generated by the self-test module;

[0023] Step S33: processing the selected original data from fixed-point numbers to floating-point numbers;

[0024] Step S34: Perform FFT processing on the floating point data;

[0025] Step S35: sending the real and imaginary data after FFT processing to the RAM memory according to the number of FFT points, and then sending an FFT processing completion signal to the software module to notify the software module to read the data stored in the RAM and perform calculations. After the software module completes the index calculation, it sends a calculation completion signal to the RAM storage control module to notify the RAM storage control module to continue storing data in the RAM;

[0026] Step S36: the ADC chip index calculation module performs index calculation according to the ADC index calculation formula;

[0027] Step S37: Send the calculated index data to the host computer through the data interface to realize dynamic display of the index.

[0028] Beneficial effects:

[0029] During the measurement period, the present invention only needs simple operation to realize the measurement and display of ADC dynamic indicators, which can effectively shorten the measurement time and has high measurement precision and accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 A schematic diagram of a measurement method in the prior art;

[0031] Figure 2 It is a schematic diagram of the structure of the ADC dynamic index measurement system based on FPGA of the present invention;

[0032] Figure 3The figure is a flow chart of the ADC dynamic index measurement method based on FPGA of the present invention. DETAILED DESCRIPTION

[0033] The present invention is described in detail below in conjunction with the accompanying drawings and embodiments.

[0034] like Figure 2 As shown, the present invention uses FPGA to construct a dynamic index measurement system for ADC chip, and implements the entire measurement system on FPGA, and the ADC chip is the measured chip.

[0035] The dynamic index measurement system of the ADC chip based on FPGA includes a host computer, a software module and a hardware logic module.

[0036] The host computer is used to issue instruction information and dynamically display the calculated ADC chip indicators; the host computer interacts with the hardware logic module through an external transmission interface.

[0037] The software module receives the processing result data of the hardware logic module and sends the data after the operation is completed to the hardware logic module; the software module is used to configure the ADC chip and operate the ADC indicators.

[0038] The hardware logic module receives the control information of the host computer and the operation result of the software module for data forwarding and data preprocessing.

[0039] In this embodiment, the host computer dynamically displays the calculated ADC chip indicator results, and the software module can be implemented using Microblaze soft core or ARM hard core.

[0040] Furthermore, the command information includes but is not limited to a self-checking command, a start measurement command, and an ADC channel selection command. The host computer is also used to send down measurement system control parameters.

[0041] Furthermore, the software module includes an ADC chip configuration module and an ADC chip index calculation module. The ADC chip configuration module is used to set the register configuration parameters of the ADC chip and control the working mode of the ADC chip, and forward the configuration parameters to the ADC chip through the hardware logic module. The ADC chip index calculation module is used to read the pre-processed data stored in the hardware logic module, calculate the index of the ADC chip, and forward the calculation result to the host computer through the hardware logic module. The indicators of the ADC chip include but are not limited to spurious free dynamic range SFDR, total harmonic distortion YHD, signal-to-noise ratio SINAD, signal-to-noise ratio and effective number of bits.

[0042] The software module is connected to the hardware logic module via an AXI bus.

[0043] Furthermore, the hardware logic module includes a clock distribution module, an IO transmission module, a data buffer conversion module, a self-test signal generation module, a data preprocessing module and a RAM storage control module. The hardware logic module is implemented based on the hardware logic resources of the FPGA.

[0044] The clock distribution module converts the FPGA external clock into an internal clock and distributes the internal clock. The clock distribution module distributes the internal clock to other modules in the hardware logic module.

[0045] The IO transmission module receives the instruction information sent by the host computer and the operation result sent by the software module, and transmits the calculated ADC chip index data to the host computer.

[0046] The data buffer conversion module converts the original signal output by the ADC chip using the IBUFDS differential signal buffer and the IDDR single-ended dual-edge converter, synchronizes with the internal sampling clock, and outputs the synchronized ADC signal.

[0047] The self-check signal generating module is used to generate a self-check signal for performing a self-check on the dynamic index measurement system and calibrating an output ADC index of the dynamic index measurement system.

[0048] The data preprocessing module is used to receive the signal from the data buffer conversion module or the self-test signal generation module, and preprocess the self-test signal or the raw data collected by the ADC chip according to the mode information set by the IO transmission module, and the preprocessing includes conversion from fixed-point to floating-point and FFT processing.

[0049] The RAM storage control module is used to store the preprocessed data into the RAM, and the ADC chip index calculation module reads the preprocessed data from the RAM to calculate the index of the ADC chip.

[0050] like Figure 3 As shown, the present invention provides an ADC dynamic index measurement method based on FPGA, the method is based on the ADC dynamic index measurement system based on FPGA as described above, and the method includes:

[0051] Step S31: The ADC chip converts the collected analog signal into a digital signal and sends it to the FPGA, and then uses the IBUFDS differential signal buffer and the IDDR single-ended dual-edge converter to perform preliminary conversion processing;

[0052] Step S32: the host computer issues a mode control command to select the working mode of the measurement system and obtain raw data; the working mode includes a measurement mode and a self-test mode; in the measurement mode, the raw data comes from the ADC chip, and in the self-test mode, the raw data comes from the data generated by the self-test module;

[0053] Step S33: processing the selected original data from fixed-point numbers to floating-point numbers;

[0054] Step S34: Perform FFT processing on the floating point data;

[0055] Step S35: sending the real and imaginary data after FFT processing to the RAM memory according to the number of FFT points, and then sending an FFT processing completion signal to the software module to notify the software module to read the data stored in the RAM and perform calculations. After the software module completes the index calculation, it sends a calculation completion signal to the RAM storage control module to notify the RAM storage control module to continue storing data in the RAM;

[0056] Step S36: the ADC chip index calculation module performs index calculation according to the ADC index calculation formula;

[0057] Step S37: Send the calculated index data to the host computer through the data interface to realize dynamic display of the index.

[0058] In this embodiment, the ADC dynamic index measurement method can be used alone to test the ADC index of the acquisition system, and can also be used as a module of the complete acquisition system FPGA program to perform real-time monitoring of the measurement index of the acquisition system.

[0059] By analyzing the measurement results, the measurement error is acceptable compared with the original method. It can be concluded that under the condition of acceptable measurement error, this ADC indicator measurement method can effectively shorten the measurement time.

[0060] Furthermore, the system is a radar signal acquisition system, which uses XC7K325T-2FFG900I FPGA as the main control chip, uses AD9467 as the external acquisition ADC chip, and has a PCIe interface for data transmission.

[0061] The above specific embodiments only describe the design principle of the present invention. The shapes and names of the components in the description may be different and are not limited. Therefore, those skilled in the art in the field of the present invention may modify or replace the technical solutions recorded in the above embodiments; and these modifications and replacements do not deviate from the creative purpose and technical solutions of the present invention and should all fall within the protection scope of the present invention.

Claims

1. A dynamic index measurement system for ADC chip based on FPGA in the field of radar signal, characterized in that: The dynamic index measurement system of the ADC chip based on FPGA includes a host computer, a software module and a hardware logic module; The host computer is used to issue instruction information and dynamically display the calculated ADC chip indicators; the host computer interacts with the hardware logic module through an external transmission interface; The software module receives the processing result data of the hardware logic module, and sends the data after the operation is completed to the hardware logic module; The software module is used to configure the ADC chip and calculate the ADC indicators; The hardware logic module receives the control information of the host computer and the operation result of the software module for data forwarding and data preprocessing; The hardware logic module includes a clock distribution module, an IO transmission module, a data buffer conversion module, a self-test signal generation module, a data preprocessing module and a RAM storage control module; The clock distribution module converts the FPGA external clock into an internal clock and distributes the internal clock, and the clock distribution module distributes the internal clock to other modules in the hardware logic module; The IO transmission module receives the instruction information sent by the host computer and the operation result sent by the software module, and transmits the calculated ADC chip index data to the host computer; The data buffer conversion module uses the IBUFDS differential signal buffer and the IDDR single-ended dual-edge converter to convert the original signal output by the ADC chip, synchronizes it with the internal sampling clock, and outputs the synchronized ADC signal; The self-test signal generating module is used to generate a self-test signal, which is used to perform a self-test on the dynamic index measurement system and calibrate the output ADC index of the dynamic index measurement system; The data preprocessing module is used to receive the signal from the data buffer conversion module or the self-test signal generation module, and preprocess the self-test signal or the raw data collected by the ADC chip according to the mode information set by the IO transmission module, and the preprocessing includes conversion from fixed-point to floating-point and FFT processing; The RAM storage control module is used to store the preprocessed data into the RAM, and the ADC chip index calculation module reads the preprocessed data from the RAM to calculate the index of the ADC chip.

2. The system according to claim 1, characterized in that The software module includes an ADC chip configuration module and an ADC chip index calculation module; the ADC chip configuration module is used to set the register configuration parameters of the ADC chip and control the working mode of the ADC chip, and forward the configuration parameters to the ADC chip through the hardware logic module; the ADC chip index calculation module is used to read the pre-processed data stored in the hardware logic module, calculate the index of the ADC chip, and forward the calculation result to the host computer through the hardware logic module.

3. The system according to claim 2, characterized in that The indicators of the ADC chip include spurious free dynamic range SFDR, total harmonic distortion YHD, signal-to-noise ratio SINAD, signal-to-noise ratio and effective number of bits.

4. The system according to claim 3, characterized in that The software module is connected to the hardware logic module via an AXI bus.

5. A method for measuring ADC dynamic indicators based on FPGA, the method being based on the system as claimed in any one of claims 1 to 4, the method comprising: Step S31: The ADC chip converts the collected analog signal into a digital signal and sends it to the FPGA, and then uses the IBUFDS differential signal buffer and the IDDR single-ended dual-edge converter to perform preliminary conversion processing; Step S32: the host computer issues a mode control command to select the working mode of the measurement system and obtain raw data; the working mode includes a measurement mode and a self-test mode; in the measurement mode, the raw data comes from the ADC chip, and in the self-test mode, the raw data comes from the data generated by the self-test module; Step S33: processing the selected original data from fixed-point numbers to floating-point numbers; Step S34: Perform FFT processing on the floating point data; Step S35: sending the real and imaginary data after FFT processing to the RAM memory according to the number of FFT points, and then sending an FFT processing completion signal to the software module to notify the software module to read the data stored in the RAM and perform calculations. After the software module completes the index calculation, it sends a calculation completion signal to the RAM storage control module to notify the RAM storage control module to continue storing data in the RAM; Step S36: the ADC chip index calculation module performs index calculation according to the ADC index calculation formula; Step S37: Send the calculated index data to the host computer through the data interface to realize dynamic display of the index.

Images