A selective emitter based on tunneling oxide layer passivation contact structure and its preparation method and application

Abstract

The present invention relates to a selective emitter based on a tunneling oxide layer passivation contact structure and a preparation method and application thereof, comprising: a low square resistance electrode region and a high square resistance non-electrode region, wherein the low square resistance electrode region comprises: a crystalline silicon substrate; a TOPCon structure layer, which is arranged on the crystalline silicon substrate, wherein the TOPCon structure layer comprises a tunneling ultra-thin oxide layer and a heavily doped amorphous silicon layer arranged on the tunneling ultra-thin oxide layer; and a metal electrode layer, which is arranged on the heavily doped amorphous silicon layer; the high square resistance non-electrode region comprises: a crystalline silicon substrate; a passivation layer, which is arranged on the crystalline silicon substrate; and an anti-reflection layer, which is arranged on the passivation layer; and a tunneling ultra-thin oxide layer, which is arranged on the anti-reflection layer. The selective emitter of the present invention can not only provide a conventional selective emitter function, but also avoid laser ablation damage to reduce efficiency, and can passivate the contact, reduce the recombination current, and maximize the battery efficiency from many aspects.

Description

Technical Field

[0001] The present invention relates to the technical field of solar cells, and in particular to a selective emitter structure based on tunneling oxide layer passivation contact, a preparation method thereof and an application in solar cells. Background Art

[0002] With the further development of the photovoltaic industry, the Passivated Emitter and Rear Contact (PERC) cells and Tunnel Oxide Passivated Contact (TOPCon) cells in the market together account for more than 91%, and further improving cell efficiency is an eternal topic. Preparing a selective emitter (SE) on the front side is one of the effective methods to improve cell efficiency. The selective doping of solar cells achieves light doping in the non-electrode area and heavy doping in the electrode area. This structure can not only form a good ohmic contact, reduce the series resistance of the cell, improve the fill factor and short-wave response of the cell, but also reduce the recombination of photogenerated minority carriers on the cell surface and increase the open circuit voltage of the cell. The lower surface impurity concentration in the non-electrode area can further reduce the surface state density of the cell, achieve a better surface passivation effect, and further reduce the surface recombination of photogenerated minority carriers.

[0003] The selective emitter (SE) doping process is usually carried out after the single crystal silicon diffusion and bonding process is completed. Since the laser has a short action time on the silicon surface and high energy, it can effectively achieve heavy doping of the battery gate area without causing secondary distribution of impurities in other areas of the battery. In order to better utilize the laser energy and reduce the impact on other areas, the laser selective doping process usually uses expensive nanosecond pulse lasers as the laser source, scanning on the phosphorus silicon glass (PSG) layer formed after the battery diffusion, and driving the impurities in the PSG layer into the silicon wafer. Usually, the laser selective doping process can increase the photoelectric conversion efficiency of solar cells by about 0.3% to 0.4%.

[0004] However, the current SE preparation method has obvious drawbacks. Although the laser selective doping process can effectively improve the photoelectric conversion efficiency of solar cells, the high-energy laser will damage the PSG layer during the process, which is the so-called laser ablation. In the post-process alkali polishing process, the damaged PSG layer has a reduced protective effect on the silicon surface, which causes over-corrosion in the electrode area and reduces the photoelectric conversion efficiency of the battery. In order to avoid over-corrosion in the gate area due to damage to the PSG layer, the efficient immersion alkali polishing process has to be changed to a chain alkali polishing process, which reduces production efficiency and increases the manufacturing cost of solar cells.

[0005] In addition, the front structure of conventional PERC and TOPCon solar cells is the same, and the front metal electrode is in direct contact with the silicon substrate, resulting in a high recombination area. 0,met More than 1500fA / cm 2 , which seriously affects the battery efficiency, so it is also necessary to reduce the positive recombination of the battery.

[0006] In view of this, it is necessary to study a new solar cell SE structure and process that is highly compatible with the existing industry, passivating the front contact while forming SE, thereby improving the photoelectric conversion efficiency of solar cells and reducing the difficulty and cost of cell production. Summary of the invention

[0007] The purpose of the present invention is to propose a selective emitter based on a tunneling oxide layer passivation contact structure that can avoid laser ablation damage and reduce efficiency, and can passivate the contact, reduce the recombination current, and improve the battery efficiency from multiple aspects.

[0008] The solution adopted by the present invention to solve the above technical problem is: a selective emitter based on a tunneling oxide layer passivation contact structure, comprising:

[0009] A low square resistance electrode region and a high square resistance non-electrode region, wherein the low square resistance electrode region includes:

[0010] Crystalline silicon substrate;

[0011] A TOPCon structure layer is disposed on a crystalline silicon substrate, wherein the TOPCon structure layer includes a tunneling ultra-thin oxide layer and a heavily doped amorphous silicon layer disposed on the tunneling ultra-thin oxide layer; and

[0012] A metal electrode layer, which is disposed on the heavily doped amorphous silicon layer;

[0013] High square resistance non-electrode areas include:

[0014] Crystalline silicon substrate;

[0015] a passivation layer disposed on the crystalline silicon substrate; and

[0016] an anti-reflection layer disposed on the passivation layer; and

[0017] Tunneling through an ultra-thin oxide layer disposed on the anti-reflection layer.

[0018] In the above-mentioned selective emitter based on tunneling oxide passivation contact structure, preferably, the thickness of the tunneling ultra-thin oxide layer is 1nm-2nm, the thickness of the heavily doped amorphous silicon layer is 20nm-200nm, the thickness of the passivation layer is 10nm-40nm, and the thickness of the anti-reflection layer is 50nm-200nm.

[0019] Further preferably, the thickness of the heavily doped amorphous silicon layer is smaller than the thickness of the anti-reflection layer.

[0020] Further preferably, the tunneling ultra-thin oxide layer includes an ultra-thin silicon dielectric film, and the ultra-thin silicon dielectric film includes but is not limited to a silicon oxide layer.

[0021] In the selective emitter based on the tunneling oxide layer passivation contact structure, preferably, the doping element in the heavily doped amorphous silicon layer is boron or phosphorus, and the doping concentration of boron is in the range of 1E17-5E20cm -3 , the phosphorus doping concentration range is 1E18-1E21cm -3 .

[0022] In the above selective emitter based on tunneling oxide layer passivation contact structure, preferably, the passivation layer includes one or both of an aluminum oxide layer and a gallium oxide layer.

[0023] In the above selective emitter based on tunneling oxide layer passivation contact structure, preferably, the anti-reflection layer includes one or both of a silicon nitride layer and a magnesium fluoride layer.

[0024] In the above selective emitter based on tunneling oxide layer passivation contact structure, preferably, the crystalline silicon substrate is a p-type crystalline silicon substrate or an n-type crystalline silicon substrate with boron diffusion.

[0025] Another object of the present invention is to provide a method for preparing the selective emitter based on the tunneling oxide layer passivation contact structure, comprising the following steps:

[0026] (1) RCA cleaning of crystalline silicon substrate;

[0027] (2) depositing a passivation layer and an anti-reflection layer in sequence on the front side of the crystalline silicon substrate;

[0028] (3) Grooving the electrode region of the substrate obtained in step (2) by photolithography to remove the passivation layer and the anti-reflection layer in the electrode region;

[0029] (4) forming a tunneling ultra-thin oxide layer on the surface of the material obtained in step (3) by a weak oxidation method, wherein the ultra-thin silicon dielectric film covers the electrode region and the non-electrode region;

[0030] (5) forming a heavily doped amorphous silicon layer on the surface of the tunneling ultra-thin oxide layer obtained in step (4); the heavily doped amorphous silicon layer and the tunneling ultra-thin oxide layer in step (4) together form a TOPCon structure;

[0031] (6) setting a mask pattern in the electrode region, then etching and removing the heavily doped amorphous silicon layer in the non-electrode region, cleaning after etching, and removing the mask pattern in the electrode region;

[0032] (7) Cleaning the mask and screen-printing a metal electrode in the electrode region, and sintering to obtain the selective emitter based on the tunneling oxide layer passivation contact structure.

[0033] In conventional batteries, sintering is to allow the electrode slurry to form good contact with the silicon wafer. The sintering process in the present invention is to form contact between the electrode slurry and the amorphous silicon in the TOPCon structure, and at the same time, the amorphous silicon crystallizes into polycrystalline silicon under high-temperature sintering. Therefore, after the battery is manufactured, the metal electrode is in contact with the heavily doped polycrystalline silicon, avoiding direct contact between the electrode and the silicon wafer. At the same time, the polycrystalline silicon is removed from the non-metallic electrode area on the front side, increasing the short-circuit current density and avoiding the parasitic light absorption from having a greater impact on the battery efficiency, thereby further improving the battery efficiency.

[0034] In the above preparation method, after RCA cleaning, the crystalline silicon substrate is sequentially deposited with a passivation layer and an anti-reflection layer on the entire surface of the crystalline silicon substrate using atomic layer deposition (ALD) and plasma enhanced chemical vapor deposition (PECVD) to passivate the non-electrode area and reduce front reflection.

[0035] In the above preparation method, step (3) is to make grooves on the front passivation layer and anti-reflection layer stack of the crystalline silicon substrate, and the passivation-anti-reflection layer in the grooves must be completely removed to expose the crystalline silicon substrate at the bottom. The groove making method includes but is not limited to photolithography, laser groove making, or spraying, printing and other methods to form electrode patterns and then etching to form the electrode grooves to be grown.

[0036] In the above preparation method, before preparing the ultra-thin silicon dielectric film in step (4), HF rinsing is used to remove the natural poor quality passivation layer on the surface of the material, and the sample is placed in a TMAH solution to remove the damage caused by the groove.

[0037] In the above preparation method, the weak oxidation method in step (4) includes but is not limited to thermal nitric acid oxidation, rapid thermal oxidation (RTO), ultraviolet ozone (UV / O3), ozone deionized water (DIO3), thermal oxidation, PECVD-N2O, and mixed acid oxidation, aiming to prepare an ultra-thin, low interface defect state density, high-quality tunneling oxide layer, preferably a silicon oxide tunneling layer.

[0038] In the above preparation method, the heavily doped amorphous silicon in step (5) includes but is not limited to being deposited on the surface of the tunneling ultra-thin oxide layer by chemical vapor deposition, and also includes other methods, which only requires decomposing the gas containing silicon elements introduced into the reaction chamber into silicon atoms or silicon atom groups and then depositing them on the surface of the tunneling ultra-thin oxide layer through bias. At this time, the non-electrode area is also deposited with a heavily doped amorphous silicon layer of the same thickness; the boron doping concentration of this structure is higher than the boron doping concentration on the surface of the non-electrode area of ​​crystalline silicon, so a low-square-resistance electrode area and a high-square-resistance non-electrode area with different square resistances will be formed on the surface of the crystalline silicon emitter, that is, a selective emitter structure, that is, the doping concentration on the TOPCon structure is higher than the doping concentration on the surface of the non-electrode area.

[0039] The emitter refers to the front diffusion layer of the battery. Battery efficiency is the product of open circuit voltage (Voc), short circuit current density (Jsc), and fill factor (FF). The open circuit voltage and short circuit current density require a lower doping concentration in the emitter, while the fill factor mainly depends on the contact resistance between the electrode and the emitter, which requires a high doping concentration. However, the entire emitter diffusion concentration of a conventional battery is the same, so the two are contradictory. In order to solve this problem, it is necessary to achieve a high doping concentration (manifested as low square resistance) in the electrode area and a low doping concentration (manifested as high square resistance) in the non-electrode area. According to the needs of different areas of the emitter, selective doping is performed. This emitter is called a selective emitter. The method used in the present invention makes the emitter as a whole have a low doping concentration, and then adds a TOPCon structure with a high doping concentration in the electrode area.

[0040] Preferably, the doping element in the heavily doped amorphous silicon layer is boron or phosphorus, and further, the doping concentration of boron is in the range of 1E17-5E20cm -3 , the phosphorus doping concentration range is 1E18-1E21cm -3 .

[0041] In the above preparation method, in step (6), the mask pattern of the electrode area is slightly wider than the groove to protect the electrode area. The mask pattern of the electrode area is an acid- and alkali-resistant organic material, which can be coated on the amorphous silicon in the electrode area by printing or scraping. Wet etching is performed, and the etching solution is selected according to the properties of the mask, but it is necessary to have obvious selectivity for amorphous silicon and silicon nitride or silicon oxide.

[0042] In the above preparation method, the metal electrode preparation method in step (7) may include but is not limited to screen printing and electroplating. Screen printing is the most commonly used method. The electrode slurry is printed on the battery surface using a screen, and then sintered at high temperature to allow the slurry to contact the emitter and form an alloy layer. The electroplating method first uses a photolithography mask method to prepare the electrode bottom layer (electroplating seed layer), and then increases the electrode thickness by electroplating.

[0043] The selective emitter based on the tunneling oxide layer passivation contact structure can be widely used in the field of solar cells.

[0044] Compared with the prior art, the above method for preparing a selective emitter has the following advantages:

[0045] (1) The TOPCon structure is applied to the front side of the crystalline silicon cell, allowing the metal electrode to contact the heavily doped polysilicon layer, avoiding the existence of a high recombination zone where the metal electrode is in direct contact with the crystalline silicon. At the same time, polysilicon is removed from the non-metallic electrode area on the front side to increase the short-circuit current density and avoid parasitic light absorption from having a significant impact on the cell efficiency, thereby further improving the cell efficiency.

[0046] (2) The present invention forms a low-resistance electrode region and a high-resistance non-electrode region with different square resistances on the surface of the crystalline silicon emitter, namely, a selective emitter structure.

[0047] (3) The method of the present invention is highly compatible with the existing industry. All production processes can be easily implemented on the existing production line. Good contact between the metal and the underlying amorphous silicon can be achieved only through the metallization sintering step. There is no need to introduce additional complex process steps or additional high-temperature crystallization annealing steps. It is sufficient to sinter the metal electrode together with the electrode after printing to form good contact. This avoids the use of traditional laser selective doping processes, avoids serious laser ablation of the SE structure and the resulting efficiency loss, and reduces investment and costs while improving efficiency and achieving provincial-level products. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Figure 1 Schematic diagram of the structure of a crystalline silicon substrate taking an n-type substrate as an example in an embodiment of the present invention;

[0049] Figure 2 It is a schematic diagram of the structure after aluminum oxide / silicon nitride films are sequentially deposited on a crystalline silicon substrate in an embodiment of the present invention;

[0050] Figure 3 Schematic diagram of the structure of the crystalline silicon material after grooves are formed in an embodiment of the present invention;

[0051] Figure 4 This is a schematic diagram of the structure after the tunneling layer is deposited in an embodiment of the present invention;

[0052] Figure 5 It is a schematic diagram of the structure after depositing a heavily doped amorphous silicon layer in an embodiment of the present invention;

[0053] Figure 6 It is a schematic diagram of the structure after printing the mask pattern resistant to alkali solution corrosion in the electrode area in an embodiment of the present invention;

[0054] Figure 7This is a schematic diagram of the structure after etching away the heavily doped amorphous silicon in the non-electrode region in an embodiment of the present invention;

[0055] Figure 8 Schematic diagram of the structure of the battery obtained after removing the mask of the electrode area and preparing the metal electrode in an embodiment of the present invention. DETAILED DESCRIPTION

[0056] For a better understanding of the present invention, the following examples are provided to further illustrate the present invention, but the present invention is not limited to the following examples.

[0057] This embodiment is described by taking an n-type substrate as an example, but this structure is also applicable to a p-type solar cell.

[0058] like Figure 1 As shown, an n-type crystalline silicon substrate having boron diffusion on the front surface is cleaned by RCA standard;

[0059] like Figure 2 As shown, ALD and PECVD are used to sequentially deposit aluminum oxide / silicon nitride films on the front side of the silicon substrate as a passivation layer and an anti-reflection layer for passivating the non-electrode area and reducing the front reflection. The aluminum oxide is used as the passivation layer material for the boron emitter on the front side of the battery.

[0060] like Figure 3 As shown, the electrode area (the area where the electrode is to be prepared) on the front AlOx / SiNx stack is grooved by photolithography to remove the aluminum oxide and silicon nitride in the electrode area, exposing the crystalline silicon substrate at the bottom. The groove method is not limited to photolithography, but can also be laser groove, or spraying, printing and other methods to form an electrode pattern and then etching to form the electrode groove to be grown. After the groove is opened, HF is used for rinsing for tens of seconds to remove the natural poor quality silicon oxide layer on the surface, and the sample is placed in a TMAH solution to remove the damage caused by the groove opening.

[0061] like Figure 4 As shown, a tunneling ultra-thin oxide layer is prepared in the groove and on the surface by a weak oxidation method (such as hydrogen peroxide or ozone oxidation method) in the groove, and the thickness is about 1nm-2nm, which can be an ultra-thin silicon oxide layer. The silicon oxide can be prepared by thermal nitric acid oxidation, rapid thermal oxidation (RTO), ultraviolet ozone (UV / O3), ozone deionized water (DIO3), thermal oxidation, PECVD-N2O, mixed acid oxidation, etc., in order to prepare an ultra-thin, low interface defect state density, high-quality silicon oxide tunneling layer.

[0062] like Figure 5As shown, PECVD is used to prepare boron-heavy doped amorphous silicon on the silicon oxide layer, and a TOPCon structure is formed together with the lower tunneling ultra-thin oxide layer. The boron doping concentration of this structure is higher than the boron doping concentration on the surface of the non-electrode region of crystalline silicon, so a low-square-resistance electrode region and a high-square-resistance non-electrode region with different square resistances will be formed on the surface of the crystalline silicon emitter, that is, a selective emitter structure. The heavily doped amorphous silicon can be deposited using chemical vapor deposition, and the main process is to decompose the gas containing silicon elements introduced into the reaction chamber by certain means and methods, decompose it into silicon atoms or silicon atom groups, and then deposit them on the substrate material through a certain bias voltage.

[0063] like Figure 6 As shown, an alkali-resistant corrosion mask pattern slightly wider than the groove is accurately printed in the electrode area to protect the electrode area. The corrosion-resistant mask is an acid- and alkali-resistant organic substance, etc., which can be covered on the amorphous silicon in the electrode area by printing or scraping. The etching solution is wet-etched according to the properties of the mask, but it must have obvious selectivity for amorphous silicon and silicon nitride or silicon oxide.

[0064] like Figure 7 As shown, the half-cell structure is briefly immersed in an alkaline solution to etch the amorphous silicon in the non-electrode area, and then cleaned after the etching is complete.

[0065] like Figure 8 As shown, after removing the mask of the electrode area, the metal electrode is screen-printed and sintered. The preparation of the metal electrode is generally to prepare the metal grid electrode by screen printing and then form a good contact between the metal electrode and the emitter by sintering; or to open holes by photolithography, and then use an electron beam evaporation coating machine to evaporate Ti / Pd / Ag as a seed layer through exposure and development, and then use an electrochemical workstation electroplating method to thicken the electrode, thereby completing the preparation of the front electrode; the metal electrode can also be prepared by chemical plating.

[0066] Example 1

[0067] The n-type front surface boron-diffused crystalline silicon substrate is polished on the back and first cleaned by standard RCA. Then, 15nm aluminum oxide is deposited by ALD and 70nm silicon nitride is deposited by PECVD to passivate the surface. Then, the electrode area is grooved by photolithography to remove the aluminum oxide in the electrode area and the grooves in the silicon nitride electrode area. After HF treatment to remove the natural oxide layer, TMAH etching is used to remove the damage caused by photolithography. Then, the sample is weakly oxidized by hydrogen peroxide to generate a 1.4nm ultra-thin silicon oxide layer. 30-100nm boron-doped amorphous silicon is deposited by PECVD. The alkali-resistant mask pattern is printed in the electrode area, and the sample is placed in an alkaline solution to selectively etch the amorphous silicon. The mask material is cleaned and removed. Then, the metal electrode is printed in the electrode area by screen printing, and a belt furnace sintering treatment is performed.

[0068] Four samples were made according to the method in Example 1, and the four samples were tested respectively: the overall passivation effect (J 0,total ), passivation effect of electrode contact area containing amorphous silicon selective emitter (J 0,met ) and contact resistivity (ρ c,met ), diffusion resistance of non-metallic contact area (R sq ) and passivation effect (J 0,pass ), and the results are shown in Table 1.

[0069] Comparative Example 1

[0070] The n-type front surface boron diffused crystalline silicon substrate is cleaned by standard RCA, and the surface is passivated by ALD deposition of aluminum oxide and PECVD deposition of silicon nitride; the electrode area is grooved by photolithography, and then the metal electrode is printed in the electrode area by screen printing, and then the belt furnace sintering is carried out.

[0071] Two samples were made according to the method in Comparative Example 1, and the two samples were tested respectively: the overall passivation effect (J 0,total ), passivation effect of electrode contact area (J 0,met ) and contact resistivity (ρ c,met ), diffusion resistance of non-metallic contact area (R sq ) and passivation effect (J 0,pass ), and the results are shown in Table 1.

[0072] Table 1 Comparison of single-sided passivation, contact, and square resistance data of Example 1 and Comparative Example 1

[0073]

[0074] The data of Example 1 and Comparative Example 1 show that the presence of the amorphous silicon selective emitter can significantly reduce the composite current density (J 0,met ), thereby reducing the overall recombination current density, reducing recombination and improving battery efficiency.

[0075] Example 2

[0076] The n-type front surface boron diffused crystalline silicon substrate was cleaned by standard RCA, and the surface was passivated by ALD deposition of aluminum oxide and PECVD deposition of silicon nitride; the electrode area was grooved by photolithography to remove the aluminum oxide and silicon nitride in the electrode area; HF treatment was used to remove the natural oxide layer, and TMAH was used to remove the damage, and the sample was weakly oxidized by hydrogen peroxide to generate an ultra-thin silicon oxide layer; then 30-100nm boron-doped amorphous silicon was deposited by PECVD; the alkali-resistant mask pattern was aligned and printed in the electrode area, and the sample was placed in an alkaline solution to selectively etch the amorphous silicon; the mask material was cleaned and removed; then the metal electrodes were printed on the front electrode area and the back by screen printing, and the belt furnace sintering was performed. According to this method, two battery samples were prepared and the battery efficiency was tested. The test results are shown in Table 2.

[0077] Comparative Example 2

[0078] The n-type front surface boron diffused crystalline silicon substrate was cleaned by standard RCA, and the surface was passivated by ALD deposition of aluminum oxide and PECVD deposition of silicon nitride; the electrode area was grooved by photolithography, and then metal electrodes were printed on the front electrode area and the back by screen printing, and then sintered in a belt furnace. Next, the battery efficiency test was carried out, and the test results are shown in Table 2.

[0079] Table 2. Comparison of typical results of batteries in Example 2 and Comparative Example 2

[0080]

[0081] The data of Example 2 and Comparative Example 2 show that the presence of the amorphous silicon selective emitter has an important effect on the open circuit voltage (V oc ) is significantly improved. Compared with batteries without selective emitters, the average efficiency of the prepared batteries can be increased by about 0.5%.

[0082] In summary, the selective emitter based on the tunneling oxide layer passivation contact structure of the present invention can not only avoid laser ablation damage and reduce efficiency, but also passivate the contact and reduce the recombination current, thereby improving the battery efficiency from many aspects.

[0083] It should be noted that the embodiments described above are only used to explain the present invention and do not constitute any limitation to the present invention. The present invention has been described with reference to typical embodiments, but it should be understood that the words used therein are descriptive and explanatory words, rather than restrictive words. The present invention may be modified within the scope of the present invention, and the present invention may be specified in the claims of the present invention without departing from the scope and spirit of the present invention. Although the present invention described therein relates to specific methods, materials and embodiments, it does not mean that the present invention is limited to the specific examples disclosed therein. On the contrary, the present invention can be extended to all other methods and applications with the same functions.

Claims

1. A selective emitter based on a tunneling oxide passivation contact structure, characterized in that: include: A low square resistance electrode region and a high square resistance non-electrode region, wherein the low square resistance electrode region includes: Crystalline silicon substrate; A TOPCon structure layer is disposed on a crystalline silicon substrate, wherein the TOPCon structure layer includes a tunneling ultra-thin oxide layer and a heavily doped amorphous silicon layer disposed on the tunneling ultra-thin oxide layer; and A metal electrode layer, which is disposed on the heavily doped amorphous silicon layer; High square resistance non-electrode areas include: Crystalline silicon substrate; a passivation layer disposed on the crystalline silicon substrate; and an anti-reflection layer disposed on the passivation layer; and tunneling through an ultra-thin oxide layer disposed on the anti-reflection layer; The passivation layer includes one or both of an aluminum oxide layer and a gallium oxide layer; The anti-reflection layer includes one or two of a silicon nitride layer and a magnesium fluoride layer; The thickness of the heavily doped amorphous silicon layer is less than the thickness of the anti-reflection layer; The crystalline silicon substrate is an n-type crystalline silicon substrate with boron diffusion.

2. The selective emitter based on tunneling oxide layer passivation contact structure according to claim 1, characterized in that: The thickness of the tunneling ultra-thin oxide layer is 1nm-2nm, the thickness of the heavily doped amorphous silicon layer is 20nm-200nm, the thickness of the passivation layer is 10nm-40nm, and the thickness of the anti-reflection layer is 50nm-200nm.

3. The selective emitter based on tunneling oxide layer passivation contact structure according to claim 1 or 2, characterized in that: The tunneling ultra-thin oxide layer includes an ultra-thin silicon dielectric film.

4. The selective emitter based on tunneling oxide layer passivation contact structure according to claim 1 or 2, characterized in that: The doping element in the heavily doped amorphous silicon layer is boron or phosphorus, the doping concentration range of boron is 1E17-5E20cm-3, and the doping concentration range of phosphorus is 1E18-1E21cm-3.

5. A method for preparing a selective emitter based on a tunneling oxide layer passivation contact structure as claimed in claim 1, characterized in that: The steps include: (1) Processing the silicon wafer substrate with texturing, diffusion, cleaning, etc.; (2) Depositing a passivation layer and an anti-reflection layer on the front side of the silicon wafer substrate in sequence; (3) Grooving the electrode region of the substrate obtained in step (2) by photolithography to remove the passivation layer and the anti-reflection layer in the electrode region; (4) forming a tunneling ultra-thin oxide layer on the surface of the material obtained in step (3) by a weak oxidation method, wherein the tunneling ultra-thin oxide layer covers the electrode region and the non-electrode region; (5) depositing a heavily doped amorphous silicon layer on the surface of the tunneling ultra-thin oxide layer obtained in step (4); (6) Setting a mask pattern in the electrode region, then etching and removing the heavily doped amorphous silicon layer in the non-electrode region, cleaning after etching, and removing the mask pattern in the electrode region; (7) Cleaning the mask and screen-printing a metal electrode in the electrode area, and sintering to obtain the selective emitter based on the tunneling oxide layer passivation contact structure.

6. Application of the selective emitter based on the tunneling oxide layer passivation contact structure as claimed in claim 1 in the field of solar cells.

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