Method for processing chrominance signal

Abstract

The present disclosure provides methods and systems for processing chrominance signals. According to some embodiments, the method may include: receiving a sequence parameter set (SPS); and determining whether chrominance residual scaling is enabled or disabled for a slice associated with the SPS based on a first flag signaled in the SPS.

Description

[0001] Cross - reference to related applications

[0002] This disclosure claims priority to U.S. Provisional Application No. 62 / 980,120, filed on February 21, 2020, which is hereby incorporated by reference in its entirety. Technical field

[0003] This disclosure generally relates to video processing, and more particularly, to methods and apparatuses for signaling parameters (e.g., chrominance residual scaling parameters, chrominance de - blocking parameters, etc.) for encoding chrominance signals. Background art

[0004] Video is a set of static images (or "frames") that capture visual information. To reduce storage memory and transmission bandwidth, video can be compressed before storage or transmission and then decompressed before display. The compression process is generally referred to as encoding, and the decompression process is generally referred to as decoding. There are various video coding formats that use standardized video coding techniques, most commonly based on prediction, transformation, quantization, entropy coding, and in - loop filtering. Standardization organizations have developed video coding standards, such as the High Efficiency Video Coding (HEVC / H.265) standard, the Versatile Video Coding (VVC / H.266) standard, and the AVS standard, which specify specific video coding formats. As more and more advanced video coding techniques are adopted in video standards, the coding efficiency of new video coding standards is getting higher and higher. Summary of the invention

[0005] Embodiments of the present disclosure provide a video decoding method. The method includes: receiving a Sequence Parameter Set (SPS); and determining whether chrominance residual scaling is enabled or disabled for a slice associated with the SPS based on a first flag signaled in the SPS.

[0006] Embodiments of the present disclosure also provide a video coding method. The method includes: signaling a first flag in a Sequence Parameter Set (SPS) associated with a slice, the first flag indicating whether chrominance residual scaling of the slice is enabled or disabled.

[0007] Embodiments of the present disclosure also provide a video encoder. The video encoder includes a memory for storing a set of instructions, and at least one processor configured to execute the set of instructions to cause the system to perform: receiving a Sequence Parameter Set (SPS); and determining whether chrominance residual scaling is enabled or disabled for a slice associated with the SPS based on a first flag signaled in the SPS.

[0008] Embodiments of the present disclosure also provide a video decoder. The video decoder includes a memory for storing an instruction set, and at least one processor configured to execute the instruction set to cause the system to perform: signaling a first flag in a sequence parameter set (SPS) associated with a slice, the first flag indicating whether chrominance residual scaling is enabled or disabled for the slice.

[0009] Embodiments of the present disclosure also provide a non-transitory computer-readable medium storing an instruction set executable by at least one processor of a computer system to cause the computer system to perform a method for decoding video content. The method includes: receiving a sequence parameter set (SPS); and determining whether chrominance residual scaling is enabled or disabled for a slice associated with the SPS based on a first flag signaled in the SPS.

[0010] Embodiments of the present disclosure also provide a non-transitory computer-readable medium storing an instruction set executable by at least one processor of a computer system to cause the computer system to perform a method for encoding video content. The method includes: signaling a first flag in a sequence parameter set (SPS) associated with a slice, the first flag indicating whether chrominance residual scaling is enabled or disabled for the slice.

[0011] Embodiments of the present disclosure provide a video processing method. The method includes: determining whether a video sequence is monochrome; and in response to determining that the video sequence is not monochrome, signaling chrominance deblocking parameters in a bitstream associated with the video sequence, wherein when the video sequence is monochrome, the chrominance deblocking parameters are not signaled in the bitstream.

[0012] Embodiments of the present disclosure also provide a video processing apparatus. The apparatus includes: a memory for storing an instruction set; and at least one processor configured to execute the instruction set to cause the system to perform: determining whether a video sequence is monochrome; and in response to determining that the video sequence is not monochrome, signaling chrominance deblocking parameters in a bitstream associated with the video sequence, wherein when the video sequence is monochrome, the chrominance deblocking parameters are not signaled in the bitstream.

[0013] Embodiments of the present disclosure also provide a non-transitory computer-readable medium storing an instruction set executable by at least one processor of a computer system to cause the computer system to perform a method for processing video content. The method includes: determining whether a video sequence is monochrome; and in response to determining that the video sequence is not monochrome, signaling chrominance deblocking parameters in a bitstream associated with the video sequence, wherein when the video sequence is monochrome, the chrominance deblocking parameters are not signaled in the bitstream. Description of the Drawings

[0014] Embodiments and aspects of the present disclosure are shown in the following detailed description and the drawings. The various features shown in the drawings are not drawn to scale.

[0015] Figure 1 is a schematic structural diagram of an exemplary video sequence according to some embodiments of the present disclosure.

[0016] Figure 2A is a schematic diagram showing an exemplary encoding process of a hybrid video coding system consistent with embodiments of the present disclosure.

[0017] Figure 2B is a schematic diagram showing another exemplary encoding process of a hybrid video coding system consistent with embodiments of the present disclosure.

[0018] Figure 3A is a schematic diagram showing an exemplary decoding process of a hybrid video coding system consistent with embodiments of the present disclosure.

[0019] Figure 3B is a schematic diagram showing another exemplary decoding process of a hybrid video coding system consistent with embodiments of the present disclosure.

[0020] Figure 4 is a block diagram of an exemplary apparatus for encoding or decoding video according to some embodiments of the present disclosure.

[0021] Figure 5 is a syntax table showing an exemplary Picture Header (PH)-level Luminance Mapping Chrominance Scaling (LMCS) syntax consistent with embodiments of the present disclosure.

[0022] Figure 6 is a syntax table showing an exemplary slice-level LMCS syntax consistent with embodiments of the present disclosure.

[0023] Figure 7 shows an implementation consistent with embodiments of the present disclosure Figure 5 and Figure 6 an example of the syntax shown.

[0024] Figure 8 shows a syntax table of an exemplary PH-level LMCS syntax consistent with embodiments of the present disclosure.

[0025] Figure 9 is a syntax table showing an exemplary slice-level LMCS syntax consistent with embodiments of the present disclosure.

[0026] Figure 10 shows an implementation consistent with embodiments of the present disclosure Figure 8 andFigure 9 An example of the syntax shown.

[0027] Figure 11 A syntax table showing an exemplary PH-level LMCS syntax consistent with an embodiment of the present disclosure.

[0028] Figure 12 A syntax table showing an exemplary slice-level LMCS syntax consistent with an embodiment of the present disclosure.

[0029] Figure 13 A syntax table showing an exemplary PH-level syntax for signaling chroma deblocking parameters consistent with an embodiment of the present disclosure.

[0030] Figure 14 A syntax table showing an exemplary slice-level syntax for signaling chroma deblocking parameters consistent with an embodiment of the present disclosure.

[0031] Figure 15 A syntax table showing an exemplary picture parameter set (PPS) syntax for signaling chroma deblocking parameters consistent with an embodiment of the present disclosure.

[0032] Figure 16 A syntax table showing an exemplary PPS syntax consistent with an embodiment of the present disclosure, where pps_chroma_tool_offsets_present_flag is replaced by ChromaArrayType.

[0033] Figure 17 A syntax table showing an exemplary PPS syntax for signaling chroma deblocking parameters consistent with an embodiment of the present disclosure.

[0034] Figure 18 A flowchart of an exemplary method for signaling LMCS parameters consistent with an embodiment of the present disclosure.

[0035] Figure 19 A flowchart of an exemplary method for signaling LMCS parameters consistent with an embodiment of the present disclosure.

[0036] Figure 20 A flowchart of an exemplary method for signaling chroma deblocking parameters consistent with an embodiment of the present disclosure. Detailed implementation

[0037] Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. The following description refers to the accompanying drawings, unless otherwise noted, where like numbers in different drawings represent the same or similar elements. The embodiments set forth in the following description of the exemplary embodiments do not represent all embodiments consistent with the present disclosure. Rather, they are merely examples of apparatus and methods consistent with aspects related to the present disclosure as recited in the appended claims. Specific aspects of the present disclosure are described in more detail below. If there is a conflict with terms and / or definitions incorporated by reference, the terms and definitions provided herein shall control.

[0038] The Joint Video Exploration Team (JVET) of the ITU-T Video Coding Experts Group (ITU-T VCEG) and the ISO / IEC Moving Picture Experts Group (ISO / IEC MPEG) is currently developing the Versatile Video Coding (VVC / H.266) standard. The VVC standard aims to double the compression efficiency of its predecessor, the High Efficiency Video Coding (HEVC / H.265) standard. In other words, the goal of VVC is to achieve the same subjective quality as HEVC / H.265 using half the bandwidth.

[0039] To achieve the same subjective quality as HEVC / H.265 using half the bandwidth, JVET has been using the Joint Exploration Model (JEM) reference software to explore technologies beyond HEVC. As coding technologies are incorporated into JEM, JEM has achieved higher coding performance than HEVC.

[0040] The VVC standard has been recently developed and continues to include more coding technologies that provide better compression performance. VVC is based on the hybrid video coding system that has been used in modern video compression standards such as HEVC, H.264 / AVC, MPEG2, H.263, etc.

[0041] Video is a set of static images (or "frames") arranged in chronological order to store visual information. These images can be captured and stored in chronological order using a video capture device (e.g., a camera), and can be displayed in a time series using a video playback device (e.g., a television, computer, smartphone, tablet computer, video player, or any end-user terminal with a display function). In addition, in some applications, the video capture device can send the captured video to the video playback device (e.g., a computer with a monitor) in real time, such as for surveillance, conferencing, or live broadcasting.

[0042] To reduce the storage space and transmission bandwidth required for such applications, the video can be compressed before storage and transmission and decompressed before display. Compression and decompression can be implemented by software executed by a processor (e.g., the processor of a general-purpose computer) or dedicated hardware. The module for compression is generally referred to as an "encoder", and the module for decompression is generally referred to as a "decoder". The encoder and decoder can be collectively referred to as a "codec". The encoder and decoder can be implemented as any of a variety of suitable hardware, software, or combinations thereof. For example, the hardware implementation of the encoder and decoder can include circuits such as one or more microprocessors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), discrete logic, or any combination thereof. The software implementation of the encoder and decoder can include program code fixed in a computer-readable medium, computer-executable instructions, firmware, or any suitable computer-implemented algorithm or process. Video compression and decompression can be implemented by various algorithms or standards, such as MPEG-1, MPEG-2, MPEG-4, the H.26x series, etc. In some applications, the codec can decompress the video from a first coding standard and recompress the decompressed video using a second coding standard, in which case the codec can be referred to as a "transcoder".

[0043] The video encoding process can identify and retain useful information that can be used to reconstruct the image and ignore unimportant reconstruction information. If the unimportant information cannot be fully reconstructed when ignored, such an encoding process can be called "lossy". Otherwise, it can be called "lossless". Most encoding processes are lossy as a trade-off to reduce the required storage space and transmission bandwidth.

[0044] The useful information of the encoded image (referred to as the "current image") includes the changes relative to a reference image (e.g., a previously encoded and reconstructed image). Such changes can include changes in the position of pixels, changes in brightness, or changes in color, with the change in position being the most concerned. The change in the position of a group of pixels representing an object can reflect the movement of the object between the reference image and the current image.

[0045] An image encoded without referring to another image (i.e., it is its own reference image) is called an "I-image". An image encoded using a previous image as a reference image is called a "P-image", and an image encoded using a previous image and a future image as reference images is called a "B-image" (the reference is "bidirectional").

[0046] Figure 1shows the structure of an example video sequence 100 in accordance with some embodiments of the present disclosure. The video sequence 100 can be a live video or a video that has been captured and archived. The video 100 can be a real-life video, a computer-generated video (e.g., a computer game video), or a combination of both (e.g., a real video with augmented reality effects). The video sequence 100 can be input from a video capture device (e.g., a camera), a video archive containing previously captured videos (e.g., a video file stored in a storage device), or a video feed interface (e.g., a video broadcast transceiver) that receives video from a video content provider.

[0047] As Figure 1 shown, the video sequence 100 can include a series of images arranged in time along a timeline, including images 102, 104, 106, and 108. Images 102 - 106 are consecutive, with more images between images 106 and 108. In Figure 1 this example, image 102 is an I-image, and its reference image is image 102 itself. Image 104 is a P-image, and its reference image is image 102, as indicated by the arrow. Image 106 is a B-image, and its reference images are images 104 and 108, as indicated by the arrows. In some embodiments, the reference image of an image (e.g., image 104) may not be immediately before or after the image. For example, the reference image of image 104 can be an image before image 102. It should be noted that the reference images of images 102 - 106 are merely examples, and the present disclosure does not limit the embodiments of the reference images as Figure 1 shown.

[0048] Generally, due to the computational complexity of the encoding and decoding tasks, video codecs do not encode or decode an entire image at once. Instead, they can divide the image into basic segments and encode or decode the image segments one by one. In the present disclosure, such a basic segment is referred to as a basic processing unit (“BPU”). For example, Figure 1The structure 110 therein shows an example structure of an image (e.g., any of the images 102-108) in the video sequence 100. In the structure 110, the image is divided into 4×4 basic processing units, the boundaries of which are shown as dashed lines. In some embodiments, the basic processing unit may be referred to as a "macroblock" in some video coding standards (e.g., the MPEG family, H.261, H.263, or H.264 / AVC), or as a "coding tree unit" ("CTU") in some other video coding standards (e.g., H.265 / HEVC or H.266 / VVC). The basic processing unit may have a variable size in the image, such as 128×128, 64×64, 32×32, 16×16, 4×8, 16×32, or pixels of any shape and size. The size and shape of the basic processing unit can be selected for the image based on a balance between coding efficiency and the level of detail to be maintained in the basic processing unit.

[0049] The basic processing unit can be a logical unit that may include a set of different types of video data stored in a computer memory (e.g., in a video frame buffer). For example, the basic processing unit of a color image may include a luminance component (Y) representing achromatic luminance information, one or more chrominance components representing color information (e.g., Cb and Cr), and associated syntax elements, where the luminance and chrominance components may have the same size as the basic processing unit. In some video coding standards (e.g., H.265 / HEVC or H.266 / VVC), the luminance and chrominance components may be referred to as "coding tree blocks" ("CTB"). Any operation performed on the basic processing unit can be repeated for each of its luminance and chrominance components.

[0050] Video coding has multiple operation stages, examples of which are Figures 2A - 2B and Figures 3A - 3BAs shown. For each stage, the size of the basic processing unit may still be too large for processing, so it can be further divided into segments called "basic processing subunits" in the present disclosure. In some embodiments, the basic processing subunit may be called a "block" in some video coding standards (e.g., the MPEG family, H.261, H.263, or H.264 / AVC), or an "encoding unit" ("CU") in some other video coding standards (e.g., H.265 / HEVC or H.266 / VVC). The basic processing subunit may have the same size as the basic processing unit or a smaller size than the basic processing unit. Similar to the basic processing unit, the basic processing subunit is also a logical unit, which may include a set of different types of video data (e.g., Y, Cb, Cr, and associated syntax elements) stored in a computer memory (e.g., in a video frame buffer). Any operation performed on the basic processing subunit can be repeated for each of its luminance and chrominance components. It should be noted that this division can be performed to a further level according to processing needs. It should also be noted that different stages may use different schemes to divide the basic processing unit.

[0051] For example, in the mode decision stage (an example of which is shown in Figure 2B ), the encoder can decide what prediction mode (e.g., intra prediction or inter prediction) to use for the basic processing unit, which may be too large to make such a decision. The encoder can divide the basic processing unit into multiple basic processing subunits (e.g., CUs in H.265 / HEVC or H.266 / VVC), and decide the prediction type for each individual basic processing subunit.

[0052] For another example, in the prediction stage (an example of which is shown in Figures 2A - 2B ), the encoder can perform prediction operations at the level of the basic processing subunit (e.g., CU). However, in some cases, the basic processing subunit may still be too large to process. The encoder can further divide the basic processing subunit into smaller segments (e.g., called "prediction blocks" or "PBs" in H.265 / HEVC or H.266 / VVC), at which level the prediction operations can be performed.

[0053] For another example, in the transform stage (an example of which is shown in Figures 2A - 2BAs shown (in [figure reference]), the encoder may perform a transform operation on a residual basic processing subunit (e.g., a CU). However, in some cases, the basic processing subunit may still be too large to process. The encoder may further divide the basic processing subunit into smaller segments (e.g., called "transformation blocks" or "TBs" in H.265 / HEVC or H.266 / VVC), at which level the transform operation can be performed. It should be noted that the partitioning scheme for the same basic processing subunit may be different in the prediction stage and the transform stage. For example, in H.265 / HEVC or H.266 / VVC, the prediction blocks and transform blocks of the same CU may have different sizes and numbers.

[0054] In Figure 1 the structure 110, the basic processing unit 112 is further divided into 3×3 basic processing subunits, the boundaries of which are shown as dashed lines. Different basic processing units of the same image may be divided into basic processing subunits in different schemes.

[0055] In some embodiments, to provide the ability for parallel processing and fault tolerance for video encoding and decoding, an image may be divided into regions for processing such that for a region of the image, the encoding or decoding process may not depend on information from any other region of the image. In other words, each region of the image can be processed independently. By doing so, the codec can process different regions of the image in parallel, thereby improving the encoding efficiency. Additionally, when the data of a region is corrupted during processing or lost during network transmission, the codec can correctly encode or decode other regions of the same image without relying on the corrupted or lost data, thereby providing fault tolerance. In certain video coding standards, an image may be divided into different types of regions. For example, H.265 / HEVC and H.266 / VVC provide two types of regions: "slices" and "tiles". It should also be noted that different images of the video sequence 100 may have different partitioning schemes for dividing the image into regions.

[0056] For example, in Figure 1 the structure 110 is divided into three regions 114, 116, and 118, the boundaries of which are shown as solid lines inside the structure 110. Region 114 includes four basic processing units. Regions 116 and 118 each include six basic processing units. It should be noted that Figure 1 the basic processing units, basic processing subunits, and structural regions in 110 are only examples, and the present disclosure does not limit its embodiments.

[0057] Figure 2A shows a schematic diagram of an exemplary encoding process 200A according to an embodiment of the present disclosure. For example, the encoding process 200A may be performed by an encoder. As Figure 2AAs shown, an encoder may encode video sequence 202 into video bitstream 228 according to process 200A. Similar to Figure 1 the video sequence 100 in Figure 1 , the video sequence 202 may include a set of images arranged in chronological order (referred to as "original images"). Similar to

[0058] the structure 110 in Figure 2A , each original image of the video sequence 202 may be divided by the encoder into basic processing units, basic processing subunits, or regions for processing. In some embodiments, the encoder may execute process 200A at the level of basic processing units for each original image of the video sequence 202. For example, the encoder may execute process 200A in an iterative manner, where the encoder may encode a basic processing unit in one iteration of process 200A. In some embodiments, the encoder may execute process 200A in parallel for regions (e.g., regions 114 - 118) of each original image of the video sequence 202.

[0059] Referring to , the encoder may feed a basic processing unit of an original image of the video sequence 202 (referred to as "original BPU") to prediction stage 204 to generate prediction data 206 and prediction BPU 208. The encoder may subtract the predicted BPU 208 from the original BPU to generate residual BPU 210. The encoder may feed the residual BPU 210 to transform stage 212 and quantization stage 214 to generate quantized transform coefficients 216. The encoder may feed the prediction data 206 and the quantized transform coefficients 216 to binary coding stage 226 to generate video bitstream 228. Components 202, 204, 206, 208, 210, 212, 214, 216, 226, and 228 may be referred to as the "forward path". During process 200A, after quantization stage 214, the encoder may feed the quantized transform coefficients 216 to inverse quantization stage 218 and inverse transform stage 220 to generate a reconstructed residual BPU 222. The encoder may add the reconstructed residual BPU 222 to the predicted BPU 208 to generate prediction reference 224, which is used in prediction stage 204 for the next iteration of process 200A. Components 218, 220, 222, and 224 of process 200A may be referred to as the "reconstruction path". The reconstruction path may be used to ensure that both the encoder and the decoder use the same reference data for prediction.

[0059] The encoder may iteratively execute process 200A to encode each original BPU (in the forward path) of the encoded original image and generate prediction reference 224 for the next original BPU (in the reconstruction path) of the encoded original image. After encoding all the original BPUs of the original image, the encoder may continue to encode the next image in the video sequence 202.

[0060] Referring to process 200A, the encoder may receive video sequence 202 generated by a video capture device (e.g., a camera). The term "receive" as used herein may refer to any action of receiving, inputting, obtaining, retrieving, fetching, reading, accessing, or using for inputting data in any way.

[0061] In prediction stage 204, at the current iteration, the encoder may receive the original BPU and prediction reference 224, and perform a prediction operation to generate prediction data 206 and prediction BPU 208. The prediction reference 224 may be generated from the reconstruction path of a previous iteration of process 200A. The purpose of prediction stage 204 is to reduce information redundancy by extracting prediction data 206 from prediction data 206 and prediction reference 224 that can be used to reconstruct the original BPU into prediction BPU 208.

[0062] Ideally, the predicted BPU 208 may be the same as the original BPU. However, due to non-ideal prediction and reconstruction operations, the predicted BPU 208 is typically slightly different from the original BPU. To record these differences, when generating the prediction BPU 208, the encoder may subtract it from the original BPU to generate a residual BPU 210. For example, the encoder may subtract the value of the corresponding pixel of the prediction BPU 208 from the value of the pixel of the original BPU (e.g., grayscale value or RGB value). Each pixel of the residual BPU 210 may have a residual value as the result of such subtraction between the corresponding pixels of the original BPU and the prediction BPU 208. Compared with the original BPU, the prediction data 206 and the residual BPU 210 may have fewer bits, but they can be used to reconstruct the original BPU without significant quality degradation. Thus, the original BPU is compressed.

[0063] To further compress the residual BPU 210, in transform stage 212, the encoder may reduce its spatial redundancy by decomposing the residual BPU 210 into a set of two-dimensional "base patterns". Each base pattern is associated with a "transformation coefficient". The base patterns may have the same size (e.g., the size of the residual BPU 210), and each base pattern may represent a frequency component of the variation of the residual BPU 210 (e.g., the frequency of brightness variation). None of the base patterns can be reproduced from any combination (e.g., linear combination) of any other base patterns. In other words, the decomposition can decompose the variation of the residual BPU 210 into the frequency domain. This decomposition is similar to the discrete Fourier transform of a function, where the base images are similar to the basic functions of the discrete Fourier transform (e.g., trigonometric functions), and the transformation coefficients are similar to the coefficients associated with the basic functions.

[0064] Different transformation algorithms can use different basic patterns. Various transformation algorithms can be used at the transformation stage 212, such as, for example, the discrete cosine transform, the discrete sine transform, etc. The transformation at the transformation stage 212 is reversible. That is, the encoder can recover the residual BPU 210 through the inverse operation of the transformation (referred to as "inverse transformation"). For example, in order to recover the pixels of the residual BPU 210, the inverse transformation can be to multiply the values of the corresponding pixels of the basic pattern by the corresponding correlation coefficients and add the products to produce a weighted sum. For video coding standards, both the encoder and the decoder can use the same transformation algorithm (and thus have the same basic pattern). Therefore, the encoder can record only the transformation coefficients, and the decoder can reconstruct the residual BPU 210 therefrom without receiving the basic pattern from the encoder. Compared with the residual BPU 210, the transformation coefficients can have fewer bits, but they can be used to reconstruct the residual BPU 210 without significant quality degradation. Thus, the residual BPU 210 is further compressed.

[0065] The encoder can further compress the transformation coefficients at the quantization stage 214. During the transformation process, different basic patterns can represent different change frequencies (e.g., luminance change frequencies). Since the human eye is generally better at recognizing low-frequency changes, the encoder can ignore the information of high-frequency changes without causing significant quality degradation in decoding. For example, at the quantization stage 214, the encoder can generate the quantized transformation coefficients 216 by dividing each transformation coefficient by an integer value (referred to as "quantization parameter") and rounding the quotient to its nearest integer. After such an operation, some transformation coefficients of the high-frequency basic pattern can be converted to zero, and the transformation coefficients of the low-frequency basic pattern can be converted to smaller integers. The encoder can ignore the quantized transformation coefficients 216 with zero values, whereby the transformation coefficients are further compressed. This quantization process is also reversible, where the quantized transformation coefficients 216 can be reconstructed as transformation coefficients in the inverse operation of quantization (referred to as "inverse quantization").

[0066] Since the encoder ignores the remainder of the division in the rounding operation, the quantization stage 214 can be lossy. Generally, the quantization stage 214 can contribute the most information loss in the process 200A. The greater the information loss, the fewer bits required for the quantized transformation coefficients 216. To obtain different levels of information loss, the encoder can use different quantization parameter values or any other parameters of the quantization process.

[0067] In the binary coding stage 226, the encoder may encode the prediction data 206 and the quantized transform coefficients 216 using binary coding techniques, such as entropy coding, variable length coding, arithmetic coding, Huffman coding, context - adaptive binary arithmetic coding, or any other lossless or lossy compression algorithm. In some embodiments, in addition to the prediction data 206 and the quantized transform coefficients 216, the encoder may encode other information in the binary coding stage 226, such as the prediction mode used in the prediction stage 204, the parameters of the prediction operation, the type of transform at the transform stage 212, the parameters of the quantization process (e.g., quantization parameter), the encoder control parameters (e.g., bit - rate control parameter), etc. The encoder may use the output data of the binary coding stage 226 to generate the video bitstream 228. In some embodiments, the video bitstream 228 may be further packed for network transmission.

[0068] Referring to the reconstruction path of process 200A, in the inverse quantization stage 218, the encoder may perform inverse quantization on the quantized transform coefficients 216 to generate the reconstructed transform coefficients. In the inverse transform stage 220, the encoder may generate the reconstructed residual BPU 222 based on the reconstructed transform coefficients. The encoder may add the reconstructed residual BPU 222 to the prediction BPU 208 to generate the prediction reference 224 that will be used in the next iteration of process 200A.

[0069] It should be noted that other variants of process 200A may be used to encode the video sequence 202. In some embodiments, the stages of process 200A may be executed by the encoder in a different order. In some embodiments, one or more stages of process 200A may be combined into a single stage. In some embodiments, a single stage of process 200A may be divided into multiple stages. For example, the transform stage 212 and the quantization stage 214 may be combined into a single stage. In some embodiments, process 200A may include additional stages. In some embodiments, process 200A may omit Figure 2A one or more of the

[0070] Figure 2B FIG. shows a schematic diagram of another exemplary encoding process 200B according to an embodiment of the present disclosure. Process 200B may be modified from process 200A. For example, process 200B may be used by an encoder compliant with a hybrid video coding standard (e.g., H.26x series). Compared with process 200A, the forward path of process 200B further includes a mode decision stage 230 and divides the prediction stage 204 into a spatial prediction stage 2042 and a temporal prediction stage 2044, and the reconstruction path of process 200B further includes a loop filter stage 232 and a buffer 234.

[0071] Generally, prediction techniques can be classified into two types: spatial prediction and temporal prediction. Spatial prediction (e.g., intra-image prediction or "intra prediction") can use pixels from one or more already-encoded neighboring BPUs in the same image to predict the current BPU. That is, the prediction reference 224 in spatial prediction can include neighboring BPUs. Spatial prediction can reduce the spatial redundancy inherent in the image. Temporal prediction (e.g., inter-image prediction or "inter prediction") can use regions from one or more already-encoded images to predict the current BPU. That is, the prediction reference 224 in temporal prediction can include encoded images. Temporal prediction can reduce the temporal redundancy inherent in the image.

[0072] Referring to process 200B, in the forward path, the encoder performs prediction operations in the spatial prediction stage 2042 and the temporal prediction stage 2044. For example, in the spatial prediction stage 2042, the encoder can perform intra prediction. For the original BPU of the encoded image, the prediction reference 224 can include one or more neighboring BPUs that have been encoded (in the forward path) and reconstructed (in the reconstruction path) in the same image. The encoder can generate a predicted BPU 208 by interpolating the neighboring BPUs. The interpolation technique can include, for example, linear interpolation or interpolation, polynomial interpolation or interpolation, etc. In some embodiments, the encoder can perform interpolation at the pixel level, for example, by interpolating the values of the corresponding pixels of each pixel of the predicted BPU 208. The neighboring BPUs used for interpolation can be located in various directions relative to the original BPU, such as in the vertical direction (e.g., on top of the original BPU), horizontal direction (e.g., to the left of the original BPU), diagonal direction (e.g., bottom left, bottom right, top left, or top right of the original BPU), or any direction defined in the video coding standard being used. For intra prediction, the prediction data 206 can include, for example, the positions (e.g., coordinates) of the neighboring BPUs used, the sizes of the neighboring BPUs used, the parameters of the interpolation, the direction of the neighboring BPUs relative to the original BPU, etc.

[0073] For another example, at the time prediction stage 2044, the encoder may perform inter-frame prediction. For the original BPU of the current image, the prediction reference 224 may include one or more images (referred to as "reference images") that have been encoded (in the forward path) and reconstructed (in the reconstruction path). In some embodiments, the reference images may be encoded and reconstructed on a per-BPU basis. For example, the encoder may add the reconstructed residual BPU 222 to the prediction BPU 208 to generate a reconstructed BPU. When all the reconstructed BPUs of the same image have been generated, the encoder may generate a reconstructed image as a reference image. The encoder may perform an operation of "motion estimation" to search for a matching region within the range of the reference image (referred to as the "search window"). The position of the search window in the reference image may be determined based on the position of the original BPU in the current image. For example, the search window may be centered at a position in the reference image that has the same coordinates as the original BPU in the current image and may extend outward a predetermined distance. When the encoder identifies (e.g., by using a pel recursive algorithm, a block matching algorithm, etc.) a region in the search window that is similar to the original BPU, the encoder may determine such a region as the matching region. The matching region may have a different size (e.g., smaller than, equal to, larger than, or a different shape) from the original BPU. Since the reference image and the current image are temporally separated on the timeline (e.g., as Figure 1 shown), the matching region may be considered to "move" over time to the position of the original BPU. The encoder may record the direction and distance of this motion as a "motion vector". When multiple reference images are used (e.g., as in Figure 1 image 106), the encoder may search for the matching region and determine its associated motion vector for each reference image. In some embodiments, the encoder may assign weights to the pixel values of the matching regions of the respective matching reference images.

[0074] Motion estimation can be used to identify various types of motion, such as translation, rotation, scaling, etc. For inter-frame prediction, the prediction data 206 may include, for example, the position (e.g., coordinates) of the matching region, the motion vector associated with the matching region, the number of reference images, the weights associated with the reference images, etc.

[0075] To generate the predicted BPU 208, the encoder may perform an operation of "motion compensation". Motion compensation can be used to reconstruct the predicted BPU 208 based on the prediction data 206 (e.g., the motion vector) and the prediction reference 224. For example, the encoder may move the matching region of the reference image according to the motion vector, where the encoder may predict the original BPU of the current image. When multiple reference images are used (e.g., as in Figure 1In the image 106), the encoder can move the matching region of the reference image according to the respective motion vectors and average pixel values of the matching regions. In some embodiments, if the encoder has assigned weights to the pixel values of the matching regions of the respective matching reference images, the encoder can sum the weighted sum of the pixel values of the moved matching regions.

[0076] In some embodiments, the inter-frame prediction can be unidirectional or bidirectional. Unidirectional inter-frame prediction can use one or more reference images in the same time direction relative to the current image. For example, Figure 1 the image 104 in is a unidirectional inter-frame prediction image, where the reference image (i.e., image 102) is before image 04. Bidirectional inter-frame prediction can use one or more reference images in two time directions relative to the current image. For example, Figure 1 the image 106 in is a bidirectional inter-frame prediction image, where the reference images (i.e., images 104 and 08) are in two time directions relative to image 104.

[0077] Still referring to the forward path of process 200B, after the spatial prediction 2042 and the temporal prediction stage 2044, at the mode decision stage 230, the encoder can select a prediction mode (e.g., one of intra-frame prediction or inter-frame prediction) for the current iteration of process 200B. For example, the encoder can perform rate-distortion optimization techniques, where the encoder can select a prediction mode to minimize the value of the cost function according to the bit rate of the candidate prediction mode and the distortion of the reconstructed reference image under the candidate prediction mode. According to the selected prediction mode, the encoder can generate the corresponding prediction BPU 208 and prediction data 206.

[0078] In the reconstruction path of process 200B, if an intra prediction mode has been selected in the forward path, after generating the prediction reference 224 (e.g., the current BPU that has been encoded and reconstructed in the current image), the encoder can directly feed the prediction reference 224 to the spatial prediction stage 2042 for later use (e.g., for interpolating the next BPU of the current image). If an inter prediction mode has been selected in the forward path, after generating the prediction reference 224 (e.g., the current image in which all BPUs have been encoded and reconstructed), the encoder can feed the prediction reference 224 to the loop filter stage 232. At this stage, the encoder can apply a loop filter to the prediction reference 224 to reduce or eliminate the distortion introduced by inter prediction (e.g., blocking artifacts). The encoder can apply various loop filter techniques at the loop filter stage 232, such as deblocking, sample adaptive compensation, adaptive loop filter, etc. The loop-filtered reference image can be stored in the buffer 234 (or "decoded image buffer") for later use (e.g., as an inter prediction reference image for future images of the video sequence 202). The encoder can store one or more reference images in the buffer 234 for use at the temporal prediction stage 2044. In some embodiments, the encoder can encode the parameters of the loop filter (e.g., loop filter strength) as well as the quantized transform coefficients 216, prediction data 206, and other information at the binary coding stage 226.

[0079] Figure 3A FIG. shows a schematic diagram of an exemplary decoding process 300A according to an embodiment of the present disclosure. Process 300A can be a decompression process corresponding to Figure 2A the compression process 200A therein. In some embodiments, process 300A can be similar to the reconstruction path of process 200A. The decoder can decode the video bitstream 228 into a video stream 304 according to process 300A. The video stream 304 can be very similar to the video sequence 202. However, due to information loss during the compression and decompression processes (e.g., Figures 2A - 2B the quantization stage 214 therein), generally, the video stream 304 is different from the video sequence 202. Similar to Figures 2A - 2B processes 200A and 200B therein, the decoder can perform process 300A on each image encoded in the video bitstream 228 at the basic processing unit (BPU) level. For example, the decoder can perform process 300A iteratively, where the decoder can decode a basic processing unit in one iteration of process 300A. In some embodiments, the decoder can perform process 300A in parallel for each region (e.g., regions 114-118) of each image encoded in the video bitstream 228.

[0080] As Figure 3AAs shown, the decoder may feed a portion of the video bitstream 228 associated with a basic processing unit of the encoded image (referred to as an “encoded BPU”) into a binary decoding stage 302, where the decoder may decode the portion into prediction data 206 and quantized transform coefficients 216. The decoder may feed the quantized transform coefficients 216 into an inverse quantization stage 218 and an inverse transform stage 220 to generate a reconstructed residual BPU 222. The decoder may feed the prediction data 206 into a prediction stage 204 to generate a predicted BPU 208. The decoder may add the reconstructed residual BPU 222 to the predicted BPU 208 to generate a prediction reference 224. In some embodiments, the prediction reference 224 may be stored in a buffer (e.g., a decoded image buffer in a computer memory). The decoder may feed the prediction reference 224 into the prediction stage 204 for performing a prediction operation in a next iteration of process 300A.

[0081] The decoder may iteratively execute process 300A to decode each encoded BPU of the encoded image and generate a prediction reference 224 for a next encoded BPU of the encoded image. After decoding all the encoded BPUs of the encoded image, the decoder may output the image to a video stream 304 for display and continue to decode a next encoded image in the video bitstream 228.

[0082] In the binary decoding stage 302, the decoder may perform an inverse operation of a binary encoding technique used by the encoder (e.g., entropy encoding, variable length encoding, arithmetic encoding, Huffman encoding, context adaptive binary arithmetic encoding, or any other lossless compression algorithm). In some embodiments, in addition to the prediction data 206 and the quantized transform coefficients 216, the decoder may decode other information in the binary decoding stage 302, such as a prediction mode, parameters of a prediction operation, a transform type, parameters of a quantization process (e.g., quantization parameters), encoder control parameters (e.g., bitrate control parameters), etc. In some embodiments, if the video bitstream 228 is transmitted in packets over a network, the decoder may unpack the video bitstream 228 before feeding it into the binary decoding stage 302.

[0083] Figure 3B A schematic diagram of another example decoding process 300B according to an embodiment of the present disclosure is shown. Process 300B may be modified from process 300A. For example, process 300B may be used by a decoder compliant with a hybrid video coding standard (e.g., the H.26x series). Compared with process 300A, process 300B additionally divides the prediction stage 204 into a spatial prediction stage 2042 and a temporal prediction stage 2044, and additionally includes a loop filter stage 232 and a buffer 234.

[0084] In process 300B, for an encoded basic processing unit (referred to as "current BPU") of a decoded encoded image (referred to as "current image"), the prediction data 206 decoded by the decoder from the binary decoding stage 302 can include various types of data, depending on what prediction mode the encoder uses to encode the current BPU. For example, if the encoder uses intra prediction to encode the current BPU, the prediction data 206 can include a prediction mode indicator (e.g., a flag value) indicating intra prediction, parameters of the intra prediction operation, etc. The parameters of the intra prediction operation can include, for example, the positions (e.g., coordinates) of one or more adjacent BPUs used as references, the sizes of the adjacent BPUs, interpolation parameters, the directions of the adjacent BPUs relative to the original BPU, etc. For another example, if the encoder uses inter prediction to encode the current BPU, the prediction data 206 can include a prediction mode indicator (e.g., a flag value) indicating inter prediction, parameters of the inter prediction operation, etc. The parameters of the inter prediction operation can include, for example, the number of reference images associated with the current BPU, the weights respectively associated with the reference images, the positions (e.g., coordinates) of one or more matching regions in the corresponding reference images, one or more motion vectors respectively associated with the matching regions, etc.

[0085] Based on the prediction mode indicator, the decoder can decide whether to perform spatial prediction (e.g., intra prediction) in the spatial prediction stage 2042 or temporal prediction (e.g., inter prediction) in the temporal prediction stage 2044. The details of performing such spatial prediction or temporal prediction are described in Figure 2B and will not be repeated hereinafter. After performing such spatial prediction or temporal prediction, the decoder can generate a predicted BPU 208. The decoder can add the predicted BPU 208 and the reconstructed residual BPU 222 to generate a prediction reference 224, as described in Figure 3A below.

[0086] In process 300B, the decoder can feed the prediction reference 224 to the spatial prediction stage 2042 or the temporal prediction stage 2044 for performing prediction operations in the next iteration of process 300B. For example, if the current BPU is decoded using intra prediction in the spatial prediction stage 2042, after generating the prediction reference 224 (e.g., the decoded current BPU), the decoder can directly feed the prediction reference 224 to the spatial prediction stage 2042 for later use (e.g., for interpolating the next BPU of the current image). If the current BPU is decoded using inter prediction in the temporal prediction stage 2044, after generating the prediction reference 224 (e.g., the reference image in which all BPUs are decoded), the encoder can feed the prediction reference 224 to the loop filter stage 232 to reduce or eliminate distortions (e.g., blocking artifacts). The decoder can, as described in Figure 2BApply the loop filter to the prediction reference 224 in the manner shown. The reference image for loop filtering can be stored in buffer 234 (e.g., the decoded picture buffer in a computer memory) for later use (e.g., as an inter-prediction reference picture for future coded pictures of the video bitstream 228). The decoder can store one or more reference pictures in buffer 234 for use at the temporal prediction stage 2044. In some embodiments, when the prediction mode indicator of the prediction data 206 indicates that inter-prediction is used to encode the current BPU, the prediction data can further include parameters of the loop filter (e.g., loop filter strength).

[0087] Figure 4 is a block diagram of an example apparatus 400 for encoding or decoding video according to an embodiment of the present disclosure. As Figure 4 shown, the apparatus 400 can include a processor 402. When the processor 402 executes the instructions described herein, the apparatus 400 can become a dedicated machine for video encoding or decoding. The processor 402 can be any type of circuit capable of manipulating or processing information. For example, the processor 402 can include any number of central processing units (or "CPUs"), graphics processing units (or "GPUs"), neural processing units ("NPUs"), microcontroller units ("MCUs"), optical processors, programmable logic controllers, microprocessors, digital signal processors, intellectual property (IP) cores, programmable logic arrays (PLAs), programmable array logic (PALs), generic array logic (GALs), complex programmable logic devices (CPLDs), a field programmable gate array (FPGA), a system on a chip (SoC), an application specific integrated circuit (ASIC), etc. in any combination. In some embodiments, the processor 402 can also be a group of processors grouped as a single logical component. For example, as Figure 4 shown, the processor 402 can include multiple processors, including processor 402a, processor 402b, and processor 402n.

[0088] The apparatus 400 can also include a memory 404 configured to store data (e.g., instruction sets, computer code, intermediate data, etc.). For example, as Figure 4As shown, the stored data may include program instructions (e.g., for implementing stages in processes 200A, 200B, 300A, or 300B) and data for processing (e.g., video sequence 202, video bitstream 228, or video stream 304). Processor 402 may access the program instructions and data for processing (e.g., via bus 410), and execute the program instructions to perform operations or manipulations on the data for processing. Memory 404 may include a high-speed random access storage device or a non-volatile storage device. In some embodiments, memory 404 may include any combination of any number of random access memories (RAMs), read-only memories (ROMs), optical discs, magnetic disks, hard disk drives, solid state drives, flash drives, secure digital (SD) cards, memory sticks, compact flash (CF) cards, etc. Memory 404 may also be a group of memories grouped as a single logical component ( Figure 4 not shown in

[0089] Bus 410 may be a communication device for transferring data between components inside device 400, such as an internal bus (e.g., CPU-memory bus), an external bus (e.g., universal serial bus port, peripheral component interconnect express port), or the like.

[0090] For ease of explanation without ambiguity, in this disclosure, processor 402 and other data processing circuits are collectively referred to as "data processing circuits". The data processing circuits may be implemented entirely in hardware, or as a combination of software, hardware, or firmware. Additionally, the data processing circuits may be a single separate module, or may be fully or partially combined into any other component of device 400.

[0091] Device 400 may also include network interface 406 to provide wired or wireless communication with a network (e.g., the Internet, an intranet, a local area network, a mobile communication network, etc.). In some embodiments, network interface 406 may include any combination of any number of network interface controllers (NICs), radio frequency (RF) modules, transponders, transceivers, modems, routers, gateways, wired network adapters, wireless network adapters, Bluetooth adapters, infrared adapters, near field communication ("NFC") adapters, cellular network chips, etc.

[0092] In some embodiments, optionally, device 400 may further include peripheral interface 408 to provide connection to one or more peripheral devices. As Figure 4 shown, the peripheral devices may include, but are not limited to, a cursor control device (e.g., a mouse, a touchpad, or a touchscreen), a keyboard, a display (e.g., a cathode ray tube display, a liquid crystal display, or a light emitting diode display), a video input device (e.g., a camera or an input interface coupled to a video archive), etc.

[0093] It should be noted that a video codec (e.g., the codec that executes processes 200A, 200B, 300A, or 300B) can be implemented as any combination of any software or hardware modules in device 400. For example, some or all stages of processes 200A, 200B, 300A, or 300B can be implemented as one or more software modules of device 400, such as program instances that can be loaded into memory 404. For another example, some or all stages of processes 200A, 200B, 300A, or 300B can be implemented as one or more hardware modules of device 400, such as dedicated data processing circuits (e.g., FPGA, ASIC, NPU, etc.).

[0094] During the VVC decoding process, an encoding tool called luminance mapping with chroma scaling (LMCS) is added as a new processing block before the loop filter. LMCS has two main components. One component is the in-loop mapping of the luminance component based on an adaptive piecewise linear model. The in-loop mapping of the luminance component adjusts the dynamic range of the input signal by redistributing codewords across the dynamic range to improve compression efficiency. The other component applies luminance-related chroma residual scaling to the chroma component. Chroma residual scaling aims to compensate for the interaction between the luminance signal and its corresponding chroma signal.

[0095] In VVC draft 8, signaling of the luminance mapping with chroma scaling (LMCS) can be controlled at the picture and slice levels. The LMCS syntax of the picture header and slice header is as shown in Figure 5 and Figure 6 respectively.

[0096] As shown in Figure 5 , when the picture-level LMCS flag ph_lmcs_enabled_flag is equal to 0, it indicates that both luminance mapping and chroma residual scaling are disabled for all slices associated with the picture. If ph_lmcs_enabled_flag is equal to 1 and ChromaArrayType is not equal to 0, an additional flag ph_chroma_residual_scale_flag is signaled. ph_chroma_residual_scale_flag specifies whether chroma residual scaling is used for decoding the picture.

[0097] As shown in Figure 6As shown, if the ph_lmcs_enabled_flag is equal to 1, the slice-level LMCS flag slice_lmcs_enabled_flag is signaled. The slice-level LMCS flag slice_lmcs_enabled_flag being equal to 1 specifies that luminance mapping is enabled for the slice associated with the slice header, and whether chroma scaling is used depends on the value of the ph_chroma_residual_scale_flag. If slice_lmcs_enabled_flag is equal to 1 and ph_chroma_residual_scale_flag is equal to 1, chroma residual scaling is enabled for the slice. If slice_lmcs_enabled_flag is equal to 1 and ph_chroma_residual_scale_flag is equal to 0, chroma residual scaling for the slice is disabled.

[0098] The slice-level LMCS flag slice_lmcs_enabled_flag being equal to 0 specifies that neither luminance mapping nor chroma residual scaling is enabled for the current slice.

[0099] A disadvantage of VVC Draft 8 is that if an image contains multiple slices, chroma residual scaling cannot be independently controlled for individual slices.

[0100] Specifically, using Figure 5 and Figure 6 the syntax shown, for all slices in a given image, whether residual scaling is used is consistent. In other words, residual scaling is either enabled for all slices or disabled for all slices. Consider an example where there are two slices in an image and LMCS is enabled for both slices. In this example, the following combinations are not supported:

[0101] Slice 1: Luminance mapping enabled (ON), chroma residual scaling disabled (OFF)

[0102] Slice 2: Luminance mapping enabled, chroma residual scaling enabled

[0103] Figure 7 Three examples of slice-level LMCS control are shown. Figure 7Examples A, B, and C are shown as follows. In all three examples, the values of sps_lmcs_enabled_flag, ph_lmcs_enabled_flag, and slice_lmcs_enabled_flag are equal to 1. In Example A, the picture-level chroma residual scaling flag is equal to 0, and in Example B, it is equal to 1. In Example A, since the picture-level ph_chroma_residual_scale_flag is equal to 0, the chroma residual scaling for both stripe 1 and stripe 2 is disabled. In Example B, since ph_chroma_residual_scale_flag is equal to 1, the chroma residual scaling for both stripes is in the ON state. In Example C, the chroma residual scaling for stripe 1 and 2 is OFF and ON, respectively. VVC Draft 8 allows Example A and Example B, but not Example C.

[0104] The present disclosure provides an LMCS method to address the above drawbacks.

[0105] In some embodiments, the (one or more) picture-level chroma residual scaling flags can be removed and replaced by stripe-level chroma residual scaling flags. The disclosed method allows enabling or disabling chroma residual scaling in a single stripe for which LMCS is enabled at the picture level. The semantic definition of the newly added stripe-level chroma residual scaling flag is as follows: slice_chroma_residual_scale_flag equal to 1 specifies that chroma residual scaling is enabled for the stripe; slice_chroma_residual_scale_flag equal to 0 specifies that chroma residual scaling is disabled for the stripe. When slice_chroma_residual_scale_flag does not exist, it is inferred to be equal to 0.

[0106] Figure 8 and Figure 9 respectively show the exemplary picture header syntax and slice header syntax of the above method. As shown in the picture header syntax of Figure 8 , the syntax element 301 (in VVC) is removed. As shown in the picture header syntax of Figure 9 , the syntax element 401 is modified from VVC.

[0107] Figure 10 shows a schematic diagram of the stripe-level control of luminance mapping and chroma residual scaling of the above exemplary method according to some embodiments of the present disclosure. Examples A, B, and C are as Figure 10As shown. For all three cases, the luminance mapping is ON. In Example A, the chroma residual scaling for both Strip 1 and Strip 2 is OFF. In Example B, for both Strip 1 and 2, the chroma residual scaling is ON. In Example C, the chroma residual coding for Strip 1 is OFF and the chroma residual scaling for Strip 2 is ON. Figure 8 and Figure 9 the syntax given in Figure 10 allows all three examples given in Figure 10 , while VVC Draft 8 only allows

[0108] Examples A and B in

[0109] In some embodiments, chroma residual scaling can be controlled both at the picture level and at the slice level. Similar to VVC Draft 8, ph_chroma_residual_scale_flag is signaled in the picture header. The semantic definition of ph_chroma_residual_scale_flag is as follows: ph_chroma_residual_scale_flag being equal to 1 specifies that chroma residual scaling can be enabled for one or more slices associated with the picture header; ph_chroma_residual_scale_flag being equal to 0 specifies that chroma residual scaling is disabled for all slices associated with the picture header. When ph_chroma_residual_scale_flag is absent, it is inferred to be equal to 0.

[0109] The syntax of the picture header and slice header is shown in Figures Figure 11 and Figure 12 respectively. As shown in Figure 11 , the PH-level syntax table is the same as that in VVC Draft 8. As shown by syntax element 601 in Figure 12 , slice_chroma_residual_scale_flag is signaled if all of the following conditions are met: slice_lmcs_enabled_flag is equal to 1; ChromaArrayType is not equal to 0; ph_chroma_residual_scale_flag is equal to 1.

[0110] The semantics of the slice-level chroma residual scaling flag are the same as above: slice_chroma_residual_scale_flag being equal to 1 specifies that chroma residual scaling is enabled for the slice; slice_chroma_residual_scale_flag being equal to 0 specifies that chroma residual scaling is disabled for the slice. When slice_chroma_residual_scale_flag is absent, it is inferred to be equal to 0.

[0111] Figure 11 andFigure 12 An advantage of the illustrated embodiment is that, in the case of turning off the chrominance residual scaling for all the stripes associated with the PH, there is no need to signal the stripe level flag, thus saving the signaling overhead.

[0112] The above embodiment shows that moving the LMCS syntax to the stripe level allows enabling and disabling chrominance residual scaling for each stripe, and thus improves the granularity level of LMCS control. According to the present disclosure, in some cases such as the embodiments described below, it is beneficial to move the control syntax for chrominance coding to the picture header.

[0113] In VVC draft 8, even if there is no chrominance color component in the picture, the chrominance deblocking parameters (e.g., β offset and tc offset) are signaled in the picture or in the stripe header. However, if there is no chrominance color component in the picture, there is no need to signal the chrominance deblocking parameters.

[0114] Embodiments of the present disclosure provide methods for processing video content by signaling the chrominance deblocking parameters.

[0115] In some embodiments, if the chrominance component exists in the video sequence (i.e., the video sequence is not monochrome), only the chrominance deblocking parameters are signaled. Figure 13 and Figure 14 respectively show an exemplary picture header syntax and a stripe header syntax for signaling the chrominance deblocking parameters. As Figure 13 and Figure 14 shown, the proposed changes to the syntax in VVC draft 8 are marked by the dashed boxes. These numbers indicate that the β offset and tc offset for Cb and Cr are signaled only when ChromaArrayType!= 0. The detailed definition of ChromaArrayType can be found in VVC draft 8, which is incorporated herein by reference.

[0116] In Figure 13 and Figure 14 the illustrated embodiments, the chrominance deblocking parameters of the PPS syntax are signaled only when ChromaArrayType is not equal to 0. Since the value of ChromaArrayType is available only after decoding the SPS syntax, the dependence on ChromaArrayType introduces an additional dependence on the SPS, which is not desirable. To avoid the SPS / PPS dependence, it is proposed to signal the separate_colour_plane_flag and chroma_format_idc not only in the SPS but also in the PPS. For example, two additional flags can be introduced, and their semantics are given below.

[0117] The flag pps_separate_colour_plane_flag being equal to 1 specifies that the three color components in the 4:4:4 chroma format are encoded separately. The flag pps_separate_colour_plane_flag being equal to 0 specifies that the color components are not encoded separately. The value of pps_separate_colour_plane_flag is equal to the value of separate_colour_plane_flag.

[0118] The parameter pps_chroma_format_idc specifies the chroma sampling relative to the luma sampling. The value of pps_chroma_format_idc is equal to the value of chroma_format_idc.

[0119] Depending on the value of pps_separate_colour_plane_flag, the value of the variable ChromaArrayType can be assigned as follows: If pps_separate_colour_plane_flag is equal to 0, then set ChromaArrayType to be equal to pps_chroma_format_idc; otherwise (pps_separate_colour_plane_flag is equal to 1), then set ChromaArrayType to be equal to 0.

[0120] Figure 15 An exemplary PPS syntax for signaling pps_separate_colour_plane_flag and pps_chroma_format_idc is shown. The syntax elements shown in the dashed box are the changes to the syntax in VVC Draft 8.

[0121] In some embodiments, in addition to signaling pps_separate_colour_plane_flag and pps_chroma_format_idc in the PPS, the signaling of pps_chroma_tool_offsets_present_flag can also be skipped. Figure 16 An exemplary PPS syntax without using pps_chroma_tool_offsets_present_flag is shown. The syntax elements shown in the dashed box are the changes to the syntax in VVC Draft 8.

[0122] In some embodiments, the PPS syntax pps_chroma_tool_offsets_present_flag may be replaced by pps_chroma_tool_present_flag. In these embodiments, if pps_chroma_tool_present_flag is equal to 1, all chroma-related syntaxes in the PPS are signaled. Similar to VVC Draft 8, separate_colour_plane_flag and chroma_format_idc are only signaled in the SPS and not signaled in the PPS.

[0123] The semantics of pps_chroma_tool_present_flag are given as follows: The flag pps_chroma_tool_present_flag being equal to 1 specifies that syntax elements related to chroma tools are present in the PPS raw byte sequence payload (RBSP) syntax structure; the flag pps_chroma_tool_present_flag being equal to 0 specifies that there are no syntax elements related to chroma tool offsets in the PPS RBSP syntax structure. When ChromaArrayType is equal to 0, the value of pps_chroma_tool_present_flag shall be equal to 0.

[0124] Figure 17 An exemplary PPS syntax using the proposed pps_chroma_tool_present_flag is shown. The syntax elements in the dashed box are the changes to the syntax in VVC Draft 8. It shows that if pps_chroma_tool_present_flag is not equal to 0, chroma-related syntax is signaled. Similar to VVC Draft 8, separate_colour_plane_flag and chroma_format_idc are only signaled in the SPS and not signaled in the PPS.

[0125] In some embodiments, signaling of slice-level chroma deblocking parameters such as slice_cb_beta_offset_div2, slice_cb_tc_offset_div2, slice_cr_beta_offset_div2, and slice_cb_beta_offset_div2 depends on the value of pps_chroma_tool_present_flag. If pps_chroma_tool_present_flag is equal to 0, then slice_cb_beta_offset_div2, slice_cb_tc_offset_div2, slice_cr_beta_offset_div2, and slice_cb_beta_offset_div2 are not signaled. If pps_chroma_tool_present_flag is equal to 1, then slice_cb_beta_offset_div2, slice_cb_tc_offset_div2, slice_cr_beta_offset_div2, or slice_cb_beta_offset_div2 is signaled.

[0126] In some embodiments, signaling of picture-level chroma deblocking parameters such as ph_cb_beta_offset_div2, ph_cb_tc_offset_div2, ph_cr_beta_offset_div2, ph_cb_beta_offset_div2, and ph_cb_beta_offset_div2 depends on the value of pps_chroma_tool_present_flag. If pps_chroma_tool_present_flag is equal to 0, then ph_cb_beta_offset_div2, ph_cb_tc_offset_div2, ph_cr_beta_offset_div2, and ph_cb_beta_offset_div2 are not signaled. If pps_chroma_tool_present_flag is equal to 1, then ph_cb_beta_offset_div2, ph_cb_tc_offset_div2, ph_cr_beta_offset_div2, or ph_cb_beta_offset_div2 is signaled.

[0127] Figure 18 is associated with Figures 5 to 12Flowchart of an exemplary method 1800 for signaling LMCS parameters consistent with the described embodiments. In some embodiments, method 1800 may be performed by a decoder and one or more software or hardware components of a device (e.g., Figure 4 device 400). For example, a processor (e.g., Figure 4 processor 402) may perform method 1800. In some embodiments, method 1800 may be implemented by a computer program product embodied in a computer-readable medium that includes computer-executable instructions, such as program code, executable by a computer (e.g., Figure 4 device 400). As Figure 18 shown, the method may include the following steps.

[0128] In step 1801, a bitstream including encoded video data is received. The bitstream includes at least one sequence parameter set (SPS).

[0129] In step 1803, based on the SPS-level chroma residual scaling flag (e.g., slice_chroma_residual_scale_flag) signaled in the received SPS, determine whether chroma residual scaling is enabled or disabled for a slice associated with the SPS. If the value of the flag is equal to 1, determine that chroma residual scaling is enabled for the slice. If the value of the flag is equal to 0, determine that chroma residual scaling for the slice is disabled.

[0130] Figure 19 is a flowchart of an exemplary method 1900 for signaling LMCS parameters consistent with the embodiments described in conjunction with Figures 5 - 12 In some embodiments, method 1900 may be performed by an encoder and one or more software or hardware components of a device (e.g., Figure 4 device 400). For example, a processor (e.g., Figure 4 processor 402) may perform method 1900. In some embodiments, method 1900 may be implemented by a computer program product embodied in a computer-readable medium that includes computer-executable instructions, such as program code, executable by a computer (e.g., Figure 4 device 400). As Figure 19 shown, method 1900 may include the following steps.

[0131] In step 1901, determine whether chroma residual scaling is enabled or disabled for a slice.

[0132] In step 1903, based on the determined result, a flag (e.g., slice_chroma_residual_scale_flag) is signaled in the sequence parameter set (SPS) associated with the slice to indicate whether chroma residual scaling is enabled or disabled for the slice. If chroma residual scaling is enabled for the slice, the value of the flag is set to 1. If chroma residual scaling is disabled for the slice, the value of the flag is set to 0.

[0133] Figure 20 is consistent with the embodiments described in conjunction with Figures 13 to 17 Exemplary method 2000 for signaling chroma deblocking parameters. In some embodiments, method 2000 may be performed by one or more software or hardware components of an encoder, a decoder, and a device (e.g., Figure 4 device 400). For example, a processor (e.g., Figure 4 processor 402) may perform method 2000. In some embodiments, method 2000 may be implemented by a computer program product included in a computer-readable medium, the computer program product including computer-executable instructions, such as program code, executed by a computer (e.g., Figure 4 device 400). As Figure 20 shown, method 2000 may include the following steps.

[0134] In step 2001, determine whether the video sequence is monochrome.

[0135] In step 2003, if the video sequence is not monochrome, determine to signal chroma deblocking parameters in the bitstream associated with the video sequence; and if the video sequence is monochrome, determine not to signal chroma deblocking parameters in the bitstream.

[0136] The embodiments may be further described using the following clauses:

[0137] 1. A computer-implemented video decoding method, comprising:

[0138] Receiving a sequence parameter set (SPS); and

[0139] Based on a first flag signaled in the SPS, determining whether chroma residual scaling is enabled or disabled for a slice associated with the SPS.

[0140] 2. The method according to clause 1, further comprising:

[0141] In response to the value of the first flag being equal to 1, determining that chroma residual scaling is enabled for the slice.

[0142] 3. The method according to any one of clauses 1 and 2, further comprising:

[0143] In response to the value of the first flag being equal to 0, determine to disable the chrominance residual scaling for the strip.

[0144] 4. The method according to any one of clauses 1-3, further comprising:

[0145] Receiving a second SPS; and

[0146] When the first flag does not exist in the second SPS, determine to disable the chrominance residual scaling for the strip associated with the second SPS.

[0147] 5. The method according to any one of clauses 1-4, wherein the first flag is signaled based on a second flag signaled in an image header associated with the strip.

[0148] 6. The method according to clause 5, wherein:

[0149] A first value of the second flag indicates enabling the chrominance residual scaling for one or more strips associated with the image header; and

[0150] A second value of the second flag indicates disabling the chrominance residual scaling for all strips associated with the image header.

[0151] 7. The method according to any one of clauses 1-4, comprising:

[0152] Receiving an image header; and

[0153] In response to a second flag having a first value signaled in the image header, determine to disable the chrominance residual scaling for all strips associated with the image header.

[0154] 8. The method according to any one of clauses 1-4, comprising:

[0155] Based on a second flag signaled in the SPS, determine whether to enable or disable luminance mapping for the strip.

[0156] 9. A computer-implemented video encoding method, comprising:

[0157] Signaling a first flag in a sequence parameter set (SPS) associated with a strip, the first flag indicating whether to enable or disable chrominance residual scaling for the strip.

[0158] 10. The method according to clause 9, comprising:

[0159] In response to enabling the chrominance residual scaling for the strip, set the value of the first flag to 1.

[0160] 11. The method according to any one of clauses 9 and 10, comprising:

[0161] Setting the value of the first flag to 0 in response to disabling the chrominance residual scaling for the strip.

[0162] 12. The method according to any one of clauses 9 - 11, further comprising:

[0163] In an image header, signaling a second flag that indicates whether the chrominance residual scaling is enabled for an image associated with the image header.

[0164] 13. The method according to clause 12, wherein the strip is part of the image, and the signaling of the first flag is in response to the value of the second flag being equal to 1, and if the value of the second flag is equal to 0, the first flag is not signaled in the SPS.

[0165] 14. The method according to any one of clauses 9 - 11, further comprising:

[0166] In the SPS, signaling a second flag that indicates whether luminance mapping is enabled or disabled for the strip.

[0167] 15. A video decoder, comprising:

[0168] A memory for storing an instruction set; and

[0169] At least one processor configured to execute the instruction set to cause the system to:

[0170] Receive a sequence parameter set (SPS); and

[0171] Based on a first flag signaled in the SPS, determine whether chrominance residual scaling is enabled or disabled for a strip associated with the SPS.

[0172] 16. The video decoder according to clause 15, wherein the at least one processor is configured to execute the instruction set to cause the system to:

[0173] In response to the value of the first flag being equal to 1, determine that the chrominance residual scaling is enabled for the strip.

[0174] 17. The video decoder according to any one of clauses 15 and 16, wherein the at least one processor is configured to execute the instruction set to cause the system to:

[0175] In response to the value of the first flag being equal to 0, determine to disable the chrominance residual scaling for the strip.

[0176] 18. The video decoder according to any one of clauses 15 - 17, wherein the at least one processor is configured to execute the instruction set to cause the system to perform:

[0177] Receive a second SPS; and

[0178] When the first flag does not exist in the second SPS, determine to disable the chrominance residual scaling for the strip associated with the second SPS.

[0179] 19. The video decoder according to any one of clauses 15 - 18, wherein the first flag is signaled based on a second flag signaled in an image header associated with the strip.

[0180] 20. The video decoder according to clause 19, wherein:

[0181] A first value of the second flag indicates enabling the chrominance residual scaling for one or more strips associated with the image header; and

[0182] A second value of the second flag indicates disabling the chrominance residual scaling for all strips associated with the image header.

[0183] 21. The video decoder according to any one of clauses 15 - 18, wherein the at least one processor is configured to execute the instruction set to cause the system to perform:

[0184] Receive an image header; and

[0185] In response to the second flag having a first value signaled in the image header, determine to disable the chrominance residual scaling for all strips associated with the image header.

[0186] 22. The video decoder according to any one of clauses 15 - 18, wherein the at least one processor is configured to execute the instruction set to cause the system to perform:

[0187] Based on a second flag signaled in the SPS, determine whether to enable or disable luminance mapping for the strip.

[0188] 23. A video encoder, comprising:

[0189] A memory for storing an instruction set; and

[0190] At least one processor, which is configured to execute the instruction set to cause the system to perform:

[0191] Signal a first flag in a sequence parameter set (SPS) associated with a slice, the first flag indicating whether chrominance residual scaling is enabled or disabled for the slice.

[0192] 24. The video encoder according to clause 23, wherein the at least one processor is configured to execute the instruction set to cause the system to perform:

[0193] In response to enabling the chrominance residual scaling for the slice, set the value of the first flag to 1.

[0194] 25. The video encoder according to any one of clauses 23 and 24, wherein the at least one processor is configured to execute the instruction set to cause the system to perform:

[0195] In response to disabling the chrominance residual scaling for the slice, set the value of the first flag to 0.

[0196] 26. The video encoder according to any one of clauses 23 - 25, wherein the at least one processor is configured to execute the instruction set to cause the system to perform:

[0197] In an image header, signal a second flag, the second flag indicating whether chrominance residual scaling is enabled for an image associated with the image header.

[0198] 27. The video encoder according to clause 26, wherein the slice is part of the image, and the signaling of the first flag is in response to the value of the second flag being equal to 1, and if the value of the second flag is equal to 0, the first flag is not signaled in the SPS.

[0199] 28. The video encoder according to any one of clauses 23 - 25, wherein the at least one processor is configured to execute the instruction set to cause the system to perform:

[0200] In the SPS, signal a second flag, the second flag indicating whether luminance mapping is enabled or disabled for the slice.

[0201] 29. A non - transitory computer - readable medium storing an instruction set executable by at least one processor of a computer system to cause the computer system to perform a method for decoding video content, the method comprising:

[0202] Receive a sequence parameter set (SPS); and

[0203] Based on a first flag signaled in the SPS, determine whether chrominance residual scaling is enabled or disabled for a slice associated with the SPS.

[0204] 30. The non - transitory computer - readable medium according to clause 29, wherein the instruction set further causes the at least one processor to execute:

[0205] In response to the value of the first flag being equal to 1, determine that chrominance residual scaling is enabled for the stripe.

[0206] 31. The non - transitory computer - readable medium according to any one of clauses 29 and 30, wherein the instruction set further causes the at least one processor to execute:

[0207] In response to the value of the first flag being equal to 0, determine that chrominance residual scaling is disabled for the stripe.

[0208] 32. The non - transitory computer - readable medium according to any one of clauses 29 - 31, wherein the instruction set further causes the at least one processor to execute:

[0209] Receive a second SPS; and

[0210] When the first flag does not exist in the second SPS, determine that chrominance residual scaling is disabled for the stripes associated with the second SPS.

[0211] 33. The non - transitory computer - readable medium according to any one of clauses 29 - 32, wherein the first flag is signaled based on a second flag signaled in an image header associated with the stripe.

[0212] 34. The non - transitory computer - readable medium according to clause 33, wherein:

[0213] A first value of the second flag indicates that chrominance residual scaling is enabled for one or more stripes associated with the image header; and

[0214] A second value of the second flag indicates that chrominance residual scaling is disabled for all stripes associated with the image header.

[0215] 35. The non - transitory computer - readable medium according to any one of clauses 29 - 32, wherein the instruction set further causes the at least one processor to execute:

[0216] Receive an image header; and

[0217] In response to a second flag having a first value signaled in the image header, determine that chrominance residual scaling is disabled for all stripes associated with the image header.

[0218] 36. The non - transitory computer - readable medium according to any one of clauses 29 - 32, wherein the instruction set further causes the at least one processor to perform:

[0219] Determine whether to enable or disable luminance mapping for the strip based on a second flag signaled in the SPS.

[0220] 37. A non - transitory computer - readable medium storing an instruction set executable by at least one processor of a computer system to cause the computer system to perform a method for encoding video content, the method comprising:

[0221] Signal a first flag in a sequence parameter set (SPS) associated with a strip, the first flag indicating whether to enable or disable chrominance residual scaling for the strip.

[0222] 38. The non - transitory computer - readable medium according to clause 37, wherein the instruction set further causes the at least one processor to perform:

[0223] In response to enabling the chrominance residual scaling for the strip, set the value of the first flag to 1.

[0224] 39. The non - transitory computer - readable medium according to any one of clauses 37 and 38, wherein the instruction set further causes the at least one processor to perform:

[0225] In response to disabling the chrominance residual scaling for the strip, set the value of the first flag to 0.

[0226] 40. The non - transitory computer - readable medium according to any one of clauses 37 - 39, wherein the instruction set further causes the at least one processor to perform:

[0227] In an image header, signal a second flag that indicates whether to enable the chrominance residual scaling for an image associated with the image header.

[0228] 41. The non - transitory computer - readable medium according to clause 40, wherein the strip is part of the image, and the signaling of the first flag is in response to the value of the second flag being equal to 1, and if the value of the second flag is equal to 0, the first flag is not signaled in the SPS.

[0229] 42. The non - transitory computer - readable medium according to any one of clauses 37 - 39, wherein the instruction set further causes the at least one processor to perform:

[0230] In the SPS, a second flag is signaled, the second flag indicating whether luminance mapping is enabled or disabled for the slice.

[0231] 43. A computer-implemented video content processing method, comprising:

[0232] Determining whether a video sequence is monochrome; and

[0233] In response to determining that the video sequence is not monochrome, signaling chroma deblocking parameters in a bitstream associated with the video sequence,

[0234] wherein when the video sequence is monochrome, the chroma deblocking parameters are not signaled in the bitstream.

[0235] 44. The method according to clause 43, wherein the chroma deblocking parameters are signaled in an image header.

[0236] 45. The method according to any one of clauses 43 and 44, wherein the chroma deblocking parameters are signaled in a slice header.

[0237] 46. The method according to any one of clauses 43-45, wherein it is determined whether the video sequence is monochrome based on the value of ChromaArrayType.

[0238] 47. The method according to clause 46, further comprising:

[0239] In a picture parameter set (PPS) associated with the video sequence, signaling a first flag indicating whether the video sequence includes multiple separately encoded color components, and a second flag indicating information about chroma sampling relative to luma sampling.

[0240] 48. The method according to clause 47, further comprising:

[0241] In response to the value of the first flag being equal to 0, setting ChromaArrayType to be equal to the value of the second flag.

[0242] 49. The method according to clause 47, further comprising:

[0243] In response to the value of the first flag being equal to 1, setting ChromaArrayType to be equal to 0.

[0244] 50. The method according to any one of clauses 43-49, further comprising:

[0245] In a PPS associated with the video sequence, signaling a flag indicating that the PPS raw byte sequence payload (RBSP) syntax structure includes chroma tool-related syntax.

[0246] 51. The method according to clause 50, wherein the flag is pps_chroma_tool_present_flag.

[0247] 52. The method according to clause 51, further comprising:

[0248] In response to the pps_chroma_tool_present_flag being equal to 1, signaling one or more slice-level chroma deblocking parameters,

[0249] wherein when the pps_chroma_tool_present_flag is equal to 0, the slice-level chroma deblocking parameters are not signaled.

[0250] 53. The method according to clause 52, wherein the one or more slice-level chroma deblocking parameters include:

[0251] slice_cb_beta_offset_div2, slice_cb_tc_offset_div2,

[0252] slice_cr_beta_offset_div2 or slice_cb_beta_offset_div2.

[0253] 54. The method according to clause 51, further comprising:

[0254] In response to the pps_chroma_tool_present_flag being equal to 1, signaling one or more picture-level chroma deblocking parameters,

[0255] wherein when the pps_chroma_tool_present_flag is equal to 0, the picture-level chroma deblocking parameters are not signaled.

[0256] 55. The method according to clause 54, wherein the one or more picture-level chroma deblocking parameters include:

[0257] ph_cb_beta_offset_div2, ph_cb_tc_offset_div2, ph_cr_beta_offset_div2, and ph_cb_beta_offset_div2.

[0258] 56. An apparatus, comprising:

[0259] A memory for storing an instruction set; and

[0260] At least one processor configured to execute the instruction set to cause the system to perform:

[0261] Determine whether the video sequence is monochrome; and

[0262] In response to determining that the video sequence is not monochrome, signal chroma deblocking parameters in a bitstream associated with the video sequence,

[0263] wherein when the video sequence is monochrome, chroma deblocking parameters are not signaled in the bitstream.

[0264] 57. The apparatus according to clause 51, wherein the at least one processor is configured to execute the instruction set to cause the system to perform:

[0265] Signal the chroma deblocking parameters in an image header.

[0266] 58. The apparatus according to any one of clauses 51 and 52, wherein the at least one processor is configured to execute the instruction set to cause the system to perform:

[0267] Signal the chroma deblocking parameters in a slice header.

[0268] 59. The apparatus according to any one of clauses 51 - 53, wherein it is determined whether the video sequence is monochrome based on the value of ChromaArrayType.

[0269] 60. The apparatus according to clause 54, wherein the at least one processor is configured to execute the instruction set to cause the system to perform:

[0270] In a Picture Parameter Set (PPS) associated with the video sequence, signal a first flag indicating whether the video sequence includes multiple separately encoded color components, and a second flag indicating information about chroma sampling relative to luma sampling.

[0271] 61. The apparatus according to clause 55, wherein the at least one processor is configured to execute the instruction set to cause the system to perform:

[0272] In response to the value of the first flag being equal to 0, set ChromaArrayType to be equal to the value of the second flag.

[0273] 62. The apparatus according to clause 55, wherein the at least one processor is configured to execute the instruction set to cause the system to perform:

[0274] In response to the value of the first flag being equal to 1, set ChromaArrayType to be equal to 0.

[0275] 63. The apparatus according to any one of clauses 51 - 57, wherein the at least one processor is configured to execute the instruction set to cause the system to perform:

[0276] In the PPS associated with the video sequence, signal a flag that indicates that the PPS raw byte sequence payload (RBSP) syntax structure includes chroma tool - related syntax.

[0277] 64. The apparatus according to clause 63, wherein the flag is pps_chroma_tool_present_flag.

[0278] 65. The apparatus according to clause 64, wherein the at least one processor is configured to execute the instruction set to cause the system to perform:

[0279] In response to the pps_chroma_tool_present_flag being equal to 1, signal one or more slice - level chroma deblocking parameters,

[0280] wherein when the pps_chroma_tool_present_flag is equal to 0, the slice - level chroma deblocking parameters are not signaled.

[0281] 66. The apparatus according to clause 65, wherein the one or more slice - level chroma deblocking parameters include:

[0282] slice_cb_beta_offset_div2, slice_cb_tc_offset_div2,

[0283] slice_cr_beta_offset_div2 or slice_cb_beta_offset_div2.

[0284] 67. The apparatus according to clause 64, wherein the at least one processor is configured to execute the instruction set to cause the system to perform:

[0285] In response to pps_chroma_tool_present_flag being equal to 1, signal one or more picture - level chroma deblocking parameters,

[0286] wherein when pps_chroma_tool_present_flag is equal to 0, the picture - level chroma deblocking parameters are not signaled.

[0287] 68. The apparatus according to clause 67, wherein the one or more picture - level deblocking parameters include:

[0288] ph_cb_beta_offset_div2, ph_cb_tc_offset_div2, ph_cr_beta_offset_div2, and ph_cb_beta_offset_div2.

[0289] 69. A non - transitory computer - readable medium storing an instruction set executable by at least one processor of a computer system to cause the computer system to perform a method, the method comprising:

[0290] Determining whether a video sequence is monochrome; and

[0291] In response to determining that the video sequence is not monochrome, signaling chroma de - blocking parameters in a bitstream associated with the video sequence,

[0292] wherein when the video sequence is monochrome, the chroma de - blocking parameters are not signaled in the bitstream.

[0293] 70. The non - transitory computer - readable medium according to clause 59, wherein the instruction set further causes the at least one processor to perform:

[0294] Signaling the chroma de - blocking parameters in an image header.

[0295] 71. The non - transitory computer - readable medium according to any one of clauses 59 and 60, wherein the instruction set further causes the at least one processor to perform:

[0296] Signaling the chroma de - blocking parameters in a slice header.

[0297] 72. The non - transitory computer - readable medium according to any one of clauses 59 - 61, wherein it is determined whether the video sequence is monochrome based on the value of ChromaArrayType.

[0298] 73. The non - transitory computer - readable medium according to clause 62, wherein the instruction set further causes the at least one processor to perform:

[0299] In a picture parameter set (PPS) associated with the video sequence, signaling a first flag indicating whether the video sequence includes multiple separately - encoded color components and a second flag indicating information about chroma sampling relative to luma sampling.

[0300] 74. The non - transitory computer - readable medium according to clause 63, wherein the instruction set further causes the at least one processor to perform:

[0301] In response to the value of the first flag being equal to 0, set ChromaArrayType to be equal to the value of the second flag.

[0302] 75. The non - transitory computer - readable medium according to clause 63, wherein the instruction set further causes the at least one processor to execute:

[0303] In response to the value of the first flag being equal to 1, set ChromaArrayType to be equal to 0.

[0304] 76. The non - transitory computer - readable medium according to any one of clauses 59 - 65, wherein the instruction set further causes the at least one processor to execute:

[0305] In the PPS associated with the video sequence, signal a flag that indicates that the PPS raw byte sequence payload (RBSP) syntax structure includes chroma tool - related syntax.

[0306] 77. The non - transitory computer - readable medium according to clause 76, wherein the flag is pps_chroma_tool_present_flag.

[0307] 78. The non - transitory computer - readable medium according to clause 77, wherein the instruction set further causes the at least one processor to execute:

[0308] In response to the pps_chroma_tool_present_flag being equal to 1, signal one or more slice - level chroma de - blocking parameters,

[0309] wherein when the pps_chroma_tool_present_flag is equal to 0, do not signal the slice - level chroma de - blocking parameters.

[0310] 79. The non - transitory computer - readable medium according to clause 78, wherein the one or more slice - level chroma de - blocking parameters include:

[0311] slice_cb_beta_offset_div2, slice_cb_tc_offset_div2,

[0312] slice_cr_beta_offset_div2 or slice_cb_beta_offset_div2.

[0313] 80. The non - transitory computer - readable medium according to clause 77, wherein the instruction set further causes the at least one processor to execute:

[0314] In response to pps_chroma_tool_present_flag being equal to 1, signal one or more picture level chroma deblocking parameters,

[0315] wherein, when pps_chroma_tool_present_flag is equal to 0, do not signal picture level chroma deblocking parameters.

[0316] 81. The non-transitory computer-readable medium according to clause 80, wherein the one or more picture level chroma deblocking parameters include:

[0317] ph_cb_beta_offset_div2, ph_cb_tc_offset_div2, ph_cr_beta_offset_div2, and ph_cb_beta_offset_div2.

[0318] In some embodiments, a non-transitory computer-readable storage medium including instructions is also provided, and the instructions can be executed by a device (such as the disclosed encoder and decoder) to perform the above method. Common forms of non-transitory media include, for example, floppy disks, hard disks, solid state drives, magnetic tapes, or any other magnetic data storage medium, CD-ROMs, any other optical data storage medium, any physical medium with a hole pattern, RAM, PROM, and EPROM, FLASH-EPROM, or any other flash memory, NVRAM, caches, registers, any other storage chip or cartridge storage, and their networked versions. The device may include one or more processors (CPUs), input / output interfaces, network interfaces, and / or memories.

[0319] It should be noted that relational terms such as "first" and "second" herein are only used to distinguish one entity or operation from another entity or operation, and do not require or imply any actual relationship or order between these entities or operations. In addition, the words "comprise", "have", "include", and "contain" and other similar forms are equivalent in meaning and are open-ended, because one or more items following any of these words do not mean an exhaustive list of such one or more items, or are limited to the listed one or more items.

[0320] As used herein, unless otherwise specifically stated, the term "or" includes all possible combinations, unless infeasible. For example, if it is stated that a database may include A or B, then the database may include A, or B, or A and B, unless otherwise clearly stated or infeasible. As a second example, if it is stated that a database may include A, B, or C, then the database may include A, or B, or C, or A and B, or A and C, or B and C, or A, B, and C, unless otherwise clearly stated or infeasible.

[0321] It should be understood that the above embodiments can be implemented by hardware, or software (program code), or a combination of hardware and software. If implemented by software, it can be stored in the above computer-readable medium. The software can execute the disclosed method when executed by a processor. The computing units and other functional units described in the present disclosure can be implemented by hardware, or software, or a combination of hardware and software. Those of ordinary skill in the art will also understand that the above multiple modules / units can be combined into one module / unit, and each of the above modules / units can be further divided into multiple sub-modules / sub-units.

[0322] In the foregoing specification, embodiments have been described with reference to numerous specific details, which may vary with the implementation. Certain modifications and changes can be made to the described embodiments. Other embodiments will be apparent to those skilled in the art by considering the specification and practice of the invention disclosed herein. The specification and embodiments are considered to be exemplary only, and the true scope and spirit of the invention are indicated by the appended claims. The sequence of steps shown in the drawings is for illustrative purposes only and is not intended to be limited to any particular sequence of steps. Thus, those skilled in the art will understand that these steps can be executed in a different order while implementing the same method.

[0323] In the drawings and the specification, exemplary embodiments have been disclosed. However, many variations and modifications can be made to these embodiments. Therefore, although specific terms are employed, they are used in a general and descriptive sense only and not for purposes of limitation.

Claims

1. A computer-implemented decoding method, comprising: determining a value signaled for pps_chroma_tool_offsets_present_flag in a picture parameter set (PPS) associated with a video sequence; and in response to pps_chroma_tool_offsets_present_flag being equal to 1, decoding one or more picture-level chroma deblocking parameters in a bitstream associated with the video sequence, wherein, when pps_chroma_tool_offsets_present_flag is equal to 0, picture-level chroma deblocking parameters are not signaled in the bitstream, and wherein the one or more picture-level chroma deblocking parameters include at least one of beta_offset or tc_offset.

2. The method according to claim 1, wherein the one or more picture-level chroma deblocking parameters include: ph_cb_beta_offset_div2, ph_cb_tc_offset_div2, ph_cr_beta_offset_div2, or ph_cr_tc_beta_offset_div2.

3. A non-transitory computer-readable medium storing a bitstream generated by executing a computer program, the computer program when executed causing a computer to perform the following method: determining a value signaled for pps_chroma_tool_offsets_present_flag in a picture parameter set (PPS) associated with a video sequence; and in response to pps_chroma_tool_offsets_present_flag being equal to 1, signaling one or more picture-level chroma deblocking parameters in a bitstream associated with the video sequence, wherein when pps_chroma_tool_offsets_present_flag is equal to 0, picture-level chroma deblocking parameters are not signaled in the bitstream, and wherein the one or more picture-level chroma deblocking parameters include at least one of beta_offset or tc_offset.

4. The non-transitory computer-readable medium according to claim 3, wherein the one or more picture-level chroma deblocking parameters include: ph_cb_beta_offset_div2, ph_cb_tc_offset_div2, ph_cr_beta_offset_div2, or ph_cr_tc_offset_div2.

5. A computer-implemented encoding method, comprising: determining a value signaled for pps_chroma_tool_offsets_present_flag in a picture parameter set (PPS) associated with a video sequence; and In response to pps_chroma_tool_offsets_present_flag being equal to 1, one or more picture-level chroma deblocking parameters are signaled in the bitstream associated with the video sequence, wherein when pps_chroma_tool_offsets_present_flag is equal to 0, the picture-level chroma deblocking parameters are not signaled in the bitstream, and wherein the one or more picture-level chroma deblocking parameters include at least one of beta_offset or tc_offset.

6. The method according to claim 5, wherein, the chroma deblocking parameters are signaled in the picture header.

7. The method according to claim 5, wherein, the one or more picture-level chroma deblocking parameters include: ph_cb_beta_offset_div2, ph_cb_tc_offset_div2, ph_cr_beta_offset_div2, or ph_cr_tc_offset_div2.

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