printed wiring board

Abstract

The printed wiring board disclosed in the present invention comprises: a substrate layer having insulating properties; a first conductive layer directly or indirectly laminated on the surface of the substrate layer and comprising copper foil; a second conductive layer directly or indirectly laminated on the back surface of the substrate layer and comprising copper foil; and a through-hole laminated on the inner periphery and bottom of a connection hole penetrating the first conductive layer and the substrate layer in the thickness direction and electrically connecting the first conductive layer and the second conductive layer, the through-hole laminate comprising an electroless copper plating layer laminated on the inner periphery and bottom of the connection hole and an electrolytic copper plating layer laminated on the surface of the electroless copper plating layer, the copper foil containing copper grains oriented along the (100) plane direction, the average grain size of the copper in the copper foil being 10 μm or more, the electroless copper plating layer containing palladium, and the amount of palladium laminated per unit area of ​​the copper foil surface being 0.03 μg / cm 2 Above and 0.15 μg / cm 2 the following.

Description

Technical Field

[0001] The present disclosure relates to a printed wiring board. Background Art

[0002] In recent years, the miniaturization of electronic devices has continued to develop, requiring high-density wiring of printed wiring boards used in electronic devices. In response to such demands, multilayer printed wiring boards having multiple patterned conductive layers are mostly used. In order to connect the patterns of different conductive layers in a multilayer printed wiring board, for example, a through hole is provided that penetrates a substrate layer having a metal foil laminated as a conductive layer on the front and back sides. The through hole is formed with an electroless copper plating layer and an electrolytic copper plating layer on the inner peripheral surface of the hole that penetrates the above-mentioned substrate layer. (See Japanese Patent Application Publication No. 2004-214410).

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Laid-Open No. 2004-214410 Summary of the Invention

[0006] The printed wiring board disclosed in the present invention comprises: a substrate layer having insulating properties; a first conductive layer directly or indirectly laminated on the surface of the substrate layer and comprising copper foil; a second conductive layer directly or indirectly laminated on the back surface of the substrate layer and comprising copper foil; and a through-hole laminated on the inner periphery and bottom of a connection hole penetrating the first conductive layer and the substrate layer in the thickness direction and electrically connecting the first conductive layer and the second conductive layer, the through-hole laminate comprising an electroless copper plating layer laminated on the inner periphery and bottom of the connection hole and an electrolytic copper plating layer laminated on the surface of the electroless copper plating layer, the copper foil containing copper grains oriented along the (100) plane direction, the average grain size of the copper in the copper foil being 10 μm or more, the electroless copper plating layer containing palladium, and the amount of palladium laminated per unit area of ​​the copper foil surface being 0.03 μg / cm 2 Above and 0.15 μg / cm 2 the following. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 This is a schematic cross-sectional view showing a printed wiring board according to one embodiment.

[0008] Figure 2 It shows Figure 1 Schematic perspective view of a connection hole of a printed wiring board. DETAILED DESCRIPTION

[0009] [Technical Problems to be Solved by the Present Disclosure]

[0010] Copper foil is generally widely used as the wiring layer of the above-mentioned through-hole. For this copper foil, it is required to further improve the mechanical properties such as bendability. For example, in order to improve the mechanical properties of copper foil, research has been conducted on the orientation of copper crystals, grain size, etc. However, when the surface of a copper foil having a crystal orientation and grain size within a specific range is subjected to electroless copper plating and then electroplated with copper, the copper crystals of the electrolytic copper plating layer sometimes grow abnormally locally. If the copper crystals grow abnormally locally in this way, unevenness will be generated on the surface of the electrolytic copper plating layer, and thus, when an automatic optical inspection device (AOI: Automated Optical Inspection system) is used for appearance inspection, it will sometimes be mistakenly detected as defective. In addition, since a large amount of copper is precipitated on the convex portion generated on the surface of the electrolytic copper plating layer, copper is not sufficiently precipitated at the bottom of the through-hole. As a result, there is a concern that the bottom of the through-hole will peel off from the conductive layer.

[0011] The present disclosure has been made based on the above-described circumstances, and an object of the present disclosure is to provide a printed wiring board capable of suppressing erroneous detection and peeling of the bottom of a through hole during appearance inspection using an automatic optical inspection device.

[0012] [Effects of the Present Disclosure]

[0013] According to the present disclosure, it is possible to provide a printed wiring board capable of suppressing erroneous detection during appearance inspection and peeling of the bottom of a through hole.

[0014] [Description of Embodiments of the Present Disclosure]

[0015] First, embodiments of the present disclosure are described in an enumerated manner.

[0016] The printed wiring board disclosed in the present invention comprises: a substrate layer having insulating properties; a first conductive layer directly or indirectly laminated on the surface of the substrate layer and comprising copper foil; a second conductive layer directly or indirectly laminated on the back surface of the substrate layer and comprising copper foil; and a through-hole laminated on the inner periphery and bottom of a connection hole penetrating the first conductive layer and the substrate layer in the thickness direction and electrically connecting the first conductive layer and the second conductive layer, the through-hole laminate comprising an electroless copper plating layer laminated on the inner periphery and bottom of the connection hole and an electrolytic copper plating layer laminated on the surface of the electroless copper plating layer, the copper foil containing copper grains oriented along the (100) plane direction, the average grain size of the copper in the copper foil being 10 μm or more, the electroless copper plating layer containing palladium, and the amount of palladium laminated per unit area of ​​the copper foil surface being 0.03 μg / cm 2 Above and 0.15 μg / cm 2 the following.

[0017] The copper foil laminated on the surface of the substrate layer of a printed wiring board contains copper grains oriented in the (100) plane direction, and the average grain diameter of the copper is 10 μm or more. In this case, the orientation of the copper grains of the copper foil is easily inherited by the copper grains precipitated by electroless copper plating and the copper grains precipitated by electrolytic copper plating. As a result, an electroless copper plating layer and an electrolytic copper plating layer having the same orientation as the copper grains of the copper foil are formed. In addition, there is a concern that the copper crystals of the electrolytic copper plating layer may grow abnormally locally and produce unevenness on the surface of the electrolytic copper plating layer. In this printed wiring board, since the electroless copper plating layer contains palladium, especially near the interface with the conductive layer below it, the orientation of the copper grains of the copper foil is suppressed from being inherited by the copper grains precipitated by electroless copper plating. As a result, the formation of unevenness on the surface of the electrolytic copper plating layer due to the abnormal growth of the copper crystals of the electrolytic copper plating layer is suppressed. Therefore, this printed wiring board can suppress erroneous detection during appearance inspection using an automatic optical inspection device and peeling of the bottom of the through hole. In addition, in this printed wiring board, the amount of palladium laminated per unit area on the surface of the copper foil is 0.03 μg / cm 2 Above and 0.15 μg / cm 2 As a result, the amount of catalyst nuclei generated by electroless copper plating increases, promoting the growth of plating with a different orientation from the copper grains of the copper foil. As a result, the inhibitory effect on the formation of an electroless copper plating layer having the same orientation as the copper grains of the copper foil can be improved. Therefore, the inhibitory effect on false detection during appearance inspection using an automatic optical inspection device and peeling at the bottom of the through-hole can be improved. The palladium-containing catalyst of the present application is in the form of an aqueous solution containing palladium ions, and does not include colloidal solutions such as tin-palladium solutions. Therefore, in the printed wiring board disclosed in the present invention, tin is not included in the electroless copper plating layer.

[0018] Here, "grain diameter" refers to, for example, the detection of grain boundaries by performing crystal orientation analysis on the surface of the copper foil serving as a sample using the EBSD (Electron Backscatter Diffraction) method, defining the area surrounded by the grain boundary as a grain, and taking the diameter of a circle having the same area as the area of ​​the area as the grain diameter of each grain. Furthermore, "average grain diameter" refers to the average value of the grain diameters of each grain present in a prescribed measurement field of view. In addition, the surface orientation of the copper grains of the copper foil is calculated by performing multiple measurements on randomly extracted portions of the copper foil surface using the EBSD method. "Average thickness" refers to the average value of the thicknesses measured at any 10 points.

[0019] In this printed wiring board, the ratio of the area of ​​copper crystal grains oriented in the (100) plane on the surface of the copper foil relative to the area of ​​the copper foil surface is preferably 50% or more. Since the ratio of the area of ​​copper crystal grains oriented in the (100) plane on the surface of the copper foil relative to the area of ​​the copper foil surface is 50% or more, the effect of suppressing local abnormal growth of copper crystals in the electrolytic copper plating layer is improved.

[0020] Here, the “area ratio of copper crystal grains oriented in the (100) plane direction” refers to the ratio of the area of ​​the copper crystal grains oriented in the (100) plane direction to the area of ​​the entire copper foil surface.

[0021] The amount of palladium deposited per unit area on the copper foil surface is preferably 0.05 μg / cm 2 Above and 0.10 μg / cm 2 Since the palladium layer is within the above range, the amount of catalyst nuclei generated by the electroless copper plating is within an appropriate range. As a result, it is believed that it is more difficult to form an electroless copper plating layer and an electrolytic copper plating layer having the same orientation as the copper grains of the copper foil.

[0022] The ratio of the area of ​​copper crystal grains oriented along the (100) plane on the surface of the copper foil to the area of ​​the copper foil surface is preferably 60% or greater. When the ratio of the area of ​​copper crystal grains oriented along the (100) plane on the surface of the copper foil is within the above range, the effect of suppressing local abnormal growth of copper crystals in the electrolytic copper plating layer is enhanced.

[0023] The average thickness of the electroless copper plating layer is preferably from 0.01 μm to 1.0 μm. Since the average thickness of the electroless copper plating layer is within the above range, the electrolytic copper plating layer can be uniformly formed, and the orientation of the copper grains of the copper foil can be suppressed from being inherited by the copper grains precipitated by the electroless copper plating.

[0024] [Details of the embodiments of the present disclosure]

[0025] Hereinafter, each embodiment of the printed wiring board according to the present disclosure will be described in detail with reference to the drawings.

[0026] <Printed Wiring Board>

[0027] Figure 1shows a printed wiring board according to one embodiment of the present disclosure. This printed wiring board 20 comprises: an insulating base layer 1; a first conductive layer 2, directly or indirectly laminated on the surface of base layer 1 and comprising copper foil; a second conductive layer 3, directly or indirectly laminated on the back surface of base layer 1 and comprising copper foil; and a through-hole laminate 10, laminated on the inner periphery and bottom of a connection hole 5 that passes through first conductive layer 2 and base layer 1 in the thickness direction and electrically connects first conductive layer 2 and second conductive layer 3. Through-holes 4, used for connecting patterns between different conductive layers, are formed by laminating through-hole laminate 10 on connection hole 5.

[0028] Next, each component of the printed wiring board will be described in detail.

[0029] [Base material layer]

[0030] As the material of the base material layer 1, for example, polyamide, polyimide, polyamide-imide, polyester, etc. can be listed. Among them, for example, from the viewpoint of mechanical strength such as heat resistance, polyamide, polyimide and polyamide-imide are preferably used. The printed wiring board does not need to have flexibility.

[0031] The lower limit of the average thickness of the substrate layer 1 is preferably 5 μm, more preferably 10 μm. On the other hand, the upper limit of the average thickness of the substrate layer 1 is preferably 100 μm, more preferably 50 μm. If the average thickness of the substrate layer 1 is less than the lower limit, there is a concern that the strength of the substrate layer 1 may be insufficient. Conversely, if the average thickness of the substrate layer 1 exceeds the upper limit, there is a concern that the flexibility may be insufficient.

[0032] [Conductive layer]

[0033] The first conductive layer 2 and the second conductive layer 3 are formed by patterning a copper foil laminated on the base material layer 1. The copper foil contains copper crystal grains oriented in the (100) plane direction, and the average copper grain size in the copper foil is 10 μm or larger. Since the copper crystal grains in the copper foil have a plane orientation and an average grain size within the above ranges, the copper foil exhibits excellent mechanical properties such as bendability.

[0034] Typically, patterning of the conductors forming the first conductive layer 2 and the second conductive layer 3 is performed after forming the through-holes 4. To increase wiring density, the first conductive layer 2 and the second conductive layer 3 may also have a structure having pads for connection to the through-holes 4 and a wiring pattern having a width smaller than the pads and extending linearly.

[0035] The copper foil contains copper grains oriented in the (100) plane direction. The lower limit of the average grain size of the copper in the copper foil is 10 μm, preferably 12 μm. The upper limit of the average grain size of the copper in the copper foil is not particularly limited, and can be set to, for example, 100 μm, preferably 80 μm, and more preferably 55 μm. It should be noted that when the average grain size of the copper in the copper foil is less than 10 μm, it is difficult to produce a poor appearance on the surface of the electrolytic copper plating layer, and therefore the effect of the printed wiring board cannot be fully exerted.

[0036] In this printed wiring board, the lower limit of the ratio of the area of ​​copper crystal grains oriented along the (100) plane on the surface of the copper foil relative to the area of ​​the copper foil surface is preferably 50%, more preferably 60%, and even more preferably 80%. Since the ratio of the area of ​​copper crystal grains oriented along the (100) plane on the surface of the copper foil relative to the area of ​​the copper foil surface is within the above range, the effect of suppressing the local abnormal growth of copper crystals in the electrolytic copper plating layer is improved. It should be noted that when the above area ratio is less than 40%, since it is difficult to produce poor appearance of the surface of the electrolytic copper plating layer, the effect of the printed wiring board cannot be fully exerted.

[0037] In order to make the ratio of the area of ​​copper grains oriented along the (100) plane direction on the surface of the above-mentioned copper foil relative to the area of ​​the above-mentioned copper foil surface fall within a specified range, although there is no particular restriction, it can be achieved by, for example, controlling the element content, controlling the rolling conditions, performing heat treatment, etc.

[0038] From the perspective of ensuring sufficient conductivity, the lower limit of the average thickness of the first conductive layer 2 and the second conductive layer 3 is preferably 2 μm, and more preferably 5 μm. On the other hand, from the perspective of circuit formability, the upper limit of the average thickness of the first conductive layer 2 and the second conductive layer 3 is preferably 100 μm, and more preferably 50 μm.

[0039] [Laminate for through-hole]

[0040] The through-hole laminate 10 includes an electroless copper plating layer 8 laminated on the inner periphery and bottom of the connection hole 5, and an electrolytic copper plating layer 7 laminated on the surface of the electroless copper plating layer 8. The through-hole laminate 10 is laminated on the inner periphery and bottom of the connection hole 5 that penetrates the first conductive layer 2 and the base layer 1 in the thickness direction. The through-hole laminate 10 electrically connects the first conductive layer 2 and the second conductive layer 3. More specifically, the through-hole laminate 10 may include an electroless copper plating layer 8 laminated on the inner periphery of the connection hole 5, the surface of the first conductive layer 2 opposite to the base layer 1, and the surface of the second conductive layer 3 exposed to the inside of the connection hole 5 (i.e., the bottom), and an electrolytic copper plating layer 7 further laminated on the electroless copper plating layer 8.

[0041] Figure 2 The figure shows a state before forming through-holes 4 and patterning the first conductive layer 2 and the second conductive layer 3, illustrating the shape of the connection holes 5. The connection holes 5 penetrate the base material layer 1 and the first conductive layer 2 in the thickness direction and are defined by the cylindrical surface forming the connection holes 5. Furthermore, by laminating the through-hole laminate 10 on the connection holes 5, the through-holes 4 for connecting the patterns of the first conductive layer 2 and the second conductive layer are formed.

[0042] (Electroless copper plating)

[0043] Electroless copper plating layer 8 is a thin layer with electrical conductivity, and is used as an adherend when forming electrolytic copper plating layer 7 by electrolytic copper plating. This electroless copper plating layer 8 can be formed with the copper laminated by electroless copper plating. Copper plating is because flexibility, thickening property, and the adhesion with electrolytic copper plating are good, and electrical conductivity is high, and is therefore suitable for printed wiring board. This electroless copper plating is the processing that makes the metal with catalytic activity precipitate by the reduction of catalyzer, and can be carried out by coating commercially available various electroless copper plating liquids. By using electroless copper plating like this, it is possible to simply carry out the lamination of electroless copper plating layer 8, it is possible to reliably further laminate electrolytic copper plating layer 7.

[0044] The lower limit of the average thickness of the electroless copper plating layer 8 is preferably 0.05 μm, more preferably 0.10 μm. On the other hand, the upper limit of the average thickness of the electroless copper plating layer 8 is preferably 1.0 μm, more preferably 0.5 μm. When the average thickness of the electroless copper plating layer 8 is less than the above lower limit, there is a concern that the continuity of the electroless copper plating layer 8 cannot be ensured, and the electrolytic copper plating layer 7 cannot be uniformly formed. In addition, when the above average thickness is less than the above lower limit, there is a concern that the orientation of the copper grains of the copper foil is easily inherited by the copper grains precipitated by the electroless copper plating. On the other hand, when the average thickness of the electroless copper plating layer 8 exceeds the above upper limit, there is a concern that the cost is unnecessarily increased. Since the average thickness of the electroless copper plating layer is within the above range, the electrolytic copper plating layer can be formed uniformly, and the orientation of the copper grains of the copper foil can be suppressed from being inherited by the copper grains precipitated by the electroless copper plating.

[0045] The electroless copper plating layer 8 contains palladium as a catalyst. Palladium is applied as a catalyst before the electroless copper plating layer lamination process described later, and the electroless copper plating layer is laminated thereon. Therefore, palladium is present in high content in the electroless copper plating layer near the interface with the conductive layer. In the printed wiring board 20, since the electroless copper plating layer 8 contains palladium, the orientation of the copper grains of the above-mentioned copper foil is suppressed from being inherited by the copper grains precipitated by the electroless copper plating. As a result, the formation of unevenness on the surface of the electrolytic copper plating layer 7 due to the abnormal growth of the copper crystals of the electrolytic copper plating layer 7 is suppressed. Therefore, the printed wiring board 20 can suppress erroneous detection during appearance inspection using an automatic optical inspection device and the peeling of the bottom of the through-hole 4 from the second conductive layer 3. As described above, as a form of the catalyst containing palladium in the present application, an aqueous solution containing palladium ions can be listed, using water as a solvent.

[0046] The lower limit of the amount of palladium deposited per unit area on the copper foil surface is 0.03 μg / cm 2 , preferably 0.05 μg / cm 2 The upper limit of the palladium layer amount is 0.15 μg / cm 2 , preferably 0.10 μg / cm 2 Since the amount of palladium stacked is within the above range, the amount of catalyst nuclei generated by the electroless copper plating is within an appropriate range. As a result, it is believed that it is more difficult to form the electroless copper plating layer 8 and the electrolytic copper plating layer 7 having the same orientation as the copper grains of the copper foil. If the amount of palladium stacked exceeds the above upper limit, there is a concern that the connection strength between the copper foil included in the second conductive layer 3 and the electroless copper plating layer 8 and the electrolytic copper plating layer 7 at the bottom of the through-hole 4 will be weakened, and the bottom of the through-hole 4 may be peeled off.

[0047] (Electrolytic copper plating layer)

[0048] Electrolytic copper plating layer 7 is laminated on the surface of electroless copper plating layer 8 by electrolytic copper plating. By forming electroless copper plating layer 8 in this manner and then providing electrolytic copper plating layer 7 on its inner periphery and bottom, through-holes 4 with excellent conductivity can be easily and reliably formed. As mentioned above, copper is inexpensive and highly conductive, so it is suitable as the metal for forming the electrolytic copper plating layer.

[0049] The lower limit of the average thickness of the electrolytic copper plating layer 7 is preferably 1 μm, more preferably 5 μm. On the other hand, the upper limit of the average thickness of the electrolytic copper plating layer 7 is preferably 50 μm, more preferably 30 μm. When the average thickness of the electrolytic copper plating layer 7 is less than the above lower limit, there is a concern that the electrical connection between the first conductive layer 2 and the second conductive layer 3 will be disconnected due to the bending of the printed wiring board 20, etc., causing the through hole 4 to break. In addition, when the above average thickness is less than the above lower limit, there is a concern that the orientation of the copper grains of the copper foil will be easily inherited by the copper grains precipitated by the electrolytic copper plating. On the other hand, when the average thickness of the electrolytic copper plating layer 7 exceeds the above upper limit, there is a concern that the printed wiring board 20 will become too thick and the manufacturing cost will be unnecessarily increased.

[0050] [Manufacturing method of printed wiring board]

[0051] The manufacturing method of the printed wiring board includes: a conductive layer laminating process, for example, laminating a first conductive layer including copper foil on the surface of a base material layer, and laminating a second conductive layer including copper foil on the back side of the above-mentioned base material layer; a connection hole forming process, forming a connection hole that penetrates the above-mentioned first conductive layer and the above-mentioned base material layer in the thickness direction; an electroless copper plating pretreatment process, performing pretreatment before electroless copper plating the inner periphery and bottom of the above-mentioned connection hole; an electroless copper plating layer laminating process, laminating an electroless copper plating layer on the inner periphery and bottom of the connection hole that has been subjected to the above-mentioned electroless copper plating pretreatment; and an electrolytic copper plating layer laminating process, laminating an electrolytic copper plating layer on the surface of the above-mentioned electroless copper plating layer.

[0052] (Conductive Layer Lamination Step)

[0053] In the conductive layer lamination step, the copper foil is laminated on the surface of the base layer to form a first conductive layer. Separately, the copper foil is laminated on the back surface of the base layer to form a second conductive layer. In the conductive layer lamination step, a conductive pattern is formed on the surface of the base layer using a known method.

[0054] There is no particular limitation on the method of laminating the copper foil constituting the first conductive layer and the second conductive layer on the base layer. For example, a bonding method in which the copper foil is bonded with an adhesive; a casting method in which a resin composition serving as the material of the base layer is coated on the copper foil; a sputtering / plating method in which copper foil is formed by plating on a thin conductive layer (seed layer) having a thickness of several nm formed on the base layer by a sputtering method or a vapor deposition method; a lamination method in which the copper foil is bonded to the base layer by hot pressing, etc. can be used.

[0055] (Connection Hole Forming Step)

[0056] The method for forming the hole for electrically connecting the first and second conductive layers is not particularly limited, and a method of, for example, drilling holes in the first conductive layer and the base layer using a micro drill or laser to expose the copper foil of the second conductive layer can be used.

[0057] (Electroless copper plating pretreatment process)

[0058] The electroless copper plating pretreatment step is a pretreatment step before electroless copper plating is performed on the inner periphery and bottom of the connection hole. In this step, for example, a cleaning step, an acid treatment step, a pre-dip step, a catalyst treatment step, and a reduction step are performed.

[0059] The pre-dip step involves immersing the substrate in a liquid, such as one obtained by removing the catalyst from the catalyst liquid, before immersing the substrate in the catalyst liquid. This pre-dip step displaces water adhering to the surface of the conductive pattern, making the surface of the substrate layer susceptible to catalyst adhesion. This prevents uneven dispersion of the catalyst during the subsequent catalyst treatment step.

[0060] In the catalyst treatment step, the laminate comprising a substrate layer and a conductive layer is immersed in an activator containing palladium ions. A water washing step is performed after the catalyst treatment step. As described above, the catalyst treatment step using palladium is performed after the conductive layer lamination step and before the electroless copper plating step. As a result, palladium is present in high concentrations in the electroless copper plating layer near the interface with the conductive layer.

[0061] In the reduction step, the catalyst is reduced. Specifically, in the reduction step, palladium ions (Pd 2+ ) is reduced to palladium (Pd 0 ) and formed on the surface to become a catalyst core, and the palladium catalyst is supported on the surface of the conductive pattern. After the above-mentioned reduction step, a water washing step is performed.

[0062] (Electroless Copper Plating Layer Lamination Process)

[0063] In the electroless copper plating layer lamination step, electroless copper plating is applied to the inner periphery and bottom of the connection hole to form an electroless copper plating layer. In the electroless copper plating step, the laminate comprising the base layer and the conductive layer is immersed in an electroless copper plating solution activated by heating to deposit copper on the surface of the conductive pattern. The electroless copper plating solution is preferably an alkaline bath.

[0064] The lower limit of the heating temperature of the electroless copper plating solution is preferably 20°C. On the other hand, the upper limit of the heating temperature of the electroless copper plating solution is preferably 40°C. If the heating temperature of the electroless copper plating solution is less than the above lower limit, there is a concern that the plating reaction may be insufficient. On the other hand, if the heating temperature of the electroless copper plating solution exceeds the above upper limit, there is a concern that it may be difficult to adjust the thickness of the formed electroless copper plating layer.

[0065] The lower limit of the immersion time in the electroless copper plating solution is preferably 1 minute, more preferably 2 minutes. On the other hand, the upper limit of the immersion time in the electroless copper plating solution is preferably 30 minutes, more preferably 20 minutes. When the immersion time in the electroless copper plating solution is less than the above lower limit, there is a concern that an electroless copper plating layer of sufficient thickness cannot be formed. On the other hand, when the immersion time in the electroless copper plating solution exceeds the above upper limit, there is a concern that corrosion of the conductive pattern caused by local battery action cannot be fully prevented.

[0066] (Electrolytic Copper Plating Layer Lamination Step)

[0067] In the electrolytic copper plating layer lamination step, an electrolytic copper plating layer is laminated on the surface of the electroless copper plating layer by electrolytic copper plating. In this electrolytic copper plating step, the thickness of the through-hole laminate is increased to a desired thickness.

[0068] In the electrolytic copper plating layer lamination step for forming the electrolytic copper plating layer, the electroless copper plating layer is used as an adherend, and a metal is laminated by electrolytic copper plating to form an electrolytic copper plating layer that contacts the inner periphery and bottom of the electroless copper plating layer, thereby forming a through hole with a sufficient thickness.

[0069] According to this printed wiring board, when a copper foil having copper crystal grains oriented in the (100) plane direction and an average crystal grain diameter of 10 μm or greater is used as a conductive layer, the formation of unevenness on the surface of the electrolytic copper plating layer of the through-hole laminate is suppressed. Therefore, this printed wiring board can suppress false detection during appearance inspection using an automatic optical inspection device and peeling of the bottom of the through-hole. Therefore, this printed wiring board is particularly suitable for use as a flexible printed wiring board used in small portable electronic devices, etc.

[0070] [Other embodiments]

[0071] The embodiments disclosed herein are to be considered in all respects as illustrative and non-restrictive. The scope of the present disclosure is not limited to the configurations of the above-described embodiments, but is defined by the claims, and is intended to encompass all modifications within the meaning and scope equivalent to the claims.

[0072] In this printed wiring board, the first conductive layer and the second conductive layer are relative to each other, and the conductive layer that is the first conductive layer in one through-hole can also be the second conductive layer in another through-hole.

[0073] The printed wiring board may also be a multilayer wiring board further comprising a base material layer and a conductive layer. Furthermore, the printed wiring board may also include other layers such as a cover layer, a solder resist, and a shielding film. Furthermore, when the printed wiring board is a multilayer wiring board, the through-hole may be a through-hole that penetrates multiple layers.

[0074] Example

[0075] Hereinafter, the present disclosure will be described in detail based on Examples, but the present disclosure should not be restrictively interpreted based on the description of these Examples.

[0076] [No.1~No.5]

[0077] As a substrate, ESPANEX (copper 12μm / polyimide 12μm / copper 12μm) produced by Nippon Steel & Sumikin Chemical Co., Ltd. was used. Copper foil oriented in the (100) plane direction was stacked on the surface and back of the substrate to form a conductive layer on the surface and back of the substrate (conductive layer stacking process). The copper and polyimide on the surface of the obtained sample were removed by UV laser to make through holes (connection hole forming process). Then, almost the entire surface of the conductive layer was subjected to electroless copper plating pretreatment (electroless copper plating pretreatment process). In this electroless copper plating pretreatment process, the sample was immersed in an aqueous solution (activator) containing palladium ions as a catalyst treatment. The conditions of the electroless copper plating pretreatment processes No. 1 to No. 5 are as follows.

[0078] (Conditions for electroless copper plating pretreatment process)

[0079] It should be noted that the conditions for No. 4, No. 5 and No. 1 are the same.

[0080] (1) No.1

[0081] The process was carried out as follows: cleaning → soft etching (60 seconds) → pickling → pre-dip → activator (1.5 times the palladium concentration in the solution: 0.12 g / L) → electroless copper plating.

[0082] (2) No.2

[0083] The steps of cleaning → soft etching (60 seconds) → pickling → pre-dip → activator (normal palladium concentration 0.08 g / L) → electroless copper plating were implemented.

[0084] (3)No.3

[0085] The process was carried out as follows: cleaning → soft etching (60 seconds) → pickling → pre-dip → activator (3 times the palladium concentration in the solution: 0.24 g / L) → electroless copper plating.

[0086] (4) No.4

[0087] The process was carried out as follows: cleaning → soft etching (60 seconds) → pickling → pre-dip → activator (1.5 times the palladium concentration in the solution: 0.12 g / L) → electroless copper plating.

[0088] (5)No.5

[0089] The process was carried out as follows: cleaning → soft etching (60 seconds) → pickling → pre-dip → activator (1.5 times the palladium concentration in the solution: 0.12 g / L) → electroless copper plating.

[0090] Electroless copper plating was performed at 23°C for 15 minutes to deposit an electroless copper plating layer with an average thickness of 0.10 μm (electroless copper plating layer deposition step). Next, the current density was adjusted to 2 A / dm2 relative to the exposed area of ​​the conductive layer. 2 Electrolytic copper plating was performed at 25° C. for 28 minutes to deposit an electrolytic copper plating layer having an average thickness of 12 μm (electrolytic copper plating layer deposition step).

[0091] [evaluate]

[0092] (Measurement of the Lamination Amount of Palladium)

[0093] Regarding the palladium lamination amount on the copper foil, the printed wiring boards No. 1 to No. 5 were cut into 20 mm x 20 mm pieces, dissolved in a mixed solution of nitric acid and hydrochloric acid, and the resulting solution was measured by inductively coupled plasma-mass spectrometry (ICP-MS).

[0094] (False detection rate during appearance inspection using automated optical inspection equipment)

[0095] 100 printed wiring boards, each numbered 1 to 5, were prepared and subjected to appearance inspection using an automated optical inspection system. Next, each of the printed wiring boards, numbered 1 to 5, that had appearance defects detected by the automated optical inspection system was visually inspected using an optical microscope to determine if any defects were present. The percentage of false positives during appearance inspection using the automated optical inspection system was calculated for each of the printed wiring boards, numbered 1 to 5, and evaluated using the following three levels: boards rated A or B were deemed acceptable.

[0096] A: False detection rate 0% or more and less than 6%

[0097] B: False detection rate 6% or more and less than 16%

[0098] C: False detection rate 16% or more

[0099] (Occurrence rate of peeling at the bottom of through-hole)

[0100] The bottoms of the through-holes were visually inspected using an optical microscope for peeling. The incidence of peeling at the bottoms of the through-holes of each of the printed wiring boards No. 1 to No. 5 was calculated by calculating the proportion of printed wiring boards with observed peeling at the bottoms of the through-holes among the 100 printed wiring boards of each test number. The results were evaluated using the following three levels. Printed wiring boards rated A or B were deemed acceptable based on the evaluation results.

[0101] A: Peel rate 0% or more and less than 1%

[0102] B: Peel rate 1% or more and less than 2%

[0103] C: Peel rate 2% or more

[0104] Table 1 shows the evaluation results.

[0105] [Table 1]

[0106]

[0107] As shown in Table 1, the average crystal grain size of copper in the copper foil is 10 μm or more, and the amount of palladium laminated per unit area on the copper foil surface is 0.03 μg / cm 2 Above and 0.15 μg / cm 2 The following tests No. 1 and No. 4 to No. 5 were effective in suppressing erroneous detection and peeling of the bottom of the through hole during appearance inspection using an automatic optical inspection device.

[0108] On the other hand, the amount of palladium deposited per unit area on the copper foil surface is less than 0.03 μg / cm 2 Test No. 2 was poor in suppressing erroneous detection during appearance inspection using an automatic optical inspection device. In addition, the amount of palladium deposited per unit area on the copper foil surface exceeded 0.15 μg / cm 2 Test No. 3 was poor in suppressing peeling at the bottom of the through-hole.

[0109] Description of Reference Numerals

[0110] 1 base material layer

[0111] 2First conductive layer

[0112] 3 Second conductive layer

[0113] 4 through holes

[0114] 5 connection holes

[0115] 7Electrolytic copper plating layer

[0116] 8. Electroless copper plating layer

[0117] 10Through-hole laminate

[0118] 20 printed wiring boards.

Claims

1. A printed wiring board comprising: a substrate layer having insulating properties; a first conductive layer, directly or indirectly laminated on the surface of the substrate layer, and comprising copper foil; a second conductive layer, directly or indirectly laminated on the back surface of the base material layer, and comprising copper foil; and The through-hole laminate is laminated on the inner periphery and bottom of the connection hole that penetrates the first conductive layer and the base layer in the thickness direction, and electrically connects the first conductive layer and the second conductive layer. The through-hole laminate comprises an electroless copper plating layer laminated on the inner periphery and bottom of the connection hole and an electrolytic copper plating layer laminated on the surface of the electroless copper plating layer. The copper foil contains copper grains oriented along the (100) plane direction, and the average grain diameter of the copper in the copper foil is 10 μm or more and 55 μm or less. The electroless copper plating layer comprises palladium, The amount of palladium deposited per unit area on the copper foil surface at the interface between the electroless copper plating layer and the first and second conductive layers was 0.03 μg / cm 2 Above and 0.10 μg / cm 2 the following, The ratio of the area of ​​the copper crystal grains oriented in the (100) plane direction present on the surface of the copper foil to the area of ​​the surface of the copper foil is 60% or more.

2. The printed wiring board according to claim 1, wherein The average thickness of the electroless copper plating layer is 0.05 μm or more and 1.0 μm or less.

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