A method for improving silicon dross after epitaxy of substrate wafers

Abstract

This invention discloses a method for improving silicon dross on the back of a substrate after epitaxy, comprising a back-sealing step and an epitaxial step. In the back-sealing step, the polycrystalline temperature is controlled at 600°C to 650°C, and silane is used as a raw material. At the polycrystalline temperature, the silane decomposes and precipitates to form a polycrystalline film. After back-sealing in the polycrystalline step, the substrate silicon wafer is polished and then proceeds to the epitaxial step. This invention adjusts the polycrystalline temperature in the polycrystalline back-sealing step to control the physical properties of the substrate wafer after the formation of the polycrystalline film, thereby improving the back-side silicon dross problem after epitaxy.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, specifically to a method for improving silicon dross after epitaxy on a substrate. Background Technology

[0002] Epitaxy refers to the process of growing a new single crystal on a single crystal substrate. Epitaxy can be used to produce a wider variety of materials, giving device design more options.

[0003] In existing processes, a polycrystalline film is typically formed on the substrate after back sealing, followed by polishing to form a polished wafer, which is then ready for epitaxial growth. However, after the epitaxial layer is grown, silicon dross of varying sizes grows along the edges of the back side of the silicon wafer. This can prevent the formation of an effective vacuum when the epitaxial wafer is placed on the lithography machine, making it difficult to hold the silicon epitaxial wafer in place. Alternatively, poor flatness of the silicon dross on the back side of the silicon epitaxial wafer can lead to uneven lithography stripe widths, causing the silicon epitaxial wafer to fail.

[0004] Currently, the process involves treating the silicon dross after epitaxy, as illustrated in the published Chinese invention patent CN102479679A, "Method for Treating Silicon Drowning on the Back Side of Silicon Epitaxial Wafers." This method removes the silicon dross from the epitaxial wafer through physical scraping and chemical cleaning, which undoubtedly increases the number of process steps. Therefore, the applicant intends to improve the existing process to reduce the amount of silicon dross. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention provides a method for improving silicon dross after epitaxy of a substrate.

[0006] This invention provides the following technical solution: a method for improving silicon dross after epitaxy of a substrate, comprising a back sealing step and an epitaxy step;

[0007] In the back sealing step, the polycrystalline temperature is controlled at 600℃ to 650℃, and silane is used as raw material. At the polycrystalline temperature, the silane decomposes and precipitates to form a polycrystalline film.

[0008] After the polycrystalline back-sealing process, the substrate silicon wafer is polished and then enters the epitaxial process.

[0009] Furthermore, the polycrystalline temperature is 600℃, the flatness after polishing is between 2.74 and 6.05 μm, the warpage is between 70.48 and 81.34, and the curvature is between -36.31 and -32.17.

[0010] Furthermore, the polycrystalline temperature is 640℃, the flatness after polishing is between 4.01 and 6.33 μm, the warpage is between 38.33 and 48.84, and the curvature is between -21.96 and -17.71.

[0011] Furthermore, the polycrystalline temperature is 650℃, the flatness after polishing is between 2.5 and 7.4 μm, the warpage is between 20.56 and 29.37, and the curvature is between -13.29 and -9.26.

[0012] Furthermore, the polycrystalline temperature is 650℃, the flatness after polishing is between 2.67 and 8.47 μm, the warpage is between 10.82 and 16.78, and the curvature is between -7.03 and -4.15.

[0013] Furthermore, polycrystalline film thickness fixation

[0014] Furthermore, the back sealing step also includes a step for generating a silica back sealing film, the thickness of which is...

[0015] Furthermore, the epitaxy is performed using an atmospheric pressure flat-plate epitaxy furnace of model LPE-3061D, with the furnace base rotation speed controlled at 5.0 r / min.

[0016] Furthermore, the extensional steps include the following:

[0017] (1) Use hydrogen chloride gas to etch the epitaxial furnace base at high temperature to remove the deposits on the base. The temperature is set to 1060℃, the hydrogen chloride gas flow rate is set to 35Slm, and the etching time is set to 10min.

[0018] (2) Load the substrate wafer into the wafer pit of the epitaxial furnace base;

[0019] (3) The intrinsic epitaxial layer is grown using trichlorosilane on the substrate to prevent the overflow of impurities from the heavily doped substrate. The intrinsic layer growth temperature is set to 1060℃. Gaseous trichlorosilane is transported into the reaction chamber using hydrogen. The hydrogen flow rate is controlled at 150 μm, the trichlorosilane flow rate is set at 20 μm, and the growth rate is controlled at 2.25 μm / min.

[0020] (4) The growth of the doped epitaxial layer was carried out at a growth temperature of 1060℃. Gaseous trichlorosilane and phosphine dopants were transported into the reaction chamber by hydrogen. The hydrogen flow rate was controlled at 150 μm, the trichlorosilane flow rate was set at 20 μm, the phosphine flow rate was set at 147 sccm, and the epitaxial layer growth rate was controlled at 2.25 μm / min.

[0021] (5) After the epitaxial layer reaches the predetermined thickness, start cooling. Set the flow rate of hydrogen and nitrogen to 150 μm and purge the reaction chamber of the epitaxial furnace for 8 minutes. Then remove the epitaxial wafer from the substrate.

[0022] Compared with the prior art, the present invention provides a method for improving silicon dross after epitaxy of a substrate, which has the following beneficial effects:

[0023] Adjusting the polycrystalline temperature in the polycrystalline back-sealing step controls the physical properties of the substrate after the polycrystalline film is formed, thereby improving the back-side silicon dross problem after epitaxy of the substrate. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of the backside silicon slag condition before the improvement of this invention;

[0025] Figure 2 This is a schematic diagram of the back silicon slag condition under the polycrystalline temperature of 600℃ according to the present invention.

[0026] Figure 3 This is a schematic diagram of the back silicon slag condition under the polycrystalline temperature of 640°C according to the present invention.

[0027] Figure 4 This is a schematic diagram of the back silicon slag condition under the polycrystalline temperature of 650°C according to the present invention.

[0028] Figure 5 This is a schematic diagram of the back silicon slag condition under the polycrystalline temperature of 660°C according to the present invention.

[0029] Figure 6 This is an enlarged schematic diagram of the back side of the present invention under various temperature conditions;

[0030] Figure 7 This is a graph showing the relationship between polycrystalline temperature and silicon slag content in this invention. Detailed Implementation

[0031] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0032] Please refer to the figure for a method to improve silicon dross after epitaxy of a substrate, which includes a back sealing step and an epitaxy step;

[0033] In the back sealing step, the polycrystalline temperature is controlled at 600℃ to 650℃, and silane is used as raw material. At the polycrystalline temperature, the silane decomposes and precipitates to form a polycrystalline film.

[0034] After the polycrystalline back-sealing process, the substrate silicon wafer is polished and then enters the epitaxial process.

[0035] In the back sealing process, two types of films are usually formed: a polycrystalline film and a silicon dioxide film.

[0036] Specifically, back-sealed polycrystalline silicon: For heavily doped silicon wafers, polycrystalline silicon undergoes a high-temperature stage, depositing a thin film on the back of the wafer to prevent dopant from diffusing outwards. This layer acts like a sealant to prevent dopant escape. Depositing polycrystalline silicon on the back prevents autodoping and traps heavy metals within the silicon wafer, further enhancing its gettering ability. At high temperatures, some polycrystalline silicon may oxidize, but this does not reduce its gettering ability.

[0037] Silanes are commonly used to grow polycrystalline silicon. The thermal decomposition reaction of silane at high temperatures is: SiH4 → Si + 2H2. In low-pressure CVD (LPCVD), it can be deposited at around 650°C. This temperature falls between the deposition temperatures of amorphous and monocrystalline silicon. After each batch of silicon wafers is produced, the thickness and uniformity of the polycrystalline back surface and the condition of the back surface must be inspected as quickly as possible.

[0038] For heavily doped silicon wafers, a thin film of silicon dioxide is deposited on the back of the wafer to prevent dopant from diffusing outwards. This layer acts like a sealant to prevent dopant escape. Three types of films are commonly used as back sealing materials: silicon dioxide (SiO2), silicon nitride (Si3N4), and polycrystalline silicon. If oxides or nitrides are used for back sealing, they can be strictly considered as sealants, while if polycrystalline silicon is used, in addition to acting primarily as a sealant, it also serves as an external getter.

[0039] The reaction of silane with oxygen in the furnace (at a temperature of around 400℃) is: SiH4 + 2O2 → SiO2 + 2H2O. During back sealing, the silicon wafer is placed face down on the substrate, and the deposited material is applied to the back side, the same size as the silicon wafer.

[0040] In this embodiment, a heavily arsenic-doped silicon substrate is used as an example to finally form a polycrystalline film with a thickness of [missing information]. Silica film thickness For two-layer films, the conventional approach is to first form a polycrystalline film and then generate a silicon dioxide film. However, if further improvements to the surface morphology of the silicon slag and substrate material are desired, it is preferable to first form a silicon dioxide film and then generate a polycrystalline film.

[0041] After back sealing, polishing is performed using the "Polishing Machine Operation Instruction Manual" document number HX-WJ-513-003-17-0. The goal is to obtain a very smooth, flat, and undamaged silicon surface. The polishing process is similar to the wafer grinding process, but the underlying principles are different. During wafer grinding, the silicon wafer undergoes mechanical abrasion; while polishing is a chemical / mechanical process. This difference in operating principle is the reason why polishing can produce a smoother surface than wafer grinding.

[0042] During polishing, the silicon wafer is chemically / mechanically polished using a special polishing pad and a special polishing slurry. The polishing surface of the silicon wafer is rotated and subjected to a certain pressure, passing through a polishing slurry covering the polishing pad. The polishing slurry consists of silica gel and a special high-pH chemical reagent. This high-pH chemical reagent oxidizes the surface of the silicon wafer, and the oxide layer is mechanically removed from the surface by the silica gel-containing polishing slurry.

[0043] Silicon wafers typically undergo multiple polishing steps. The first step is rough polishing, using a harder polishing pad. The polishing slurry reacts more readily with the pad, and contains more coarse (60-100nm) silicone particles than the slurries used in subsequent polishing stages. This first step aims to remove etch spots and some residual mechanical damage (generally removing 22-26µm). In the following polishing stages, a fine polishing process is performed using a softer polishing pad and a polishing slurry containing fewer chemicals and finer (20-40nm) silicone particles. This final polishing, removing remaining damage and haze, is called fine polishing. Fine polishing removes virtually no material.

[0044] After polishing and cleaning, a visual inspection can be performed. During the inspection, under a spotlight, a full visual inspection is conducted to confirm defects such as scratches, chipping, gaps, orange peel, shallow pits, fogging, and crazing on the surface of the polished sheet. Using a sorting machine, the flatness and warping of CTR THK, Mean THK, Min.THK, Max.THK, TTV, Warp-bf, and Bow-bf are recorded.

[0045] Next, the epitaxial step is carried out. In this embodiment, an LPE-3061D atmospheric pressure flat plate epitaxial furnace is used, and the rotation speed of the epitaxial furnace base is controlled at 5.0 r / min.

[0046] (1) Use hydrogen chloride gas to etch the epitaxial furnace base at high temperature to remove residual deposits on the base. The temperature is set to 1060℃, the hydrogen chloride gas flow rate is set to 35Slm, and the etching time is set to 10min.

[0047] (2) Load the substrate wafer into the wafer pit of the epitaxial furnace base;

[0048] (3) The intrinsic epitaxial layer is grown using trichlorosilane on the substrate to prevent the overflow of impurities from the heavily doped substrate. The intrinsic layer growth temperature is set to 1060℃. Gaseous trichlorosilane is transported into the reaction chamber using hydrogen. The hydrogen flow rate is controlled at 150 μm, the trichlorosilane flow rate is set at 20 μm, and the growth rate is controlled at 2.25 μm / min.

[0049] (4) The growth of the doped epitaxial layer was carried out at a growth temperature of 1060℃. Gaseous trichlorosilane and phosphine dopants were transported into the reaction chamber by hydrogen. The hydrogen flow rate was controlled at 150 μm, the trichlorosilane flow rate was set at 20 μm, the phosphine flow rate was set at 147 sccm, and the epitaxial layer growth rate was controlled at 2.25 μm / min.

[0050] (5) After the epitaxial layer reaches the predetermined thickness, begin cooling. Set the flow rates of hydrogen and nitrogen to 150 μm and purge the reaction chamber of the epitaxial furnace for 8 minutes each time. Then, remove the epitaxial wafer from the substrate. Visually inspect the condition of the silicon slag on the back side using fluorescent and high-intensity light.

[0051] In this embodiment, the surface properties of the substrate after polycrystalline formation, such as warpage, curvature, and flatness, are adjusted by controlling the temperature at which the polycrystalline film is formed, thereby controlling the silicon slag condition after epitaxy.

[0052] The specific values ​​for flatness (TTV), warpage (WARP), and bending (BOW) are as follows:

[0053] After polycrystalline polishing at 600℃, the TTV of the full scan data is between 2.74 and 6.05 μm, the Warp is between 70.48 and 81.34, and the Bow is between -36.31 and -32.17.

[0054] After polycrystalline polishing at 640℃, the TTV data of the full scan ranged from 4.01 to 6.33 μm, the Warp ranged from 38.33 to 48.84, and the Bow ranged from -21.96 to -17.71.

[0055] After polycrystalline polishing at 650℃, the thickness TTV ranged from 2.5 to 7.4 μm, the warp ranged from 20.56 to 29.37 μm, and the bow ranged from -13.29 to -9.26 μm.

[0056] After polycrystalline polishing at 660℃, the thickness TTV ranged from 2.67 to 8.47 μm, the warp ranged from 10.82 to 16.78 μm, and the bow ranged from -7.03 to -4.15 μm.

[0057]

[0058]

[0059] Experimental methods:

[0060] To control variables, first, ensure that all other process steps remain consistent in each experiment, and only differentiate the temperature at which the polycrystalline film is generated, trying each temperature one by one as described above: 600℃, 640℃, 650℃, and 660℃.

[0061] Polycrystalline front full scan data:

[0062]

[0063]

[0064] The TTV of the polycrystalline pre-scan data ranged from 1.99 to 4.88 μm, the Warp ranged from 5.15 to 10.69, and the Bow ranged from -1.21 to 0.46.

[0065] Full scan data after polycrystalline polishing at 600℃.

[0066]

[0067]

[0068] After polycrystalline polishing at 600℃, the TTV of the full scan data is between 2.74 and 6.05 μm, the Warp is between 70.48 and 81.34, and the Bow is between -36.31 and -32.17.

[0069] like Figure 2 This is a polycrystalline silicon epitaxy at 600℃, showing the silicon slag on the back side after epitaxy.

[0070] Full scan data after polycrystalline silicon at 640℃:

[0071]

[0072]

[0073]

[0074] Summary: After polycrystalline silicon at 640℃, the TTV of the full scan data is between 2.02 and 5.15 μm, the Warp is between 6.27 and 11.32, and the Bow is between -1.43 and 0.29.

[0075] Full scan data after polycrystalline back seal at 640℃:

[0076]

[0077]

[0078] Summary: The TTV of the full scan data after polycrystalline back sealing at 640℃ is between 1.98 and 5.21 μm, the Warp is between 16.62 and 22.84, and the Bow is between -8.24 and -5.88.

[0079] Full scan data after polycrystalline polishing at 640℃:

[0080]

[0081]

[0082]

[0083] Summary: After polycrystalline polishing at 640℃, the TTV of the full scan data is between 4.01 and 6.33 μm, the Warp is between 38.33 and 48.84, and the Bow is between -21.96 and -17.71.

[0084] like Figure 3 The silicon slag on the back side of the 640℃ polycrystalline epitaxial wafer.

[0085] Thickness data before polishing after polycrystalline processing at 650℃:

[0086]

[0087]

[0088] Summary: The thickness data before polishing after polycrystalline processing at 650℃ are TTV between 1.84 and 5.57 μm, Warp between 3.75 and 7.83 μm, and Bow between -2.38 and -0.37 μm.

[0089] Full scan data after polycrystalline polishing at 650℃:

[0090]

[0091]

[0092]

[0093] Summary: After polycrystalline polishing at 650℃, the thickness TTV ranged from 2.5 to 7.4 μm, the warp ranged from 20.56 to 29.37 μm, and the bow ranged from -13.29 to -9.26 μm.

[0094] like Figure 4 Polycrystalline silicon at 650℃, backside dross condition after epitaxy:

[0095] Full scan data after polycrystalline silicon at 660℃:

[0096]

[0097]

[0098] Summary: After polycrystalline melting at 660℃, the thickness TTV ranges from 2.1 to 5.6 μm, the warp ranges from 5.33 to 8.69 μm, and the bow ranges from -2.84 to -0.87 μm.

[0099] Full scan data after polycrystalline polishing at 660℃:

[0100]

[0101]

[0102]

[0103] Summary: After polycrystalline polishing at 660℃, the thickness TTV ranged from 2.67 to 8.47 μm, the warp ranged from 10.82 to 16.78 μm, and the bow ranged from -7.03 to -4.15 μm.

[0104] Figure 5 The condition of silicon slag on the back side after epitaxy at 660℃ polycrystalline.

[0105] In summary, temperatures between 600℃ and 660℃ are beneficial for improving the flatness, warpage, and curvature of polycrystalline silicon after polishing. The better these physical properties are, the better the improvement effect on backside silicon dross.

[0106] Figure 6 Regarding the relationship between temperature and silicon slag, higher temperatures result in less silicon slag. However, in actual processes, while reaching 660℃ improves the smoothness and reduces silicon slag, it also accelerates the polycrystalline growth rate to a certain extent, leading to larger polycrystalline grains and poorer gettering. Therefore, a trade-off needs to be struck between various parameters in the actual process. In the improved process requirements, it is not recommended that the polycrystalline temperature exceed 650℃; the optimal range is between 600℃ and 650℃.

[0107] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A method of improving silicon residue after epitaxy of a substrate wafer, characterized by: The back sealing step and the epitaxial step are included; in the back sealing step, the step for generating the silicon dioxide back sealing film and the step for generating the polycrystal film are included, wherein the polycrystal film is generated after the silicon dioxide film is generated; when the polycrystal film is generated, the polycrystal temperature is controlled to be 600-650 DEG C, the silane is used as the raw material, the silane is decomposed and precipitated at the polycrystal temperature, so as to form the polycrystal film; after the back sealing of the substrate wafer through the polycrystal step, the substrate wafer is polished and then enters the epitaxial step; when the polycrystal temperature is 600 DEG C, the flatness of the polished substrate wafer is 2.74-6.05 μm, the warping degree is 70.48-81.34, and the bending degree is -36.31--32.17; when the polycrystal temperature is 640 DEG C, the flatness of the polished substrate wafer is 4.01-6.33 μm, the warping degree is 38.33-48.84, and the bending degree is -21.96--17.71; when the polycrystal temperature is 650 DEG C, the flatness of the polished substrate wafer is 2.5-7.4 μm, the warping degree is 20.56-29.37, and the bending degree is -13.29--9.26; the epitaxial step includes the following steps: (1) the base of the epitaxial furnace is corroded at high temperature by using hydrogen chloride gas to remove the deposits on the base; (2) the substrate wafer is loaded into the wafer pit of the base of the epitaxial furnace; (3) the growth of the intrinsic epitaxial layer is carried out, the intrinsic epitaxial layer is grown on the substrate by using trichlorosilane, the overflow of the impurities of the heavily doped substrate is prevented, and the gaseous trichlorosilane is transported into the reaction chamber by using hydrogen; (4) the growth of the doped epitaxial layer is carried out, the gaseous trichlorosilane and the phosphine dopant are transported into the reaction chamber by using hydrogen; (5) after the epitaxial layer is grown to the predetermined thickness, the cooling is started, and then the epitaxial wafer is taken out from the base.

2. The method of claim 1 wherein: The thickness of the polycrystal film is fixed at 8000 angstroms.

3. The method of claim 1 wherein: the substrate is a wafer; and the silicon residue is formed on a backside of the wafer after epitaxial growth of a layer on a frontside of the wafer. The step for generating the silicon dioxide back sealing film is further included in the back sealing step, and the thickness of the back sealing film is 5000 angstroms.

4. The method of claim 1 wherein: the substrate is a wafer; and the silicon residue is formed after epitaxial growth of the wafer. In the back sealing step, the flow rate of the silane introduced into the polycrystal film is 300 Slm, the growth time is 50 min, and the growth thickness is 8000 angstroms.

5. The method of claim 1 wherein: the substrate is a wafer; and the silicon residue is formed after epitaxial growth of the wafer. The epitaxial furnace is the LPE-3061D type atmospheric flat plate epitaxial furnace, and the rotation speed of the base of the epitaxial furnace is controlled to be 5.0 r / min.

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