Power device and preparation method thereof

Abstract

The present application provides a power device and a method for preparing the same. The preparation method comprises the following steps: providing a silicon substrate, forming a well region, a drift region located in the well region, and a shallow trench isolation structure located in the drift region in the silicon substrate, forming a liner isolation layer between the shallow trench isolation structure and the silicon substrate, defining an injection window on the drift region, the injection window being adjacent to the shallow trench isolation structure, and the injection window exposing the silicon substrate; performing ion implantation on the injection window in the drift region to form a destructive layer mainly composed of amorphous silicon on the surface of the silicon substrate corresponding to the injection window; performing thermal oxidation treatment on the region corresponding to the destructive layer to form a high-voltage gate oxide layer in the injection window, the high-voltage gate oxide layer being adjacent to the shallow trench isolation structure. The present application helps to avoid local breakdown of the device and can improve the electrical performance of the device.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to a power device and a method for preparing the same. Background Art

[0002] BCD devices are commonly used power devices that combine bipolar, CMOS, and DMOS devices on the same chip. They are increasingly used in the power device field because they combine the high transconductance and strong load drive capability of bipolar devices, the high integration and low power consumption of CMOS, and the high voltage and high current resistance of DMOS. These devices complement each other and leverage their respective strengths.

[0003] As the process size of power devices continues to shrink, the isolation process of semiconductor devices has changed from Local Oxidation of Silicon (LOCOS) to Shallow Trench Isolation (STI). In power devices, the STI process is additionally used in the drain region to increase the drain current path and reduce the hot carrier effect.

[0004] However, the STI process also has many problems, such as sharp corners at STI corners and pits (divots) formed by excessive corrosion at the top edge of the STI. Therefore, when growing the high-voltage gate oxide (HV GOX, LOCOS) of power devices, the pits and sharp corners at the top edge of the STI will cause the gate oxide to be locally too thin, which directly affects the reliability of the HV GOX and can easily cause local device breakdown and / or leakage, resulting in device performance degradation. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of the present application is to provide a power device and a method for preparing the same, so as to solve the problems of the power devices in the prior art, especially the BCD devices, which are caused by the sharp corners at the STI corners formed in the STI process and / or the pits formed by excessive corrosion of the STI top edge, resulting in local gate oxide being too thin, leading to device performance degradation.

[0006] To achieve the above-mentioned and other related purposes, the present application provides a method for preparing a power device, comprising the steps of:

[0007] Providing a silicon substrate, forming a well region of a first conductivity type, a drift region of a second conductivity type located in the well region, and a shallow trench isolation structure located in the drift region in the silicon substrate, wherein a liner isolation layer is formed between the shallow trench isolation structure and the silicon substrate, and an implantation window is defined on the drift region, the implantation window being adjacent to the shallow trench isolation structure and exposing the silicon substrate through the implantation window;

[0008] Performing ion implantation on the implantation window of the drift region to form a destructive layer mainly composed of amorphous silicon on the surface of the silicon substrate corresponding to the implantation window;

[0009] A thermal oxidation process is performed on a region corresponding to the damaged layer to form a high-voltage gate oxide layer in the implantation window, wherein the high-voltage gate oxide layer is adjacent to the shallow trench isolation structure.

[0010] Optionally, the ions implanted into the implantation window of the drift region include several ions selected from oxygen ions, nitrogen ions, silicon ions and germanium ions.

[0011] More optionally, the ion implantation dose is 1E14-1E16, and the implantation energy is 10 KeV-100 KeV.

[0012] Optionally, forming a well region, a drift region and a shallow trench isolation structure in the silicon substrate includes the following steps:

[0013] Performing ion implantation on the silicon substrate to form the well region in the silicon substrate;

[0014] Performing photolithographic etching on the silicon substrate to form a shallow trench in the silicon substrate region;

[0015] forming the liner isolation layer on the surface of the shallow trench;

[0016] Filling an insulating layer on the surface of the silicon substrate and in the shallow trench;

[0017] Performing a surface planarization process to remove the insulating layer outside the shallow trench, the shallow trench filled with the insulating layer is the shallow trench isolation structure, and the upper surface of the shallow trench isolation structure is not lower than the upper surface of the silicon substrate;

[0018] Performing ion implantation on the well region to form a drift region in the well region;

[0019] Wherein, before and / or after the surface planarization treatment, the method further includes performing an annealing treatment on the silicon substrate.

[0020] Optionally, during the annealing process, the annealing temperature is 200° C.-1200° C., the annealing gas includes nitrogen, oxygen, water vapor and hydrogen peroxide, and the annealing time is 10 min-4 h.

[0021] Optionally, before forming the shallow trench, an oxide layer and an etch stop layer are formed in sequence on the surface of the silicon substrate, and the shallow trench penetrates the etch stop layer and the oxide layer and extends into the silicon substrate, and the high-voltage gate oxide layer formed extends from one end of the shallow trench isolation structure to below the etch stop layer.

[0022] Optionally, the oxide layer is a silicon oxide layer, the etch stop layer is a silicon nitride layer, and the thickness of the silicon nitride layer is 200 nm-500 nm.

[0023] Optionally, the step of forming the liner isolation layer on the surface of the shallow trench isolation structure includes:

[0024] forming a first isolation layer on the surface of the shallow trench isolation structure by a deposition process;

[0025] removing the first isolation layer by a wet etching process;

[0026] The liner isolation layer is formed on the surface of the shallow trench isolation structure by a deposition process.

[0027] More optionally, the thickness of the first isolation layer is the same as the thickness of the liner isolation layer.

[0028] As an example, the first isolation layer and the pad isolation layer include several types of layers selected from the group consisting of a polysilicon layer, a silicon dioxide layer, a silicon nitride layer, and a silicon oxynitride layer, and each layer has a thickness of 50 angstroms to 500 angstroms.

[0029] The present application also provides a power device, which is prepared according to the method described in any of the above solutions.

[0030] As described above, the power device and preparation method thereof of the present application have the following beneficial effects: the improved process design of the present application adds an additional ion implantation process before forming the high-voltage gate oxide layer so that the silicon lattice of the silicon substrate at the corresponding implantation window is damaged to a certain extent, forming a damage layer mainly composed of amorphous silicon, which can improve the oxidation efficiency during local oxidation of silicon, thereby achieving the purpose of passivating the sharp corners of the shallow trench isolation structure and increasing the gate oxide thickness at the junction of the corners of the shallow trench isolation structure and the high-voltage gate oxide layer, which helps to improve the performance of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figures 1 to 3 Shown is a partial process schematic diagram of the method for preparing a power device provided in Example 1 of the present application.

[0032] Figures 4 to 6 Shown is a partial process schematic diagram of the method for preparing a power device provided in Example 2 of the present application.

[0033] Figures 7 to 8 Shown is a partial process schematic diagram of the method for preparing a power device provided in Example 3 of the present application.

[0034] Component number description

[0035] 11 Well region

[0036] 12 Drift Zone

[0037] 121 Injection Window

[0038] 122 Destruction Layer

[0039] 13 Shallow Trench Isolation Structure

[0040] 131 shallow groove

[0041] 132 insulation layer

[0042] 14 High voltage gate oxide layer

[0043] 15 Pad isolation layer

[0044] 16 Etch stop layer

[0045] 17 Oxide layer

[0046] 18 First isolation layer DETAILED DESCRIPTION

[0047] The following describes the implementation methods of the present application through specific specific examples. Those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. The present application can also be implemented or applied through other different specific implementation methods. The details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. For example, when describing the embodiments of the present application in detail, for the sake of convenience, the cross-sectional views showing the device structure will not be partially enlarged according to the general proportion, and the schematic views are only examples, which should not limit the scope of protection of the present application. In addition, in actual production, the three-dimensional dimensions of length, width and depth should be included.

[0048] For convenience, spatially relative terms such as "under," "below," "below," "below," "above," and "on" may be used herein to describe the relationship of one element or feature to other elements or features shown in the drawings. It will be understood that these spatially relative terms are intended to encompass orientations of the device in use or operation in addition to the orientation depicted in the drawings. Additionally, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

[0049] In the context of the present application, a structure described as a first feature being "above" a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature is formed between the first and second features, such that the first and second features may not be in direct contact.

[0050] It should be noted that the diagrams provided in this embodiment are merely schematic illustrations of the basic concept of this application. Therefore, the diagrams only show components relevant to this application and are not drawn according to the number, shape, and size of components in actual implementation. In actual implementation, the type, quantity, and proportion of each component may be varied arbitrarily, and the component layout may be more complex. To minimize the illustrations, not all structures are labeled in the drawings.

[0051] See also Figures 1 to 8 .

[0052] Example 1

[0053] like Figures 1 to 3 As shown, the present application provides a method for preparing a power device, which is particularly suitable for preparing a BCD device. The preparation method comprises the following steps:

[0054] A silicon substrate is provided, and a well region 11, a drift region 12 located in the well region 11, and a shallow trench isolation structure 13 located in the drift region 12 are formed in the silicon substrate. A liner isolation layer 15 is formed between the shallow trench isolation structure 13 and the silicon substrate. An injection window 121 is defined on the drift region 12. The injection window 121 is adjacent to the shallow trench isolation structure 13, and the injection window 121 exposes the silicon substrate. The conductivity types of the well region 11 and the drift region 12 can be the same or different, for example, the well region 11 is N-type and the drift region 12 is P-type, or the well region 11 is P-type and the drift region 12 is N-type, or both the well region 11 and the drift region 12 are N-type or both are P-type. In this embodiment, taking the example of the well region 11 being an N-type well and the drift region 12 being a P-type drift region 12, the silicon substrate is correspondingly a P-type silicon substrate; the structural diagram obtained in this step is shown in Figure 1, from Figure 1 It can be seen that pits and sharp corners are formed on the top of the shallow trench isolation structure 13, which are usually formed during the etching process and are usually difficult to avoid. However, the present application can avoid the adverse effects of the pits and sharp corners on device performance through improved process design. Please continue to refer to the subsequent content for details.

[0055] After forming the structures including the well region 11, the drift region 12 and the shallow trench isolation structure 13 in the silicon substrate, ion implantation is performed on the implantation window 121 of the drift region 12. The implanted ions will cause a certain degree of damage to the silicon lattice of the surface layer of the silicon substrate in the corresponding implantation window 121, thereby forming a damage layer 122 mainly composed of amorphous silicon on the surface of the silicon substrate corresponding to the implantation window 121. The structure obtained after this step is as follows: Figure 2 As shown;

[0056] Next, the region corresponding to the damage layer 122 is subjected to thermal oxidation treatment. For example, the structure obtained after forming the damage layer 122 is placed in a furnace tube device and subjected to a high-temperature dry oxidation or wet oxygen process to form a high-voltage gate oxide layer (HV GOX) 14 in the implantation window 121. The high-voltage gate oxide layer 14 is adjacent to the shallow trench isolation structure 13. The structure obtained after this step is as follows: Figure 3 shown.

[0057] The improved process design of the present application adds an additional ion implantation process before forming the high-voltage gate oxide layer so that the silicon lattice of the silicon substrate at the corresponding implantation window is damaged to a certain extent, forming a damage layer mainly composed of amorphous silicon (Amorphous Si). This can improve the oxidation efficiency during the local oxidation of silicon (LOCOS), thereby passivating the sharp corners of the shallow trench isolation structure and improving the interface between the corner of the shallow trench isolation structure and the high-voltage gate oxide layer (such as Figure 3 The purpose of the gate oxide thickness (indicated by the circle) is to prevent local breakdown and leakage of the device, which helps to improve the performance of the device.

[0058] In a preferred embodiment, the ions implanted into the implantation window 121 of the drift region 12 include oxygen ions, nitrogen ions, silicon ions, and germanium ions. For example, the implanted ions may be one, two, or more. The ion implantation in this step is typically performed at a low temperature, for example, at a temperature below 200° C. Preferably, the ion implantation dose is 1E14 to 1E16, and the implantation energy is 10 KeV to 100 KeV.

[0059] As an example, Figures 1 to 3 As shown, the preparation method further includes the steps of forming an oxide layer 17 and an etch stop layer 18 on the surface of the silicon substrate, and the formed shallow trench isolation structure 13 penetrates the oxide layer 17 and the etch stop layer 18 and extends into the silicon substrate.

[0060] It should be noted that the preparation method of the power device also includes the steps of forming other structures such as active areas, but since this part of the content is not the focus of the application, the preparation process of this part of the application is basically the same as the existing technology and will not be elaborated in detail.

[0061] Example 2

[0062] like Figures 4 to 6 As shown, this embodiment provides another method for preparing a power device, comprising the steps of:

[0063] A silicon substrate is provided, and a well region 11, a drift region 12 located within the well region 11, and a shallow trench isolation structure 13 located within the drift region 12 are formed within the silicon substrate. A liner isolation layer 15 is formed between the shallow trench isolation structure 13 and the silicon substrate, i.e., the liner isolation layer 15 is formed on the surface of the shallow trench isolation structure 13. An implantation window 121 is defined in the drift region 12, adjacent to the shallow trench isolation structure 13, and exposed from the silicon substrate. It should be noted that, in this embodiment, the shallow trench isolation structure 13 is formed within the silicon substrate first, followed by the drift region 12.

[0064] A high voltage gate oxide layer 14 is formed in the implantation window 121 , wherein the high voltage gate oxide layer 14 is adjacent to the shallow trench isolation structure 13 ;

[0065] The step of forming the liner isolation layer 15 on the surface of the shallow trench isolation structure 13 includes: forming a first isolation layer 18 on the surface of the shallow trench isolation structure 13 by a deposition process, more precisely, forming the first isolation layer 18 on the surface of the shallow trench, because the shallow trench has not been filled at this time, and after forming the first isolation layer 18, the following is obtained: Figure 4 The structure shown in FIG. 1 is then removed by a wet etching process to obtain the structure shown in FIG. Figure 5 Next, the deposition process is again used to form the liner isolation layer 15 on the surface of the shallow trench isolation structure 13, to obtain Figure 6 The structure shown in FIG. 1 is then filled with the shallow trench to obtain the shallow trench isolation structure 13. After this step, the oxide layer 17 and the etching stop layer 16 corresponding to the injection window 121 are usually removed by etching to obtain the injection window 121. Figure 1 In the structure shown, the implantation window 121 exposes the silicon substrate.

[0066] In this embodiment, the first isolation layer formed by the first deposition is removed by wet method, and then a new isolation layer is formed as a liner isolation layer by a second deposition process, so that the corners of the shallow trench isolation structure 13 (such as Figure 6 The sharp corners (indicated by the circle in the figure) are further passivated and rounded, which is beneficial to eliminating the sharp corners when growing the high-voltage gate oxide layer later. It can also avoid defects such as local breakdown and leakage of the device, and help improve the electrical performance of the device.

[0067] As an example, the first isolation layer 18 and the pad isolation layer 15 include, but are not limited to, several types of layers, such as polysilicon, silicon dioxide, silicon nitride, and silicon oxynitride. To simplify the process, a single-structured film layer is preferred, for example, both being silicon oxide layers. Of course, the materials of the two layers can also be different. The formation process for both depends on their specific materials. For example, if both are silicon oxide layers, thermal oxidation is preferred, while if they are silicon nitride layers, vapor deposition can be used.

[0068] In a preferred example, the thickness of the first isolation layer and the thickness of the liner isolation layer 15 are the same, and are both 50 angstroms to 500 angstroms, for example, both are 100 angstroms.

[0069] The preparation method of the power device provided in this embodiment is basically the same as the existing preparation method of the power device except for the special treatment of forming the liner isolation layer through the steps of deposition-wet etching-re-deposition, and the other steps and structural features are not elaborated in detail.

[0070] Example 3

[0071] like Figures 7 to 8 As shown, this embodiment provides another method for preparing a power device, comprising the steps of:

[0072] A silicon substrate is provided, and a well region 11, a drift region 12 located within the well region 11, and a shallow trench isolation structure 13 located within the drift region 12 are formed within the silicon substrate. A liner isolation layer 15 is formed between the shallow trench isolation structure 13 and the silicon substrate, i.e., the liner isolation layer is formed on the surface of the shallow trench isolation structure 13. An implantation window 121 is defined in the drift region 12, adjacent to the shallow trench isolation structure 13, and exposed from the silicon substrate. It should also be noted that, in this embodiment, the shallow trench isolation structure 13 is formed within the silicon substrate first, followed by the drift region 12.

[0073] A high voltage gate oxide layer 14 is formed in the implantation window 121 , wherein the high voltage gate oxide layer 14 is adjacent to the shallow trench isolation structure 13 ;

[0074] The steps of forming the well region 11, the drift region 12 and the shallow trench isolation structure 13 in the silicon substrate include:

[0075] Performing ion implantation on the silicon substrate to form the well region 11 in the silicon substrate. The ion implantation in this step is usually light doping.

[0076] The silicon substrate is photolithographically etched to form a shallow trench in the silicon substrate region. In a typical example, before forming the shallow trench, an oxide layer 17 and an etch stop layer 16 are sequentially formed on the surface of the silicon substrate, wherein the shallow trench penetrates the etch stop layer 16 and the oxide layer 17 and extends into the silicon substrate. The oxide layer 17 is preferably a silicon oxide layer, and the etch stop layer 16 is preferably a silicon nitride layer. The thickness of the silicon nitride layer is preferably 200 nm to 500 nm.

[0077] forming the liner isolation layer 15 on the surface of the shallow trench 131;

[0078] The insulating layer 132 is filled on the surface of the silicon substrate and in the shallow trench by a vapor deposition process including but not limited to silicon oxide, silicon oxynitride or other high-K dielectric materials. The insulating layer 132 filled in this step not only fills the shallow trench but also covers the entire surface of the silicon substrate. The structure obtained after this step is as follows: Figure 7 As shown;

[0079] The structure obtained after forming the insulating layer 132 is subjected to a surface planarization process including but not limited to a chemical mechanical polishing process to remove the insulating layer 132 outside the shallow trench. If an etch stop layer is originally formed on the surface of the silicon substrate, the etch stop layer will be exposed after the surface planarization process. The shallow trench filled with the insulating layer 132 is the shallow trench isolation structure 13. The upper surface of the shallow trench isolation structure 13 is not lower than the upper surface of the silicon substrate and is usually flush with or close to the upper surface of the etch stop layer. The structure obtained after this step is as shown in FIG. Figure 8 As shown. Before and / or after the surface planarization treatment, the step of annealing the silicon substrate is also included. In a preferred example, during the annealing treatment, the annealing temperature is 200°C-1200°C, for example, 1050°C, the annealing time is 10 minutes-4 hours, for example, 4 hours, and the annealing gas includes nitrogen, oxygen, water vapor, and hydrogen peroxide gas. Generally, a single gas is preferred, for example, nitrogen is preferred.

[0080] Ion implantation is performed on the well region 11 to form a drift region 12 in the well region 11; after this step, the etching stopper layer and the oxide layer corresponding to the implantation window 121 are usually removed by an etching process to expose the silicon substrate in the implantation window 121 to obtain the following: Figure 1 The structure shown;

[0081] Then, a high voltage gate oxide layer 14 is formed on the silicon substrate corresponding to the injection window 121. The end of the high voltage gate oxide layer 14 away from the shallow trench isolation structure 13 extends to the bottom of the etching stop layer, and a similar Figure 3The structure shown.

[0082] The main difference between the power device fabrication method provided in this embodiment and the prior art lies in the addition of an additional annealing process before the planarization process and / or after the surface planarization process during the formation of the shallow trench isolation structure. The added annealing process can make the shallow trench isolation structure more compact, which also helps eliminate sharp corners during the subsequent growth of the high-voltage gate oxide layer, helps prevent local device breakdown and leakage, and helps improve device performance.

[0083] Example 4

[0084] The present embodiment provides another method for preparing a power device. The difference between the present embodiment and the prior art is that, in the process of preparing the power device, the present embodiment includes not only an additional ion implantation process before forming the high-voltage gate oxide layer 14 so that the silicon lattice of the silicon substrate at the corresponding implantation window 121 is damaged to a certain extent, forming a damage layer 122 mainly composed of amorphous silicon (Amorphous Si), but also a step of forming a liner isolation layer by secondary deposition such as deposition-wet etching-re-deposition, that is, the features of the first and second embodiments are combined at the same time (or, on the basis of the first embodiment, the step of forming a liner isolation layer by secondary deposition steps of deposition-wet removal-re-deposition in the second embodiment is added, or, on the basis of the second embodiment, an additional ion implantation process is added before forming the high-voltage gate oxide layer 14 so that the silicon lattice of the silicon substrate at the corresponding implantation window 121 is damaged to a certain extent, forming a damage layer 122 mainly composed of amorphous silicon (Amorphous Si). Si-based destruction layer 122 accordingly possesses the advantages of both Embodiments 1 and 2. For details, please refer to Embodiments 1 and 2, which will not be described in detail for the sake of brevity. This dual guarantee ensures that sharp corners are eliminated during the growth of the high-voltage gate oxide layer, helping to avoid local device breakdown and leakage, thereby improving device performance.

[0085] Example 5

[0086] This embodiment provides another method for preparing a power device. The difference between this embodiment and the prior art is that, in the process of preparing the power device, this embodiment includes not only adding an additional ion implantation process before forming the high-voltage gate oxide layer 14 so that the silicon lattice of the silicon substrate at the corresponding implantation window 121 is damaged to a certain extent, forming a damage layer 122 mainly composed of amorphous silicon (Amorphous Si), but also includes adding an additional annealing process before and / or after the planarization process in the process of forming the shallow trench isolation structure 13, that is, combining the features of the first embodiment and the third embodiment (or adding the step of adding an additional annealing process before and / or after the planarization process in the process of forming the shallow trench isolation structure 13 in the first embodiment, or adding the step of adding an additional ion implantation process before forming the high-voltage gate oxide layer 14 so that the silicon lattice of the silicon substrate at the corresponding implantation window 121 is damaged to a certain extent, forming a damage layer 122 mainly composed of amorphous silicon (Amorphous Si)). Si-based destruction layer 122 accordingly possesses the advantages of both Embodiments 1 and 3. For details, please refer to Embodiments 1 and 3, which will not be described in detail for the sake of brevity. This dual guarantee ensures that sharp corners are eliminated during the growth of the high-voltage gate oxide layer, helping to avoid local device breakdown and leakage, and thus improving device performance.

[0087] Example 6

[0088] This embodiment provides another method for preparing a power device. The difference between this embodiment and the prior art is that, in the process of preparing the power device, this embodiment includes a step of forming a liner isolation layer by secondary deposition such as deposition-wet etching-redeposition, and also includes an additional annealing process before and / or after the planarization process in the process of forming the shallow trench isolation structure 13. That is, it combines the features of the second and third embodiments (or in other words, it adds the step of adding an additional annealing process before and / or after the planarization process in the process of forming the shallow trench isolation structure 13 in the third embodiment on the basis of the second embodiment, or in other words, it adds the step of forming a liner isolation layer by the steps of deposition-wet etching-redeposition on the basis of the third embodiment). Therefore, it also has the advantages of both the second and third embodiments. For the specific details, please refer to the second and third embodiments, which will not be repeated for the purpose of brevity. Through this dual guarantee, it can be ensured that sharp corners are eliminated when growing the high-voltage gate oxide layer, which helps to avoid local breakdown and leakage of the device and helps to improve device performance.

[0089] Example 7

[0090] This embodiment provides another method for preparing a power device. The difference between this embodiment and the prior art is that, during the process of preparing the power device, this embodiment includes not only an additional ion implantation process before forming the high-voltage gate oxide layer 14 so that the silicon lattice of the silicon substrate at the corresponding implantation window 121 is damaged to a certain extent, forming a damage layer 122 mainly composed of amorphous silicon, but also includes a step of forming a liner isolation layer through a secondary deposition process such as deposition-wet etching-redeposition. It also includes an additional annealing process before and / or after the planarization process during the formation of the shallow trench isolation structure 13. That is, it combines the characteristics of the first, second and third embodiments at the same time, and accordingly also has the advantages of the first, second and third embodiments at the same time. For the specific details, please refer to the first to third embodiments, which will not be repeated for the purpose of brevity. Through this triple guarantee, it can ensure that the sharp corners are eliminated when growing the high-voltage gate oxide layer, which helps to avoid local breakdown and leakage of the device and helps to improve device performance.

[0091] In summary, in the preparation method of the power device provided in the present application, an additional ion implantation process is added before forming the high-voltage gate oxide layer so that the lattice of the silicon substrate at the corresponding implantation window is damaged to a certain extent, forming a damage layer mainly composed of amorphous silicon, and a pad isolation layer is formed by secondary deposition such as deposition-wet etching-re-deposition, and in the process of forming the shallow trench isolation structure, an additional annealing process is added before and / or after the planarization process. These three technical solutions can be used individually or in any combination. However, no matter which method of use is used, compared with the existing technology, it can effectively improve the sharp corner problem during the growth of the high-voltage gate oxide layer, help avoid local breakdown and leakage of the device, and thereby further improve the device performance.

[0092] The present application also provides a power device, which is manufactured according to the method described in any of the above embodiments, and the above content is hereby incorporated by reference in its entirety. The power device is, for example, a BCD device. Depending on the specific manufacturing method employed, the power device provided in the present application may have one or more of the following characteristics compared to the prior art:

[0093] Before forming the high-voltage gate oxide layer, an additional ion implantation process is performed to damage the lattice of the silicon substrate at the corresponding implantation window to a certain extent, forming a damage layer mainly composed of amorphous silicon;

[0094] forming a liner isolation layer through a secondary deposition process of deposition-wet etching-redeposition;

[0095] In the process of forming the shallow trench isolation structure, an additional annealing process is added before and / or after the planarization process.

[0096] Aside from the aforementioned differences, the structure of the power device provided in this embodiment is essentially the same as that of the prior art, including, for example, a well region, a drift region, a shallow trench isolation structure, and a high-voltage gate oxide layer located on the surface of the drift region and adjacent to the shallow trench isolation structure. However, due to its fabrication method provided in this application, the power device provided in this application can effectively avoid defects such as local breakdown and leakage, significantly improving its electrical performance.

[0097] In summary, the present application provides a power device and a method for preparing the same. The preparation method comprises the following steps: providing a silicon substrate, forming a well region, a drift region located within the well region, and a shallow trench isolation structure located within the drift region within the silicon substrate, wherein a liner isolation layer is formed between the shallow trench isolation structure and the silicon substrate, an implantation window is defined on the drift region, the implantation window is adjacent to the shallow trench isolation structure, and the implantation window exposes the silicon substrate; performing ion implantation on the implantation window of the drift region to form a destructive layer mainly composed of amorphous silicon on the surface of the silicon substrate corresponding to the implantation window; and performing thermal oxidation treatment on the region corresponding to the destructive layer to form a high-voltage gate oxide layer within the implantation window, wherein the high-voltage gate oxide layer is adjacent to the shallow trench isolation structure. The improved process design of this application adds an additional ion implantation process before forming the high-voltage gate oxide layer. This process causes a certain degree of damage to the silicon substrate lattice at the corresponding implantation window, forming a damage layer composed primarily of amorphous silicon. This improves the oxidation efficiency during localized silicon oxidation, thereby passivating the sharp corners of the shallow trench isolation structure and increasing the gate oxide thickness at the interface between the shallow trench isolation corner and the high-voltage gate oxide layer, thereby improving device performance. Therefore, this application effectively overcomes the various shortcomings of the existing technology and has high industrial application value.

[0098] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical concepts disclosed in this application shall be covered by the claims of this application.

Claims

1. A method for preparing a power device, characterized in that: Including steps: A silicon substrate is provided, a well region (11), a drift region (12) located in the well region (11), and a shallow trench isolation structure (13) located in the drift region (12) are formed in the silicon substrate, a liner isolation layer (15) is formed between the shallow trench isolation structure (13) and the silicon substrate, an injection window (121) is defined on the drift region (12), the injection window (121) is adjacent to the shallow trench isolation structure (13), and the injection window (121) exposes the silicon substrate; the injection window of the drift region (12) is Ion implantation is performed through the implantation window (121) to form a destructive layer (122) mainly composed of amorphous silicon on the surface of the silicon substrate corresponding to the implantation window (121); wherein the step of forming the liner isolation layer (15) on the surface of the shallow trench isolation structure (13) comprises: forming a first isolation layer (18) on the surface of the shallow trench isolation structure (13) by a deposition process; removing the first isolation layer (18) by a wet etching process; and forming the liner isolation layer (15) on the surface of the shallow trench isolation structure (13) by a deposition process; A thermal oxidation process is performed on the region corresponding to the damage layer (122) to form a high-voltage gate oxide layer (14) in the injection window (121), wherein the high-voltage gate oxide layer (14) is adjacent to the shallow trench isolation structure (13).

2. The preparation method according to claim 1, characterized in that The ions implanted into the implantation window (121) of the drift region (12) include several kinds of oxygen ions, nitrogen ions, silicon ions and germanium ions; the ion implantation dose is 1E14-1E16, and the implantation energy is 10Kev-100Kev.

3. The preparation method according to claim 2, characterized in that The conductivity types of the well region (11) and the drift region (12) are the same or different.

4. The preparation method according to claim 1, characterized in that Forming a well region (11), a drift region (12) and a shallow trench isolation structure (13) in the silicon substrate comprises the following steps: Performing ion implantation on the silicon substrate to form the well region (11) in the silicon substrate; Performing photolithographic etching on the silicon substrate to form a shallow trench (131) in the silicon substrate region; forming the liner isolation layer (15) on the surface of the shallow trench (131); Filling an insulating layer (132) on the surface of the silicon substrate and in the shallow trench (131); Performing a surface planarization process to remove the insulating layer (132) outside the shallow trench (131); the shallow trench (131) filled with the insulating layer (132) is the shallow trench isolation structure (13); and the upper surface of the shallow trench isolation structure (13) is not lower than the upper surface of the silicon substrate; Performing ion implantation on the well region (11) to form a drift region (12) in the well region (11); Wherein, before and / or after the surface planarization treatment, the method further includes performing an annealing treatment on the silicon substrate.

5. The preparation method according to claim 4, characterized in that During the annealing process, the annealing temperature is 200° C.-1200° C., the annealing gas includes nitrogen, oxygen, water vapor and hydrogen peroxide gas, and the annealing time is 10 minutes-4 hours.

6. The preparation method according to claim 4, characterized in that Before forming the shallow trench (131), an oxide layer (17) and an etch stop layer (16) are sequentially formed on the surface of the silicon substrate. The shallow trench (131) penetrates the etch stop layer (16) and the oxide layer (17) and extends into the silicon substrate. The formed high-voltage gate oxide layer (14) extends from one end of the shallow trench isolation structure (13) to below the etch stop layer (16).

7. The preparation method according to claim 6, characterized in that The oxide layer (17) is a silicon oxide layer, the etching stop layer (16) is a silicon nitride layer, and the thickness of the silicon nitride layer is 200nm-500nm.

8. The preparation method according to any one of claims 1 to 7, characterized in that The first isolation layer (18) and the liner isolation layer (15) include several types of polysilicon layer, silicon dioxide layer, silicon nitride layer and silicon oxynitride layer, and the thickness of each layer is 50 angstroms to 500 angstroms.

9. A power device, characterized in that: The power device is prepared according to the method according to any one of claims 1 to 8.

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