Output drive circuit for power module and drive circuit system using the same

Abstract

An output drive circuit uses a thinner oxide thickness process for its high-voltage transistor. Through the design of the high-voltage transistor's front-end circuit, the voltage withstand level between the high-voltage transistor's gate and source can be adjusted downward, while the voltage withstand level between the drain and source can still reach 25 volts without affecting the characteristic specifications of the output end.

Description

Technical Field

[0001] The present invention relates to an output drive circuit for a power component and a drive circuit system using the same, and in particular to an output drive circuit with a smaller circuit area (or larger drive current) and a thinner oxide layer of a high-voltage transistor and a drive circuit system using the same. Background Art

[0002] Power components such as MOSFETs, IGBTs, SJs (super junctions), SiC, and GaN are currently widely used in power electronics systems. Driver chips are often the key to controlling the power components' on and off functions. To achieve optimal efficiency, power component specifications are selected. For example, for a 1kW output, a 25V / 40A or 200V / 5A power component might be selected. The corresponding driver chip voltage and drive current specifications will vary. Insufficient driver chip capacity can lead to decreased system efficiency and increased power component temperature (increased chip junction temperature, TJ).

[0003] Please refer to Figure 1 , Figure 1 This is a schematic diagram of a common power supply circuit system. Power supply circuit system 1 includes two power transistors HQ and LQ, a driver chip 11, an external diode BD, and a capacitor C. One terminal of driver chip 11 is connected to system voltage VCC to obtain supply voltage. Driver chip 11 receives input signals HIN and LIN and outputs drive signals HO and LO to control the on / off switching of power transistors HQ and LQ. Driver chip 11 also includes a logic control circuit 111 and two output driver circuits 112 and 113. Logic control circuit 111 receives input signals HIN and LIN and generates switch control signals for output driver circuits 112 and 113, enabling them to output drive signals HO and LO, respectively.

[0004] To drive power transistors HQ and LQ, their parasitic gate capacitances must be charged. Therefore, the drive currents of the drive signals HO and LO output by output driver circuits 112 and 113 must be sufficiently large to successfully turn on power transistors HQ and LQ. The drive current is related to the area of ​​the transistors in driver circuits 112 and 113. Therefore, increasing the area of ​​these transistors to achieve sufficient drive current has traditionally been a common practice. However, this increased area not only increases chip cost but also limits chip packaging.

[0005] Figure 2 is a schematic diagram of an output drive circuit of the prior art, and the circuit architecture of the drive circuits 112 and 113 can refer to Figure 2Output driver circuit 2, amplifier stage modules 21, 22, and output stage module 23. Amplifier stage modules 21, 22 are used to amplify the switch control signal V_IN, wherein amplifier stage module 21 is composed of amplifiers A4-A6 connected in series, and amplifier stage module 22 is composed of amplifiers A1-A3 connected in series. When the system voltage VCC is generally 10-20 volts, the high-voltage transistors HV_PMOS and HV_NMOS of the output stage module 23 must be three-terminal high-voltage components that can withstand voltages above 20 volts to generate a high-current drive signal DRVOUT for the parasitic gate capacitor COUT.

[0006] To improve withstand voltage, the high-voltage transistors HV_PMOS and HV_NMOS use materials with larger spacing and thicker (deeper) layers. However, given the same width as the low-voltage transistors, the saturation current of the high-voltage transistors HV_PMOS and HV_NMOS is smaller. Therefore, to further increase the drive current, the area of ​​the high-voltage transistors HV_PMOS and HV_NMOS must be increased. Summary of the Invention

[0007] According to the purpose of the present invention, an embodiment of the present invention provides an output drive circuit, comprising a high-voltage transistor pair including a first P-type high-voltage transistor and a second N-type high-voltage transistor, wherein the source and drain of the first high-voltage transistor are electrically connected to a system voltage and the drain of the second high-voltage transistor, respectively, and the source of the second high-voltage transistor is electrically connected to a ground voltage, and the drains of the first high-voltage transistor and the second high-voltage transistor are configured to output a drive signal, wherein the withstand voltages between the gates and the sources of the first high-voltage transistor and the second high-voltage transistor are respectively a first limiting voltage and a second limiting voltage, and the first limiting voltage and the second limiting voltage are respectively related to the oxide thickness of the gates of the first high-voltage transistor and the second high-voltage transistor; a voltage clamping circuit electrically connected to the gate of the first high-voltage transistor, receiving a switching control signal, and outputting a first signal not less than a voltage difference between the system voltage and the first limiting voltage to control the on and off of the first high-voltage transistor; and a conversion circuit electrically connected to the gate of the second high-voltage transistor, receiving the switching control signal, and outputting a second signal not exceeding the second limiting voltage to control the on and off of the second high-voltage transistor.

[0008] Optionally, the first limit voltage and the second limit voltage may be the same, that is, the oxide layer thickness of the gate of the first high-voltage transistor is the same as the oxide layer thickness of the gate of the second high-voltage transistor.

[0009] According to the purpose of the present invention, an embodiment of the present invention provides a driving circuit system, comprising the aforementioned output driving circuit; and a logic control circuit electrically connected to the output driving circuit to provide the switch control signal.

[0010] Optionally, the driving circuit system can be integrated into a single chip to form a driving chip.

[0011] In summary, the output driving circuit provided by the embodiment of the present invention has a larger driving current compared to a traditional output driving circuit of the same area, or, compared to a traditional output driving circuit of the same area, has a smaller area.

[0012] To further understand the technology, means and effects of the present invention, reference may be made to the following detailed description and accompanying drawings, which may provide a thorough and specific understanding of the purposes, features and concepts of the present invention. However, the following detailed description and accompanying drawings are intended only to provide a reference and illustration of the implementation of the present invention and are not intended to limit the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The accompanying drawings are provided to help those skilled in the art to which the present invention pertains to further understanding of the present invention and are incorporated into and constitute a part of the specification of the present invention. The accompanying drawings illustrate exemplary embodiments of the present invention and, together with the specification of the present invention, are used to explain the principles of the present invention.

[0014] Figure 1 This is a schematic diagram of a common power supply circuit system.

[0015] Figure 2 is a schematic diagram of an output drive circuit in the prior art.

[0016] Figure 3 FIG. 4 is a schematic diagram of an output drive circuit according to an embodiment of the present invention.

[0017] Figure 4 FIG. 4 is a schematic diagram of an output driving circuit according to another embodiment of the present invention.

[0018] Figure 5 FIG. 4 is a schematic diagram of an output driving circuit according to another embodiment of the present invention.

[0019] Figure 6 FIG. 4 is a schematic diagram of an output driving circuit according to another embodiment of the present invention.

[0020] The symbols indicated in the diagram are explained as follows: 1 power supply circuit system; 11 driver chip; 111 logic control circuit; 112, 113, 2 to 6 output driver circuits; 21, 22 amplifier stage module; 23 output stage module; 31, 41, 51, 61 voltage clamping circuit; 32, 42, 52, 62 conversion circuit; 33, 43, 53, 63 high-voltage transistor pairs; A1 to A6, G1 to G5 amplifiers; BD diodes; C capacitor; CS current source; COUT parasitic gate capacitance; INV1, INV2 inverters; HIN, LIN input signals; HO, LO, DRVOUT drive signals; HQ, LQ power transistors; HV_PMOS, HV_NMOS high-voltage transistors; Q1 to Q7 transistors; R1 resistor; V_IN switch control signal; VCC system voltage; VL limit voltage; ZD Zener diode. DETAILED DESCRIPTION

[0021] Reference will now be made in detail to exemplary embodiments of the present invention, which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals will be used in the drawings and the description to refer to the same or similar parts. The exemplary embodiments are merely one example of how the present invention may be implemented, and the following examples are not intended to limit the present invention.

[0022] The embodiment of the present invention provides an innovative technical solution that can increase the output current of the driving circuit system and reduce the area of ​​the circuit, thereby obtaining significant related benefits. In the embodiment of the present invention, the high-voltage transistor uses a thinner oxide layer thickness process. For example, the oxide layer thickness (gate oxide layer thickness, hereinafter referred to as oxide layer thickness) of a high-voltage transistor with a typical withstand voltage of 25 volts is about (90 nanometers), but the oxide layer thickness of a low-voltage transistor with a withstand voltage of 5 volts is about Although the oxide layer thickness of the high-voltage transistor used in the embodiment of the present invention is relatively thin, the design of the high-voltage transistor's front-end circuit allows the gate-source withstand voltage of the high-voltage transistor to be adjusted downward, while the drain-source withstand voltage can still reach 25 volts without affecting the output characteristics.

[0023] Furthermore, taking the withstand voltage between the gate and the source as 5 volts and the system voltage as 15 volts as an example, the front-end circuit connected to the gate of the N-type high-voltage transistor in the high-voltage transistor can be a conversion circuit with a maximum output voltage of 5 volts, and the front-end circuit connected to the gate of the P-type high-voltage transistor in the high-voltage transistor can be a voltage clamping circuit, which is used to clamp the voltage of the gate of the P-type high-voltage transistor in the high-voltage transistor so that it is not less than 10 volts. In this way, the high-voltage transistor with a thinner oxide layer thickness can be protected. At the same time, under the same channel width, the saturation current value of the high-voltage transistor with a thinner oxide layer thickness is three times that of the high-voltage transistor with a general oxide layer thickness. Therefore, the technical solution of the embodiment of the present invention can reduce the circuit area and increase the drive current.

[0024] Next, please refer to the present invention Figure 3 , Figure 3 Schematic diagram of an output driver circuit according to an embodiment of the present invention. The output driver circuit 3 is used in a driver circuit system (the driver circuit system can be an integrated chip, but is not limited thereto) to control the on and off of power transistors outside the driver circuit system. The output driver circuit 3 comprises a voltage clamp circuit 31, a conversion circuit 32, and a high-voltage transistor pair 33. The high-voltage transistor pair 33 comprises a high-voltage transistor HV_PMOS (a P-type high-voltage transistor) and an HV_NMOS (an N-type high-voltage transistor). The source of the high-voltage transistor HV_PMOS is electrically connected to the system voltage VCC, the gate of the high-voltage transistor HV_PMOS is electrically connected to the output of the voltage clamp circuit 31, and the drain of the HV_PMOS is electrically connected to the drain of the high-voltage transistor HV_NMOS. The gate of the high-voltage transistor HV_NMOS is electrically connected to the output end of the conversion circuit 32, the source of the high-voltage transistor HV_NMOS is electrically connected to the ground voltage, and the drain of the high-voltage transistor HV_NMOS and the drain of the high-voltage transistor HV_PMOS are electrically connected to the gate of a power transistor outside the driving circuit system to output a driving signal DRVOUT, wherein the current of the driving signal DRVOUT is used to charge and discharge the parasitic gate capacitance COUT of the power transistor.

[0025] The conversion circuit 32 is used to receive the switch control signal V_IN and amplify the switch control signal V_IN. The conversion circuit 32 can be an inverting or non-inverting amplifier or buffer circuit, or a conversion circuit with logic gates or other circuit components, and the present invention is not limited thereto. The conversion circuit 32 receives the limit voltage VL as the supply voltage (it can also receive a voltage lower than the limit voltage VL as the supply voltage), and the maximum voltage value of the amplified switch control signal V_IN will not exceed the limit voltage VL. In this embodiment, the conversion circuit 32 has multiple amplifiers G1, G2 and G3 connected in series, and the signal that each amplifier G1, G2 and G3 can output will not exceed the limit voltage VL, for example, 5 volts. In an embodiment of the present invention, the high-voltage transistor HV_NMOS is selected to use a thinner oxide layer thickness. The withstand voltage between its drain and source is still a high voltage, for example, 25 volts, and the withstand voltage between its gate and source is the limit voltage VL (the limit voltage VL is related to the oxide layer thickness). For example, the oxide layer thickness is about At about 12 nm, the limit voltage VL is 5 V. Thus, the voltage difference between the gate and source of the high-voltage transistor HV_NMOS will not exceed the limit voltage VL, so that the high-voltage transistor HV_NMOS is protected.

[0026] The voltage clamp circuit 31 receives the switch control signal V_IN and the system voltage VCC, wherein the system voltage is between 10 and 20 volts, for example, 15 volts, and the voltage clamp circuit 31 uses the system voltage VCC as a supply voltage. In the embodiment of the present invention, the high voltage transistor HV_PMOS also uses a thinner oxide layer thickness. The withstand voltage between its drain and source is still a high voltage, for example, 25 volts, and the withstand voltage between its gate and source is a limit voltage VL (the limit voltage VL is related to the oxide layer thickness). For example, the oxide layer thickness is about 100 volts. (12 nanometers), the limiting voltage VL is 5 volts. The voltage clamp circuit 31 is designed to output a clamp voltage not lower than the voltage value of VCC-VL (for example, 10 volts) to prevent the voltage difference between the gate and source of the high-voltage transistor HV_PMOS from exceeding the withstand voltage between the gate and source of the high-voltage transistor HV_PMOS, thereby protecting the high-voltage transistor HV_PMOS. The oxide layer thickness of the high-voltage transistor HV_PMOS and HV_NMOS is about When the thickness of the oxide layer is about 12 nanometers, the output current of the high-voltage transistors HV_PMOS and HV_NMOS in this embodiment is three times that of the high-voltage transistors with a general oxide layer thickness. Therefore, the technical solution of the embodiment of the present invention can indeed reduce the circuit area and increase the driving current.

[0027] Please refer to Figure 4 , Figure 4FIG. 1 is a schematic diagram of an output drive circuit according to another embodiment of the present invention. In this embodiment, the output drive circuit 4, the voltage clamp circuit 41, the conversion circuit 42 and the high-voltage transistor pair 43 are the same as Figure 3 The conversion circuit 32 and the high-voltage transistor pair 33 are not described in detail.

[0028] The voltage clamp circuit 41 comprises amplifiers G4 and G5, an N-type transistor Q1, a resistor R1, and a Zener diode ZD. Amplifiers G4 and G5 are connected in series, with amplifier G4 receiving a switch control signal V_IN and amplifier G5 outputting a switch control signal V_IN amplified by amplifiers G4 and G5. Because amplifiers G4 and G5 receive a limit voltage VL as their supply voltage, the maximum voltage of the amplified switch control signal V_IN does not exceed the limit voltage VL, for example, 5 volts. The gate of transistor Q1 is electrically connected to amplifier G5 to receive the amplified switch control signal V_IN. The source of transistor Q1 is electrically connected to ground, and the drain of transistor Q1 is electrically connected to one end of resistor R1. The cathode of Zener diode ZD is electrically connected to system voltage VCC, and the anode of Zener diode ZD is electrically connected to the other end of resistor R1 and the gate of high-voltage transistor HV_PMOS.

[0029] Due to the existence of Zener diode ZD, once the gate voltage of high voltage transistor HV_NMOS is less than VCC-V ZD , the gate voltage of the high voltage transistor HV_PMOS will be clamped at VCC-V ZD , where V ZD Indicates the breakdown voltage of the Zener diode ZD. By selecting the breakdown voltage V ZD is less than or equal to the limit voltage VL, that is, the voltage difference between the gate and the source of the high-voltage transistor HV_PMOS will not exceed the limit voltage VL, so that the high-voltage transistor HV_PMOS can be protected.

[0030] Please refer to Figure 5 , Figure 5 FIG is a schematic diagram of an output drive circuit according to another embodiment of the present invention. In this embodiment, the output drive circuit 5, the voltage clamp circuit 51, the conversion circuit 52 and the high-voltage transistor pair 53, wherein the conversion circuit 52 and the high-voltage transistor pair 53 are the same as Figure 3 The conversion circuit 32 and the high voltage transistor pair 33 are not described in detail. The voltage clamp circuit 51, amplifiers G4, G5, N-type transistor Q1, resistor R1 and multiple transistors Q2, Q3, Q4 used as diodes. Figure 4The difference is that a plurality of transistors Q2, Q3, and Q4 functioning as diodes are used instead of the Zener diode ZD, wherein the drain of the transistor Q2 is electrically connected to the system voltage VCC, and the source of the transistor Q4 is electrically connected to the other end of the resistor R1 and the gate of the high-voltage transistor HV_PMOS.

[0031] Due to the presence of multiple transistors Q2, Q3, and Q4 used as diodes, once the gate voltage of the high-voltage transistor HV_NMOS is less than VCC-V th1 -V th2 -V th3 , the gate voltage of the high voltage transistor HV_PMOS will be clamped at VCC-V th1 -V th2 -V th3 , where V th1 、V th2 、V th3 Represents the threshold voltage of transistors Q2, Q3, and Q4. By selecting the total threshold voltage V of transistors Q2, Q3, and Q4 th1 +V th2 +V th3 is less than or equal to the limit voltage VL, that is, the voltage difference between the gate and the source of the high-voltage transistor HV_PMOS will not exceed the limit voltage VL, so that the high-voltage transistor HV_PMOS can be protected.

[0032] Please refer to Figure 6 , Figure 6 FIG. 1 is a schematic diagram of an output drive circuit according to another embodiment of the present invention. The output drive circuit 6, the voltage clamp circuit 61, the conversion circuit 62 and the high-voltage transistor pair 63, the high-voltage transistor pair 63 and Figure 3 The high voltage transistor pair 33 is the same, so it is not described in detail. Figure 3 In the embodiment, the conversion circuit 62 includes an inverter INV1, whose output voltage does not exceed a limit voltage VL, for example, 5 volts. The input of the inverter INV1 receives the switch control signal V_IN, and the output of the inverter INV1 is used to output an inverted version of the switch control signal V_IN to the gate of the high-voltage transistor HV_NMOS.

[0033] The voltage clamp circuit 61 includes transistors Q1 to Q7, an inverter INV2, a resistor R1, and a current source CS. Transistors Q1 and Q2 are N-type transistors, while transistors Q3 to Q7 are P-type transistors. The sources of transistors Q1 and Q2 are electrically connected to ground. The gates of transistors Q1 and Q2 are electrically connected to the output and input of inverter INV2, respectively. The input of inverter INV2 receives a switch control signal V_IN. Resistor R1 has two terminals electrically connected to a system voltage VCC and the gates of transistors Q3 and Q4, respectively. Current source CS has two terminals electrically connected to ground and one end of the resistor connected to the gates of transistors Q3 and Q4. The drains of transistors Q3 and Q4 are electrically connected to the drains of transistors Q1 and Q2, respectively. The sources of transistors Q3 and Q4 are electrically connected to the drains of transistors Q5 and Q6, respectively. The sources of transistors Q5 and Q6 receive the system voltage VCC, and the gates of transistors Q5 and Q6 are electrically connected to the sources of transistors Q3 and Q4, respectively. The source of transistor Q7 receives the system voltage VCC, the drain of transistor Q7 is electrically connected to the source of transistor Q4 and the gate of high-voltage transistor HV_PMOS, and the gate of transistor Q7 is electrically connected to the gate of transistor Q2.

[0034] Through the above connection method, the transistors Q1 to Q7 and the resistor R1 are configured as a level shifter, so that the voltage on the gate of the high-voltage transistor HV_NMOS is VCC-I*R1+V GSQ4 , where V GSQ4 is the voltage between the gate and source of transistor Q4, and I is the current provided by current source CS. By proper threshold bias design and resistor selection, I*R1-V GSQ4 is less than or equal to the limit voltage VL, that is, the voltage difference between the gate and the source of the high-voltage transistor HV_PMOS will not exceed the limit voltage VL, so that the high-voltage transistor HV_PMOS can be protected.

[0035] Incidentally, while the above description uses an example where the limiting voltage VL of the high-voltage transistors HV_PMOS and HV_NMOS is the same, the present invention is not limited to this. In specific applications, the limiting voltages of the high-voltage transistors HV_PMOS and HV_NMOS are VL1 and VL2, respectively, and the limiting voltages VL1 and VL2 are different. In this case, according to the above-described inventive concept, the conversion circuit only needs to output a signal no higher than the limiting voltage VL2 to control the on and off of the high-voltage transistor HV_NMOS, and the voltage clamping circuit only needs to output a signal no lower than the voltage difference (VCC - VL1) between the system voltage VCC and the limiting voltage VL1 to control the on and off of the high-voltage transistor HV_PMOS.

[0036] In addition, embodiments of the present invention further provide a drive circuit system comprising a drive circuit system, a logic control circuit, and at least one output drive circuit, wherein the logic control circuit is electrically connected to the output drive circuit to provide a switch control signal to the output drive circuit, and the output drive circuit is configured to generate a drive signal DRVOUT based on the switch control signal to a power component (e.g., a power transistor) electrically connected to the drive circuit system. The output drive circuit can be implemented using any of the aforementioned embodiments, and the drive circuit system can be applied to motor systems, charging stations, chargers, or other applications requiring high power.

[0037] In summary, an embodiment of the present invention provides an output drive circuit for use in power components, wherein the high-voltage transistor of the output drive circuit uses a thinner oxide layer, and a corresponding conversion circuit and a voltage clamping circuit are provided to protect the high-voltage transistor. Due to the thinner oxide layer, the output drive circuit can output a higher drive current, or the area of ​​the output drive circuit can be reduced at the same drive current. Accordingly, the technical solution of the present invention can reduce manufacturing costs or reduce the limitation of the packaging area, and can even make a trade-off between area and drive current to obtain a better product as a better solution for the application end of the power component.

[0038] It should be understood that the examples and embodiments described herein are for illustrative purposes only and that various modifications or changes in light thereof will be suggested to those skilled in the art and are to be included within the spirit and purview of this application and the scope of the appended claims.

Claims

1. An output drive circuit, characterized in that: The driving circuit includes: A high-voltage transistor pair, comprising a first P-type high-voltage transistor and an N-type second high-voltage transistor, wherein the source and drain of the first high-voltage transistor are electrically connected to a system voltage and the drain of the second high-voltage transistor, respectively, and the source of the second high-voltage transistor is electrically connected to a ground voltage, and the drains of the first high-voltage transistor and the second high-voltage transistor are used to output a drive signal, wherein a withstand voltage between the gate and the source of the first high-voltage transistor and the second high-voltage transistor is a limit voltage, and the limit voltage is related to the oxide layer thickness of the gate of the first high-voltage transistor and the second high-voltage transistor; a voltage clamping circuit electrically connected to the gate of the first high-voltage transistor, receiving a switch control signal, and outputting a first signal having a voltage difference not less than the system voltage minus the limit voltage to control the on and off of the first high-voltage transistor; and The conversion circuit is electrically connected to the gate of the second high-voltage transistor, receives the switch control signal, and outputs a second signal that does not exceed the limit voltage to control the turning on and off of the second high-voltage transistor.

2. The output drive circuit according to claim 1, wherein: A plurality of first amplifiers are connected in series, and the plurality of first amplifiers receive the limiting voltage as their supply voltage and are used for amplifying the switch control signal so as to transmit the amplified switch control signal to the gate of the second high-voltage transistor.

3. The output drive circuit according to claim 2, wherein: The voltage clamping circuit further includes: a plurality of second amplifiers, first transistors, resistors and Zener diodes connected in series; The plurality of second amplifiers receive the limiting voltage as their supply voltage and are configured to amplify the switch control signal to transmit the amplified switch control signal to the gate of the first transistor. The source of the first transistor is electrically connected to the ground voltage, the drain of the first transistor is electrically connected to one end of the resistor, the cathode of the Zener diode is electrically connected to the system voltage, and the anode of the Zener diode is electrically connected to the other end of the resistor and the gate of the high-voltage transistor.

4. The output drive circuit according to claim 2, wherein: A plurality of second amplifiers, a first transistor, a resistor, and a plurality of second transistors functioning as diodes are connected in series, wherein the plurality of second amplifiers receive the limiting voltage as their supply voltage and are configured to amplify the switch control signal to transmit the amplified switch control signal to the gate of the first transistor. The source of the first transistor is electrically connected to the ground voltage, and the drain of the first transistor is electrically connected to one end of the resistor. The plurality of second transistors are connected in series, the drain of one of the plurality of second transistors is electrically connected to the system voltage, and the source of another of the plurality of second transistors is electrically connected to the other end of the resistor and the gate of the high-voltage transistor.

5. The output drive circuit according to claim 1, wherein: a first inverter, wherein an input terminal of the first inverter receives the switch control signal, and an output terminal of the first inverter is used to output an inverted version of the switch control signal to a gate of the second high-voltage transistor.

6. The output drive circuit according to claim 5, wherein: The voltage clamping circuit is a level converter.

7. The output driving circuit according to claim 1, wherein: The oxide layer thickness of the gates of the first high-voltage transistor and the second high-voltage transistor is 12 nanometers, the limiting voltage is 5 volts, and the system voltage is 15 volts.

8. An output drive circuit, characterized in that: The driving circuit includes: A high-voltage transistor pair comprising a first P-type high-voltage transistor and an N-type second high-voltage transistor, wherein the source and drain of the first high-voltage transistor are electrically connected to a system voltage and the drain of the second high-voltage transistor, respectively, and the source of the second high-voltage transistor is electrically connected to a ground voltage, and the drains of the first high-voltage transistor and the second high-voltage transistor are used to output a drive signal, wherein the withstand voltages between the gate and the source of the first high-voltage transistor and the second high-voltage transistor are respectively a first limiting voltage and a second limiting voltage, and the first limiting voltage and the second limiting voltage are respectively related to the thickness of the oxide layer of the gate of the first high-voltage transistor and the second high-voltage transistor; a voltage clamping circuit electrically connected to the gate of the first high-voltage transistor, receiving a switch control signal, and outputting a first signal having a voltage not less than a voltage difference between the system voltage and the first limit voltage to control the on and off of the first high-voltage transistor; and The conversion circuit is electrically connected to the gate of the second high-voltage transistor, receives the switch control signal, and outputs a second signal that does not exceed the second limit voltage to control the turning on and off of the second high-voltage transistor.

9. A driving circuit system, characterized in that: The driving circuit includes: At least one output driver circuit according to any one of claims 1 to 8; and The logic control circuit is electrically connected to the output drive circuit to provide the switch control signal.

10. The driving circuit system according to claim 9, wherein: The driving circuit system is integrated into a single chip.

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