9t computing-in-memory circuit, multiply-accumulate circuit, compute-in-memory circuit, and chip

Abstract

The application belongs to the technical field of integrated circuits, and particularly relates to a read margin enhanced storage array, a 9T storage and calculation circuit, a multiply-accumulate operation circuit, an in-memory operation circuit based on the 9T storage, and a CIM chip based on the 9T storage. The 9T storage and calculation circuit comprises a basic 6T storage unit and a calculation unit composed of three additional NMOS tubes N5, N6 and N7. The multiply-accumulate operation circuit is further designed on the basis of the aforementioned 9T storage and calculation circuit. The multiply-accumulate operation circuit comprises a calculation array, a current mirror circuit, an input circuit, a current monitoring array and an output circuit according to the function division. Based on the new architecture of the multiply-accumulate operation circuit and the traditional SRAM circuit, the application further provides an in-memory operation circuit based on the 9T storage, and the CIM circuit has the functions of data reading / writing, holding and multiply-accumulate operation. The application solves the problems of the 6T storage only having the data storage function, the operation logic of the existing multiply-accumulate operation circuit being complex, and the operation efficiency being low.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of integrated circuits, and particularly relates to a read margin enhanced memory array, a 9T storage and calculation circuit, a multiply-accumulate operation circuit, an in-memory operation circuit based on 9T SRAM, and a CIM chip based on 9T SRAM. BACKGROUND

[0002] With the rapid development of high-tech such as machine learning, cloud computing, artificial intelligence, the demand for application data is also growing, which also heralds the arrival of the "computing power era". In such an environment, the Von Neumann architecture, as the cornerstone of modern computer structure, is also facing great challenges. The traditional Von Neumann architecture has long been regarded as the paradigm of mainstream computing, in which data and instructions are stored in a common memory and transmitted to the computing unit through a bus. In emerging data-intensive applications (such as machine learning) and edge computing scenarios, due to the significant increase in the scale of computation, the cost of moving data between cache and main memory accounts for a large part of the overall data processing energy consumption. In a sense, the Von Neumann architecture has become the main bottleneck of data processing performance in super-large-scale systems. In order to overcome this problem, scholars in the field of computers and integrated circuits mainly focus on developing solutions based on in-memory computing (CIM). In fact, such solutions bring computing directly into the memory circuit, avoiding most data exchanges with the CPU.

[0003] With the deepening of research, the in-memory computing architecture has become popular and has replaced the traditional Von Neumann architecture on a large scale in many emerging fields, especially for processing artificial neural networks and solving various optimization and mathematical problems in resource movement restricted edge computing devices. Research shows that CIM architecture can embed various functions in memory, thereby significantly reducing memory access and related energy savings. In addition to improving energy efficiency, the CIM architecture also improves computing performance by implementing large-scale parallelism when computing in a bit cell array with a storage array having embedded analog multiply and accumulate (MAC) functions. In addition, CIM can isolate personal data in edge devices (i.e., edge computing) without reading or storing data in the cloud (i.e., cloud computing), thereby greatly reducing privacy and security concerns. Multiplication and multiply-accumulate operations are the most widely used type of operation in applications such as artificial neural networks, so how to develop an in-memory operation circuit that can efficiently handle complex logical operation tasks such as point multiplication and multiply-accumulate operations has become a technical problem that needs to be solved by those skilled in the art. SUMMARY

[0004] In order to solve the problems that the traditional 6T SRAM only has a data storage function, and the existing multiplication and accumulation operation circuit has complex operation logic and low operation efficiency, the present invention provides a 9T storage and calculation circuit, a multiplication and accumulation operation circuit, an in-memory operation circuit based on 9T SRAM, and a CIM chip based on 9T SRAM.

[0005] The present invention is achieved by adopting the following technical solutions:

[0006] A 9T storage-calculation circuit is used as the basic functional unit of a large-scale in-memory arithmetic circuit. This 9T storage-calculation circuit has basic data reading, writing, and holding functions, as well as multiplication functions. Each 9T storage-calculation circuit consists of two PMOS tubes P1 and P2, and seven NMOS tubes N1 to N7. According to functional division, the 9T storage-calculation circuit includes a 6T storage unit and a calculation unit. Among them, P1, P2, N1, N2, N3, and N4 constitute a 6T storage unit. The 6T storage unit is used to store data, and Q and QB are a pair of inverted storage nodes in the 6T storage unit. N5, N6, and N7 constitute a calculation unit; the calculation unit is used to form a basic unit for implementing multiplication operations together with the 6T storage unit.

[0007] In the 9T storage-calculation circuit, the computation unit's circuit connections are as follows: the gate of N5 is connected to the storage node Q, and the gate of N7 is connected to the storage node QB. The source of N5, the drain of N7, and the gate of N6 are connected. The drains of N5 and N6 are connected and connected to the computation line CL. The source of N7 is grounded, and the source of N6 is connected to the inverted signal NIN of the input signal IN.

[0008] In the solution provided by the present invention, the 6T memory cell follows the circuit scheme used in traditional SRAMs. The specific circuit connections are as follows: the gates of N1 and N2 are connected to word line WL; the drain of N1 is connected to bit line signal BL; the source of N1, the gate of P2, the gate of N4, the drain of P1, and the drain of N3 are connected and serve as storage node Q. The drain of N2 is connected to bit line signal BLB; the source of N2, the gate of P1, the gate of N3, the drain of P2, and the drain of N4 are connected and serve as storage node QB. The sources of P1 and P2 are connected to VDD; the sources of N3 and N4 are grounded.

[0009] In the present invention, the 9T memory cell implements data reading, writing, and retention primarily through the 6T memory cell. The specific operating logic is as follows: WL controls the opening of N1 and N2 to perform read and write control. PMOS transistors P1 and P2 and NMOS transistors N3 and N4 form two cross-coupled inverters to latch the potential at the Q and QB nodes, thereby storing and retaining the corresponding data.

[0010] As a further improvement of the present application, the operation process of the 9T storage unit to realize the multiplication operation needs the joint participation of the calculation unit and the 6T storage unit, and the specific operation logic is as follows:

[0011] I. The operand pre-storage stage

[0012] The word line WL is turned on, and the first operand is written into the storage node Q of the 9T storage and calculation circuit in the data writing mode through the bit lines BL and BLB.

[0013] II. The operation stage

[0014] The current signal I is filled into the calculation line CL in the calculation mode, and the inverse signal NIN of the second operand IN is input into the 9T storage and calculation circuit through the source of N6. Among them, the high level state of IN represents that the second operand is 1, and the low level state of IN represents that the second operand is 0.

[0015] Then, whether there is a current signal flowing into the drain of N5 and N6 of the calculation line CL is detected, and the current conduction between CL and the 9T storage and calculation circuit is identified as I F As the calculation result of the multiplication operation, that is, I F = Q * IN.

[0016] The present application also includes a multiply-accumulate operation circuit for performing multiply-accumulate operation. The multiply-accumulate operation circuit is further designed on the basis of the aforementioned 9T storage and calculation circuit, and the multiply-accumulate operation circuit includes a calculation array, a current mirror circuit, an input circuit, a current monitoring array, and an output circuit according to the functional division.

[0017] Among them, the calculation array is composed of a plurality of 9T storage and calculation circuits arranged in columns; all the 9T storage and calculation circuits are connected with the bit lines BL, BLB and the calculation line CL; and each 9T storage and calculation circuit is connected with a word line WL for controlling the opening.

[0018] The current mirror circuit is used to fill the current signal I required in the operation stage into the calculation line CL.

[0019] The input circuit is composed of a plurality of inverters arranged in columns, and each inverter corresponds to a 9T storage and calculation circuit in rows. Each inverter is used to output a corresponding inverse signal NIN to the source of N6 in the 9T storage and calculation circuit according to the input signal IN.

[0020] The current monitoring circuit is composed of three NMOS tubes M5, M6 and M7 connected in the same circuit connection relationship as the calculation unit N5, N6 and N7 in the 9T storage and calculation circuit, and the current monitoring circuit is connected to the calculation line CL and simulates the signal state of the calculation unit when the product result is 1. The current monitoring circuit is used to divide the current signal I flowing into each calculation unit with the product result of 1 in the calculation line CL in the operation stage.

[0021] The output circuit is used to collect the shunt signal ΔI flowing into the current monitoring circuit, and output the corresponding multiply-accumulate operation result N according to the proportional relationship between the shunt signal ΔI and the injected current signal I:

[0022] In the multiply-accumulate operation circuit provided by the application, the current mirror circuit is composed of four PMOS tubes M1, M2, M3 and M4. The circuit connection relationship is as follows: the sources of M1 and M2 are connected to VDD; the gate of M1, the drain of M1, the gate of M2, and the source of M3 are connected. The drain of M2 is connected to the source of M4; the gate and the drain of M3 are both connected to the gate of M4; the drain of M3 is the output end of the reference current I REF . The drain of M4 is the output end of the replica current I and is connected to the calculation line CL.

[0023] In the multiply-accumulate operation circuit provided by the application, the circuit connection relationship of the current monitoring circuit is as follows: the gate of M5 is connected to the high-level control signal OPEN=1.2V, and the gate of N7 is connected to the low-level control signal NOPEN=0V. The source of M5, the drain of M7 and the gate of M6 are connected. The drains of M5 and M6 are connected and connected to the calculation line CL; the source of M7 is connected to the ground, and the source of M6 is connected to the inverted signal NIN output by the input circuit.

[0024] As a further improvement of the application, the operation logic of the multiply-accumulate operation circuit performing multiply-accumulate operation is as follows:

[0025] I. Pre-storing stage of operation number

[0026] According to the number of the first operation number in the multiply-accumulate operation, n word lines WL0-WL n-1 are selected in turn, and each first operation number Q0-Q n-1 is written into the storage node in each row of the 9T storage and calculation circuit in the data writing mode through the corresponding bit line BL and BLB.

[0027] II. Operation stage

[0028] In the operation mode, the second operation number IN0-IN n-1 required by each 9T storage and calculation circuit is synchronously input into each inverter in the input circuit. At the same time, the current signal I is injected into the calculation line CL through the current mirror circuit, and the shunt signal ΔI flowing into the current monitoring circuit is collected by the output circuit. Finally, the corresponding multiply-accumulate operation result N is output:

[0029]

[0030] The application also comprises an in-memory computing circuit based on 9T SRAM, which comprises a computing array, a bit line group, a computing line group, a word line group, an input circuit, a current mirror circuit, a current monitoring circuit, an output circuit, a pre-charge circuit, a word line conversion circuit, a row decoding module, a column decoding module, and a control circuit.

[0031] The computing array is arranged in the form of N rows and M columns by a plurality of 9T computing circuits as described above.

[0032] The bit line group comprises M bit lines BL0-BLM. M-1 and M bit lines BLB0-BLBM. M-1 Each 9T computing circuit in each column in the computing array is connected to the same bit line group BL and BLB.

[0033] The computing line group comprises M computing lines CL0-CLM. M-1 Each 9T computing circuit in each column in the computing array is connected to the same computing line CL.

[0034] The word line group comprises N word lines WL0-WLN. N-1 Each 9T computing circuit in each row in the computing array is connected to the same word line WL.

[0035] The input circuit is arranged in columns by at least N+1 inverters. The input ends of the first N inverters are connected to the input signal IN corresponding to the first operand, and the output ends are connected to the source of N6 in the 9T computing circuit corresponding to the row. The last inverter is connected to a current monitoring circuit and keeps the output at a low level state during the operation stage.

[0036] The current mirror circuit is used to fill the computing line CL corresponding to the operation stage with the current signal I required for multiplication or multiply-accumulate operation. The basic functional unit of the current mirror circuit is composed of four PMOS tubes M1, M2, M3, and M4. The sources of M1 and M2 are connected to VDD; the gate of M1, the drain of M1, the gate of M2, and the source of M3 are connected. The drain of M2 is connected to the source of M4; the gate and drain of M3 are connected to the gate of M4; the drain of M3 is the output end of the reference current I REF ; and the drain of M4 is the output end of the replica current I and is connected to the computing line CL.

[0037] The current monitoring array is arranged by M current monitoring circuits in rows. Each current monitoring circuit is connected to the calculation line; the current monitoring circuit is used for dividing the current signal I flowing into each calculation unit with a product result of 1 in the calculation stage of the calculation line CL. The current monitoring circuit is composed of three NMOS tubes M5, M6 and M7; the gate of M5 is connected to the high-level control signal OPEN = 1.2V, and the gate of N7 is connected to the low-level control signal NOPEN = 0V. The source of M5, the drain of M7 and the gate of M6 are connected; the drains of M5 and M6 are connected and connected to the calculation line CL. The source of M7 is grounded, and the source of M6 is connected to the signal output by the input circuit, which is usually low.

[0038] The output circuit includes M groups of data reading units and operation result quantization units. The data reading unit is used to output the data Q stored in the 9T storage and calculation circuit according to the bit line voltage in the data read / write mode. The operation result quantization unit collects the shunt signal ΔI flowing into the current monitoring circuit in the operation mode, and outputs the corresponding operation result N.

[0039] The precharge circuit is used for precharging the selected bit lines BL and BLB in the bit line group.

[0040] The word line conversion circuit is used for controlling the opening of each word line WL.

[0041] The row decoding module is connected with the word line conversion circuit, and the decoding module is used for decoding the address signal and transmitting it to the word line conversion circuit.

[0042] The column decoding module is used for selecting each bit line group, and then combining the row decoding module and the word line conversion circuit to select any 9T storage and calculation circuit to perform corresponding data reading / writing or operation operation.

[0043] The control circuit includes a timing control module, a mode control module and a read / write control module. The timing control module is used for generating various clock signals required in the data reading / writing, multiplication operation or multiplication and accumulation operation process. The mode control module is used for switching the working mode of the 9T storage-based in-memory operation circuit, and the working mode includes a storage mode and an operation mode. The read / write control module is used for controlling the process of performing data reading / writing operation on the circuit.

[0044] The application also includes a 9T storage-based CIM chip, which is an integrated circuit and is packaged by the aforementioned 9T storage-based in-memory operation circuit.

[0045] The technical scheme provided by the application has the following beneficial effects:

[0046] The application designs a new 9T storage and calculation circuit structure on the basis of a 6T SRAM storage unit, and the 9T storage and calculation circuit can realize relatively complex multiplication operation on the basis of not affecting the data reading and writing and data retention function of the original 6T SRAM storage unit, by using a newly added calculation line CL and three NMOS tubes.

[0047] The application also provides a new multiply-accumulate operation circuit structure and a 9T SRAM-based in-memory operation circuit on the basis of the newly designed 9T storage and calculation circuit.

[0048] The circuit provided by the application has the advantage that the operation process is simple in operation logic, and the multiplication operation of the calculation units in different rows in the same column can be processed in parallel, so that the multiply-accumulate operation task including a large number of operation numbers can be completed in a short period. BRIEF DESCRIPTION OF DRAWINGS

[0049] Figure 1 The circuit diagram of the 9T storage and calculation circuit provided in embodiment 1 of the application.

[0050] Figure 2 The circuit connection and signal flow direction diagram of the 9T storage and calculation circuit provided in embodiment 1 of the application in the process of performing different multiplication operations.

[0051] Figure 3 The circuit architecture diagram of the multiply-accumulate operation circuit provided in embodiment 2 of the application.

[0052] Figure 4 The circuit connection and signal flow direction diagram of the multiply-accumulate operation circuit provided in embodiment 2 of the application in the process of performing multiplication and accumulation operations,

[0053] Figure 5 The waveform diagram of each signal of the multiply-accumulate operation circuit in embodiment 2 of the application in the process of performing multiplication and accumulation operations.

[0054] Figure 6 The module block diagram of the 9T SRAM-based in-memory operation circuit provided in embodiment 3 of the application. DETAILED DESCRIPTION

[0055] In order to make the objects, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and should not be used to limit the present application.

[0056] Embodiment 1

[0057] The embodiment provides a 9T computing-in-memory circuit, which is used as a basic functional unit of a large-scale computing-in-memory circuit. The 9T computing-in-memory circuit has basic data reading, writing and holding functions, and a multiplication operation function. As shown in the figure, each 9T computing-in-memory circuit is composed of two PMOS tubes P1 and P2 and seven NMOS tubes N1 to N7. According to the functional division, the 9T computing-in-memory circuit includes a 6T storage unit and a computing unit. Figure 1

[0058] It can be seen that in the 9T computing-in-memory circuit, P1, P2, N1, N2, N3 and N4 constitute a 6T storage unit. The 6T storage unit is used for storing data, and Q and QB are a pair of reverse storage nodes in the 6T storage unit. Specifically, in the scheme of the embodiment, the 6T storage unit uses the circuit scheme in the conventional SRAM, and the specific circuit connection relationship is as follows: the gates of N1 and N2 are connected to the word line WL. The drain of N1 is connected to the bit line signal BL, and the source of N1, the gate of P2, the gate of N4, the drain of N3 and the drain of N3 are connected and serve as the storage node Q. The drain of N2 is connected to the bit line signal BLB, and the source of N2, the gate of P1, the gate of N3, the drain of P2 and the drain of N4 are connected and serve as the storage node QB. The sources of P1 and P2 are connected to VDD; the sources of N3 and N4 are connected to the ground. Figure 1 The remaining three NMOS tubes N5, N6 and N7 constitute a computing unit; the computing unit is used to constitute a basic unit for implementing multiplication operation together with the 6T storage unit. Specifically, the circuit connection relationship of the computing unit is as follows: the gate of N5 is connected to the storage node Q, and the gate of N7 is connected to the storage node QB; the source of N5, the drain of N7 and the gate of N6 are connected, and the drains of N5 and N6 are connected and connected to the computing line CL. The source of N7 is connected to the ground, and the source of N6 is connected to the inverted signal NIN of the input signal IN.

[0059]

[0060] ​​The 9T memory cell provided in the embodiment still realizes data reading, writing and holding based on the basic 6T memory cell, and thus the specific operation logic is still the same as the conventional method, specifically as follows: the opening of N1 and N2 is controlled by WL to perform read and write control. The PMOS transistors P1 and P2 and the NMOS transistors N3 and N4 constitute two cross-coupled inverters to realize the latching of potentials at the Q and QB nodes, and then store and hold the corresponding data;

[0061] In particular, in the 9T memory cell provided in the embodiment, the operation process for realizing the multiplication operation needs the cooperation of the calculation unit and the 6T memory cell, and the specific operation logic is as follows:

[0062] I. Pre-storing of operands

[0063] The word line WL is turned on, and the first operand is written to the storage node Q of the 9T memory and calculation circuit in the data writing mode through the bit lines BL and BLB.

[0064] II. Operation stage

[0065] In the calculation mode, the current signal I is filled into the calculation line CL, and the inverse signal NIN of the second operand IN is input into the 9T memory and calculation circuit through the source of N6. The high level state of IN represents that the second operand is 1, and the low level state of IN represents that the second operand is 0.

[0066] Then, it is detected whether there is a current signal flowing into the drains of N5 and N6, and the current conduction between CL and the 9T memory and calculation circuit is identified as I F As the calculation result of the multiplication operation, that is, I F = Q × IN.

[0067] In order to better display the logic and principle of the circuit realizing the multiplication operation in the embodiment, the following further description is made in combination with Figure 2 . Figure 2 The middle column of contains four different 9T memory and calculation circuits, and each 9T memory and calculation circuit is performing four different multiplication operation processes of 1 × 1, 0 × 1, 1 × 0 and 0 × 0 from top to bottom. Figure 2 The left side of is a plurality of inverters, which are used to generate the inverse signal NIN according to the input signal IN, and the inverse signal NIN is directly input into the right side 9T memory and calculation circuit to complete the multiplication operation, thereby constituting the source of the second operand IN in the multiplication operation. Figure 2 The right side of is a partial amplification and current flow direction diagram of the calculation unit during the execution of the multiplication operation stage by the middle 9T memory and calculation circuits.

[0068] In combination with Figure 2It can be seen that in the multiplication operation, the 6T storage units in the 9T storage and calculation circuit have been pre-written with the first operand Q required by the multiplication operation. In order from top to bottom, Q0=1 in the first 9T storage and calculation circuit, Q1=1 in the second 9T storage and calculation circuit, Q2=0 in the third 9T storage and calculation circuit, and Q3=1 in the fourth 9T storage and calculation circuit.

[0069] Then, the second operand IN is input into each inverter on the left, and the combination of Figure 2 It can be seen that in order from top to bottom, IN0=1 in the first inverter, so MIN0=0. IN1=0 in the second inverter, so MIN1=1. IN2=1 in the third inverter, so MIN2=0. IN3=0 in the fourth inverter, so MIN3=1.

[0070] Next, the calculation unit performs the operation. For the first row: in the state of Q0=1 and QB0=0, N1 is on and N2 is off; when the input IN0=1, NIN0=0, N3 forms a diode connection type, and N3 is always in the saturation region, so the current on CL can flow into the 9T storage and calculation unit. At this time, I F is recorded as the current conduction identifier between the calculation line CL and the 9T storage and calculation circuit, so I F =1; correspondingly, I F is taken as the multiplication result, so it can be seen that I F =Q×IN is established in the current state, and the operation 1×1=1 is completed.

[0071] For the second row: in the state of Q1=1 and QB1=0, N4 is on and N5 is off; when the input IN1=0, NIN1=1, since NIN1 is high, the source-drain of N6 is reversed, so that the gate-source of N6 is connected in high resistance state, at this time no current flows in. I F =0. Correspondingly, I F is taken as the multiplication result, so it can be seen that I F =Q×IN is established in the current state, and the operation 1×0=0 is completed.

[0072] For the third and fourth rows: in the state of Q2=0 and QB2=1, N7 is off and N8 is on; at this time, the gate of N9 will be grounded through N8, so that N9 is off, no matter whether the input IN2 is 0 or 1, no current will flow in, I F =0. That is, the case of Q3=0 and IN3=0 is the same as the case of Q2=0 and IN2=1. Correspondingly, I F is taken as the multiplication result, so it can be seen that I F =Q×IN is established in the state of the third row and the fourth row, and the operations 0×1=0 and 0×0=0 are completed respectively.

[0073] In summary: Figure 2 The truth table of the circuit in performing multiplication is as follows:

[0074] Table 1: Multiplication truth table of the 9T storage circuit in this embodiment

[0075] Q QB IN NIN I F ]] 1 0 1 0 1 1 0 0 1 0 0 1 1 0 0 0 1 0 1 0

[0076] Based on the above content, it can be seen that the 9T storage and calculation circuit provided in this embodiment is a new circuit designed on the basis of the traditional 6T storage cell, which has both data reading, writing and holding functions and multiplication functions. The circuit turns on the current conduction flag I between the calculation line and the added 3T calculation unit part. F As the output of the multiplication result, it will not affect the data reading, writing and retention functions of the 6T storage unit part. It is a new solution for the basic circuit part of the storage and calculation circuit for performing complex logical operations such as multiplication and multiplication and accumulation, and has high practical value.

[0077] Example 2

[0078] Based on the 9T storage-calculation circuit with multiplication function provided in Example 1, this embodiment further provides a multiplication-accumulation circuit with a new architecture. This circuit implements fast and efficient multiplication-accumulation operations. In this circuit, regardless of the data size of the multiplication-accumulation operation, only two operation cycles are required to complete the operation.

[0079] Specifically, such as Figure 3 As shown, the multiplication-accumulation circuit provided in this embodiment generally includes five parts according to the functions: a calculation array, a current mirror circuit (Current Mirror), an input circuit, a current monitoring circuit (Current Monitor Cell), and an output circuit.

[0080] The computation array is composed of multiple 9T memory-computation circuits from Example 1 arranged in columns; all 9T memory-computation circuits are connected to bit lines BL and BLB and computation lines CL; and each 9T memory-computation circuit is connected to a word line WL for controlling its activation. In practical applications, the number of 9T memory-computation circuits in a column can be determined based on the maximum number of supported multiplication-accumulation operands.

[0081] The current mirror circuit is used to fill the current signal I required in the operation stage to the corresponding calculation line CL when performing multiplication operation (only 1 row is opened) or multiply-accumulate operation (multiple rows are opened at the same time). The current mirror circuit in the embodiment is composed of four PMOS tubes M1, M2, M3 and M4. The specific circuit connection relationship is as follows: the source electrodes of M1 and M2 are connected to VDD; the gate electrode of M1, the drain electrode of M1, the gate electrode of M2 and the source electrode of M3 are connected. The drain electrode of M2 is connected to the source electrode of M4; the gate electrode and the drain electrode of M3 are connected to the gate electrode of M4; the drain electrode of M3 is the output terminal of the reference current I REF ; the drain electrode of M4 is the output terminal of the copied current I and is connected to the calculation line CL.

[0082] The input circuit is arranged in columns by a plurality of inverters, and each inverter corresponds to a 9T storage and calculation circuit in rows. Each inverter is used to output a corresponding inverted signal NIN to the source electrode of N6 in each 9T storage and calculation circuit performing operation according to the input signal IN.

[0083] The current monitoring circuit is connected in the same circuit connection relationship as the calculation unit N5, N6 and N7 in the 9T storage and calculation circuit, and is connected to the calculation line CL and simulates the signal state of the calculation unit when the product result is 1. The current monitoring circuit is used to divide the current signal I flowing into each calculation unit with the product result of 1 in the calculation line CL in the operation stage.

[0084] Specifically, the circuit connection relationship of the current monitoring circuit is as follows: the gate electrode of M5 is connected to the high-level control signal OPEN=1.2V, and the gate electrode of N7 is connected to the low-level control signal NOPEN=0V. The source electrode of M5, the drain electrode of M7 and the gate electrode of M6 are connected; the drain electrodes of M5 and M6 are connected and connected to the calculation line CL. The source electrode of M7 is connected to the ground, and the source electrode of M6 is connected to the signal output by the input circuit, which is usually low level.

[0085] The output circuit is used to collect the shunt signal ΔI flowing into the current monitoring circuit, and output the corresponding multiply-accumulate operation result N according to the proportional relationship between the shunt signal ΔI and the filled current signal I:

[0086] In the multiply-accumulate operation circuit provided in the embodiment, the operation logic for performing multiply-accumulate operation is as follows:

[0087] I. Pre-storing stage of the operation number

[0088] According to the number of the first operation number in the multiply-accumulate operation, n word lines WL0-WL n-1 are selected in turn, and each first operation number Q0-Qn-1 .

[0089] II. Operation phase

[0090] In the operation mode, the second operand IN0~IN n-1 .

[0091] Meanwhile, the current signal I is filled into the calculation line CL through the current mirror circuit, and the shunt signal ΔI flowing into the current monitoring circuit is collected by the output circuit.

[0092] The final output corresponds to the multiply-accumulate operation result N:

[0093]

[0094] The principle of the multiply-accumulate operation circuit provided in the embodiment can be described in combination with Figure 4 In the circuit, Figure 4 It can be known from the content in the foregoing embodiments that in the "single-column" calculation array composed of a plurality of 9T storage and calculation circuits designed in the embodiment, each 9T storage and calculation circuit will keep conducting with the calculation line CL when the product result is 1, and then the current signal I on the calculation line will be "shunted" to each 9T storage and calculation circuit. The shunt signal in each 9T storage and calculation circuit can be denoted as ΔI. Since the structures and conducting states of all the 9T storage and calculation circuits are consistent, and all are connected in parallel on the calculation line CL, the shunt signals ΔI are also the same in size. In this state, as long as the proportional relationship between the shunt signal ΔI and the original current signal I is determined, it can be known how many 9T storage and calculation circuits have the multiplication operation result of 1, and the multiply-accumulate operation result N is also obtained.

[0095] On this basis, considering that the shunt signal ΔI flowing into each 9T storage and calculation circuit is difficult to measure directly, the multiply-accumulate operation circuit designed in the embodiment separately adds a "3T calculation unit" as a "current monitoring circuit". The current monitoring circuit is also connected in parallel on the calculation line CL and keeps synchronous with the calculation unit in the 3T calculation unit with the product of 1. At this time, the current monitoring circuit can also "shunt" a part of the shunt signal ΔI from the calculation line CL.

[0096] Further, the output circuit in the embodiment can use a sensitive amplifier to detect the size of the "shunted" shunt signal ΔI in the current monitoring circuit, and then calculate the final multiply-accumulate operation result N through a hardware or software method, that is:

[0097]

[0098] Combined with the above, it can be seen that the operation process of the multiplication and accumulation circuit provided by this embodiment includes two steps: the pre-storage stage and the calculation stage. Therefore, the operation process of the circuit is fast and efficient. Specifically, during the operation process, the change process of each signal is roughly as follows: Figure 5 As shown. Combined Figure 5 It can be seen that in the data prediction (wirte) stage: the word lines WL0~WL n-1 Open, and precharge the corresponding column bit line BL to a high level, and write the corresponding first operands Q0~Q n-1 Then in the next computing stage, since the circuit signal I is first injected into the calculation line CL, the current monitoring current in the conductive state with CL is very high. When the second operands IN0 to IN1 are input through the inverter, the current signal ΔI is very high. n-1 Then, multiple different computing units will also remain connected to CL. At this time, the shunt signal ΔI will gradually decrease from a higher original value to a lower value based on the calculation result. Ultimately, the result of the multiplication and accumulation operation can be determined based on the decrease in ΔI.

[0099] It can be seen from this that in the circuit of this embodiment, as long as the pre-storage process of the first operand is completed and multiple second operands are input synchronously, the multiplication and accumulation operation process and the output of the result can be directly implemented within one cycle, and the operation process and the quantization process of the operation result are very efficient.

[0100] It's important to note that during the pre-storage phase, although all 9T storage circuits are connected to the same set of bit lines BL and BLB, the values ​​of the storage nodes Q in each 9T storage circuit cannot be written all at once. During the operation, the first operand must be written sequentially in different cycles. This may result in longer multiplication and accumulation cycles and lower efficiency.

[0101] However, the actual situation is not like this. Because the 6T storage unit in each 9T storage circuit has a data retention function, and the multiplication and accumulation operation process does not affect the data of the storage node. Therefore, the circuit can write multiple different first operands into different 9T storage circuits, and then directly select the 9T storage circuit corresponding to the required second operand to participate in the operation when performing the multiplication and accumulation operation. The operation logic at this time changes to:

[0102] 1. Operation unit selection stage

[0103] According to the first operand of the required operation, the 9T storage and calculation circuits in each row that have pre-stored relevant data are selected to participate in the operation.

[0104] 2. Operational Stage

[0105] The second operation number is input to each 9T storage and calculation circuit, and the current signal I is filled into the calculation line CL; then the shunt signal ΔI is collected and the operation result is output.

[0106] At this time, the new multiply-accumulate operation logic changes the process of sequentially writing the data pre-storing stage to each first operation number into the process of one-time selecting the appropriate 9T storage and calculation circuit to be started. The starting of the word lines WL of different rows can be completed synchronously. Therefore, the multiply-accumulate operation circuit provided in the embodiment can still realize the multiply-accumulate operation of a large-scale operation number in the shortest two periods.

[0107] It can be seen that, compared with most conventional schemes, the new circuit architecture proposed in the embodiment has the advantages of rapidness and high efficiency in multiply-accumulate operation.

[0108] Embodiment 3

[0109] Based on the new architecture of the multiply-accumulate operation circuit proposed in Embodiment 2, the embodiment further provides a 9Tstram-based in-memory operation circuit (CIM). The CIM circuit is introduced into the multiply-accumulate operation architecture in Embodiment 2 in a large-scale storage circuit based on 6Tstram, so that the CIM circuit has the functions of data reading / writing and data holding. The CIM circuit can realize simple multiplication operation and complex multiply-accumulate operation. A prominent advantage of the 9Tstram-based in-memory operation circuit provided in the embodiment is high efficiency and fast speed in executing the multiply-accumulate operation function.

[0110] Specifically, as shown in Figure 6 Fig. 1, the 9Tstram-based in-memory operation circuit provided in the embodiment includes a storage and calculation array, a bit line group, a calculation line group, a word line group, an input circuit, a current mirror circuit, a current monitoring array, an output circuit, a pre-charge circuit, a word line conversion circuit, a row decoding module, a column decoding module, and a control circuit.

[0111] The storage and calculation array is arranged in the form of N rows and M columns by a plurality of 9T storage and calculation circuits as in Embodiment 1. The number N of rows of 9T storage and calculation circuits in the array determines the maximum operation number scale of the multiply-accumulate operation that can be supported by the circuit. The number N of columns determines the number of tasks of data reading / writing or multiply-accumulate operation that can be completed in parallel by the circuit.

[0112] The bit line group includes M bit lines BL0-BLM M-1 and M bit lines BLB0-BLBM M-1 Each 9T storage and calculation circuit in each column in the storage and calculation array is connected to the same bit line group BL and BLB. The calculation line group includes M calculation lines CL0-CLM M-1Each 9T storage and calculation circuit in each column in the storage and calculation array is connected to the same calculation line CL. The word line group includes N word lines WL0-WL N-1 Each 9T storage and calculation circuit in each row in the storage and calculation array is connected to the same word line WL.

[0113] The current mirror circuit is used to fill the current signal I required in the operation stage into the corresponding calculation line CL when performing multiplication or multiply-accumulation operation. The basic functional unit of the current mirror circuit is composed of four PMOS tubes M1, M2, M3 and M4. The sources of M1 and M2 are connected to VDD; the gate of M1, the drain of M1, the gate of M2 and the source of M3 are connected. The drain of M2 is connected to the source of M4; the gate and the drain of M3 are both connected to the gate of M4; the drain of M3 is the output end of the reference current I REF ; and the drain of M4 is the output end of the copied current I and is connected to the calculation line CL.

[0114] The current monitoring array is arranged in rows by M current monitoring circuits, each of which is connected by three NMOS tubes M5, M6 and M7 in the same circuit connection relationship as the calculation unit N5, N6 and N7 in the 9T storage and calculation circuit. The current monitoring circuit is connected to the calculation line CL and simulates the signal state of the calculation unit when the product result is 1. The current monitoring circuit is used to divide the current signal I flowing into each calculation unit with the product result of 1 in the calculation line CL in the operation stage.

[0115] The circuit structure of the current monitoring circuit (CMC) is the same as that of the calculation unit in the 9T, and is connected to CL as the 9T. By giving the signal OPEN=1.2V representing the logic high level "1", NOPEN=0V representing the logic low level "0", and NIN=0V being the logic low level "0" output by IN=1.2V representing the logic high level "1" through the inverter, M1 is opened and M2 is turned off, M1 and M3 form a diode connection type, and CMC only uses M1, M2 and M3 three NMOS transistors to act as a conducting 9T unit, reducing the chip area. The circuit connection relationship of CMC is as follows: the gate of M5 is connected to the high-level control signal OPEN=1.2V, and the gate of N7 is connected to the low-level control signal NOPEN=0V. The source of M5, the drain of M7 and the gate of M6 are connected; the drains of M5 and M6 are connected and connected to the calculation line CL. The source of M7 is connected to the ground, and the source of M6 is connected to the signal output by the input circuit, which is usually low.

[0116] The input circuit is arranged in columns by at least N+1 inverters. The inputs of the first N inverters are connected to the input signal IN corresponding to the first operand, and the outputs are connected to the source of N6 in the 9T storage and calculation circuit corresponding to the row. The last inverter is connected to a current monitoring circuit and keeps the output at a low level during the operation stage.

[0117] In the scheme provided by the embodiment, considering that the current monitoring circuit is equivalent to a "redundant 9T storage and calculation circuit", in order to simplify the circuit design, in addition to the first operand of each 9T storage and calculation circuit being assigned by the input circuit, the input circuit also needs to assign the current monitoring circuit, and ensure that the current monitoring circuit is always in a "synchronous" state with the 9T storage and calculation circuit with a product of 1 during the multiply-accumulate operation stage.

[0118] The output circuit includes M groups of data reading units and operation result quantization units. The data reading unit is used to output the data Q stored in the corresponding 9T storage and calculation circuit according to the bit line voltage in the data read / write mode. The operation result quantization unit collects the shunt signal ΔI flowing into the current monitoring circuit in the operation mode, and outputs the corresponding operation result N.

[0119] The pre-charge circuit is used for pre-charging the selected bit lines BL and BLB in the bit line group. The word line conversion circuit is used for controlling the opening of each word line WL. The row decoding module is connected with the word line conversion circuit, and the decoding module is used for decoding the address signal and transmitting it to the word line conversion circuit. The column decoding module is used for selecting each bit line group, and then combining the row decoding module and the word line conversion circuit to select any 9T storage and calculation circuit to perform corresponding data read / write or operation operation.

[0120] The control circuit includes a timing control module, a mode control module and a read / write control module. The timing control module is used to generate various clock signals required in the data read / write, multiplication operation or multiply-accumulate operation process. The mode control module is used to switch the working mode of the 9T storage-based in-memory operation circuit, and the working mode includes a storage mode and an operation mode. The read / write control module is used to control the process of performing data read / write operation on the circuit.

[0121] The 9T storage-based in-memory operation circuit provided by the embodiment can be provided in the form of an integrated circuit chip in actual application. Specifically, the embodiment can also provide a 9T storage-based CIM chip, which is an integrated circuit and is packaged by the aforementioned 9T storage-based in-memory operation circuit.

[0122] In conclusion, the circuit scheme provided by the embodiment can effectively overcome the influence of process fluctuation and improve the success rate of MRAM array read operation. The above description is only the preferred embodiment of the present application and is not intended to limit the present application. Any modification, equivalent replacement and improvement made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A 9T storage-calculation circuit, used as a basic functional unit for large-scale in-memory arithmetic circuits, having basic data read, write, and hold functions, as well as multiplication functions; characterized by: The 9T storage-calculation circuit is composed of two PMOS transistors P1 and P2, and seven NMOS transistors N1 to N7. According to functional division, the 9T storage-calculation circuit includes a 6T storage unit and a calculation unit. Among them, P1, P2, N1, N2, N3, and N4 constitute the 6T storage unit; the 6T storage unit is used to store data, and Q and QB are a pair of inverted storage nodes in the 6T storage unit; N5, N6, and N7 constitute the calculation unit; the calculation unit is used to form a basic unit for implementing multiplication operations together with the 6T storage unit; The circuit connection relationship of the calculation unit is as follows: the gate of N5 is connected to the storage node Q, and the gate of N7 is connected to the storage node QB; the source of N5, the drain of N7 and the gate of N6 are connected, and the drains of N5 and N6 are connected and connected to the calculation line CL; the source of N7 is grounded, and the source of N6 is connected to the inverted signal NIN of the input signal IN; The operation logic of the 9T storage and calculation circuit to realize multiplication operation is: Turn on the word line WL and write the first operand to the storage node Q of the 9T storage circuit through the bit lines BL and BLB in the data write mode; In calculation mode, a current signal I is fed into the calculation line CL, and an inverted signal NIN of the second operand IN is input to the 9T storage circuit through the source of N6; a high level state of IN represents that the second operand is 1, and a low level state of IN represents that the second operand is 0; Then, the calculation line CL is detected to see if there is a current signal flowing into the drain of N5 and N6, and the current conduction flag I between CL and the 9T storage circuit is set. F As the result of the multiplication operation, I F =Q×IN.

2. The 9T storage-calculation circuit according to claim 1, wherein: The circuit connection relationship of the 6T memory cell is as follows: the gates of N1 and N2 are connected to the word line WL; the drain of N1 is connected to the bit line signal BL, the source of N1, the gate of P2, the gate of N4, the drain of P1, and the drain of N3 are connected and serve as the storage node Q; the drain of N2 is connected to the bit line signal BLB, the source of N2, the gate of P1, the gate of N3, the drain of P2, and the drain of N4 are connected and serve as the storage node QB; the sources of P1 and P2 are connected to VDD; the sources of N3 and N4 are grounded.

3. The 9T storage-calculation circuit according to claim 2, wherein: The 9T storage circuit implements the following operational logic for data reading, writing, and retention: WL controls the opening of N1 and N2 to perform read and write control; PMOS transistors P1 and P2 and NMOS transistors N3 and N4 form two cross-coupled inverters to latch the potential at the Q and QB nodes, thereby storing and retaining the corresponding data.

4. A multiplication-accumulation circuit for performing multiplication-accumulation operations; characterized in that: The multiplication-accumulation operation circuit comprises: A computing array, comprising a plurality of 9T memory-computation circuits according to any one of claims 1 to 3 arranged in columns; all 9T memory-computation circuits are connected to bit lines BL, BLB and a computing line CL; and each 9T memory-computation circuit is connected to a word line WL for controlling the opening thereof; a current mirror circuit, configured to inject a current signal I required for the operation phase into the calculation line CL; An input circuit, which is composed of multiple inverters arranged in columns, each inverter corresponding to a 9T storage circuit in a row; each inverter is used to output a corresponding inverted signal NIN to the source of N6 in the 9T storage circuit according to the input signal IN; A current monitoring circuit, comprising three NMOS transistors M5, M6, and M7 connected in the same circuit connection relationship as the computing units N5, N6, and N7 in the 9T storage-calculation circuit, is connected to the computing line CL and simulates the signal state of the computing unit when the multiplication result is 1. The current monitoring circuit is used to evenly distribute the current signal I flowing from the computing line CL to each computing unit whose multiplication result is 1 during the operation phase; and The output circuit is used to collect the shunt signal ΔI flowing out of the current monitoring circuit and output the corresponding multiplication and accumulation operation result N according to the proportional relationship between the shunt signal ΔI and the input current signal I:

5. The multiplication-accumulation circuit according to claim 4, wherein: The current mirror circuit is composed of four PMOS tubes M1, M2, M3, and M4. The circuit connection relationship is as follows: the source of M1 and M2 is connected to VDD; the gate of M1, the drain of M1, the gate of M2, and the source of M3 are connected; the drain of M2 is connected to the source of M4; the gate and drain of M3 are both connected to the gate of M4; the drain of M3 is the reference current I REF The drain of M4 is the output end of the copied current I and is connected to the calculation line CL.

6. The multiplication-accumulation circuit according to claim 4, wherein: The circuit connection relationship of the current monitoring circuit is as follows: the gate of M5 is connected to the high-level control signal OPEN, and the gate of N7 is connected to the low-level control signal NOPEN; the source of M5, the drain of M7 and the gate of M6 are connected; the drains of M5 and M6 are connected and connected to the calculation line CL; the source of M7 is grounded, and the source of M6 is connected to the inverted signal NIN output by the input circuit.

7. The multiplication-accumulation circuit according to claim 4, wherein: The operation logic of the multiplication-accumulation-addition circuit for performing the multiplication-accumulation-addition operation is as follows:

1. Operand Pre-storage Stage Select n word lines WL0~WL1 in sequence according to the number of operands in the multiplication and accumulation operation n-1 The first operands Q0 to Q1 are written to the storage nodes of the 9T storage circuits in each row through the corresponding bit lines BL and BLB in the data write mode. n-1 ; 2. Operational Stage In the operation mode, the second operand IN0~IN1 required by each 9T storage circuit is synchronously input to each inverter in the input circuit. n-1 At the same time, the current signal I is injected into the calculation line CL through the current mirror circuit, and the output circuit collects the shunt signal ΔI flowing into the current monitoring circuit and outputs the corresponding multiplication and accumulation operation result N:

8. A 9T SRAM-based in-memory operation circuit, characterized in that: It includes: A memory and computation array, comprising a plurality of 9T memory and computation circuits as claimed in claim 1 arranged in N rows and M columns; The bit line group includes M bit lines BL0~BL M-1 and M bit lines BLB0~BLB M-1 Each 9T memory circuit in each column of the memory array is connected to the same set of bit lines BL and BLB; The calculation line group includes M calculation lines CL0~CL M-1 Each 9T storage circuit in each column of the storage array is connected to the same calculation line CL; A word line group, which includes N word lines WL0 to WL N-1 Each 9T memory circuit in each row of the memory array is connected to the same word line WL; An input circuit is composed of at least N+1 inverters arranged in columns; the input terminals of the first N inverters are connected to the input signal IN corresponding to the first operand, and the output terminals are connected to the source of N6 in the 9T storage circuit in the corresponding row; the last inverter is used to connect to a current monitoring circuit and keep its output in a low state during the operation phase; A current mirror circuit is used to inject the current signal I required for the operation phase into the corresponding calculation line CL when performing a multiplication operation or a multiplication-accumulation operation. The basic functional unit of the current mirror circuit is composed of four PMOS tubes M1, M2, M3, and M4. The sources of M1 and M2 are connected to VDD; the gate of M1, the drain of M1, the gate of M2, and the source of M3 are connected; the drain of M2 is connected to the source of M4; the gate and drain of M3 are both connected to the gate of M4; the drain of M3 is the reference current I REF The drain of M4 is the output terminal of the copied current I and is connected to the calculation line CL; A current monitoring array is formed by M current monitoring circuits arranged in rows; each current monitoring circuit is connected to a calculation line; the current monitoring circuit is used to evenly distribute the current signal I flowing from the calculation line CL into each calculation unit whose product result is 1 during the operation phase; the current monitoring circuit is composed of three NMOS transistors M5, M6, and M7; the gate of M5 is connected to a high-level control signal OPEN, and the gate of N7 is connected to a low-level control signal NOPEN; the source of M5, the drain of M7, and the gate of M6 are connected; the drains of M5 and M6 are connected and connected to the calculation line CL; the source of M7 is grounded, and the source of M6 is connected to the normally low-level signal output by the input circuit; an output circuit comprising M groups of data reading units and operation result quantization units; the data reading units being configured to output data Q stored in the corresponding 9T storage circuit according to the bit line voltage in a data read / write mode; and the operation result quantization units being configured to collect a shunt signal ΔI flowing into the current monitoring circuit in an operation mode and output a corresponding operation result N; A precharge circuit, which is used to perform a precharge operation on the selected bit lines BL and BLB in the bit line group; A word line switching circuit, which is used to control the opening of each word line WL; A row decoding module connected to the word line conversion circuit, the decoding module is used to decode the address signal and then transmit it to the word line conversion circuit; The column decoding module is used to select each bit line group, and then combines with the row decoding module and word line conversion circuit to select any 9T storage and calculation circuit to perform the corresponding data read / write or calculation operation; as well as The control circuit includes a timing control module, a mode control module and a read-write control module; the timing control module is used to generate the various clock signals required during data read / write, multiplication or multiplication-accumulation operations; the mode control module is used to switch the operating mode of the 9Tsram-based in-memory operation circuit, which includes a storage mode and an operation mode; the read-write control module is used to control the process of the circuit performing data read and write operations.

9. A CIM chip based on 9T SRAM, characterized by: It is encapsulated by the in-memory operation circuit based on 9Tsram as described in claim 8.

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