Interface circuit, memory controller, and method for calibrating multiple signal processing devices

Abstract

The present invention relates to an interface circuit, a memory controller, and a method for calibrating multiple signal processing devices within an interface circuit of a memory controller. The method includes: negotiating an operating mode of the interface circuit in a calibration process with a host device during a link process; and calibrating a characteristic value of a first signal processing device and a characteristic value of a second signal processing device during the calibration process, wherein the first signal processing device is configured on a receive signal processing path to process a receive signal, and the second signal processing device is configured on a transmit signal processing path to process a transmit signal, and the interface circuit operates according to the operating mode during the calibration process.

Description

Technical Field

[0001] The present invention relates to a calibration method for calibrating an interface circuit in a high-speed communication system. Background Art

[0002] A serializer-deserializer (SerDes) is a pair of functional blocks commonly used in high-speed communications to compensate for limited I / O. The SerDes converts data between serial and parallel interfaces in each direction. The primary purpose of a SerDes is to provide data transmission over a single line or differential pair, minimizing the number of I / O pins and interconnect logic.

[0003] SerDes operate at high frequencies. However, high-frequency signal transmission has a low tolerance for frequency or voltage jitter. Therefore, if the characteristic values ​​of the signal processing components within the SerDes shift, this shift may produce undesirable frequency or voltage jitter, which in turn may cause fatal errors in the SerDes' signal processing. Once a fatal error occurs, the system must be powered off or reset, which becomes a serious problem.

[0004] In order to prevent fatal errors in a high-speed communication system, a calibration method for calibrating an interface circuit including a serializer-deserializer in the high-speed communication system is needed. Summary of the Invention

[0005] An object of the present invention is to provide a method for calibrating an interface circuit including a serializer-deserializer in a high-speed communication system. By calibrating characteristic value offsets of signal processing elements in the interface circuit, frequency or voltage jitter is avoided, thereby preventing fatal errors in the high-speed communication system.

[0006] According to one embodiment of the present invention, an interface circuit includes a first signal processing device, a second signal processing device and a correction device. The first signal processing device is configured on a receiving signal processing path to process a receiving signal. The second signal processing device is configured on a transmitting signal processing path to process a transmitting signal. The correction device couples the first signal processing device and the second signal processing device to correct a characteristic value of the first signal processing device and a characteristic value of the second signal processing device in a correction procedure. The first signal processing device is coupled to an external signal receiving path and an internal signal receiving path, and is used to sequentially process a receiving signal received from the external signal receiving path and a receiving signal received from the internal signal receiving path in the correction procedure. The second signal processing device is coupled to the first signal processing device through the internal signal receiving path, and is used to provide the transmitting signal to the first signal processing device in the correction procedure.

[0007] According to another embodiment of the present invention, a memory controller is coupled to a memory device for controlling access to the memory device and includes an interface circuit. The interface circuit is coupled to a host device for communicating with the host device. The interface circuit includes a first signal processing device, a second signal processing device, and a correction device. The first signal processing device is configured on a receive signal processing path for processing a receive signal. The second signal processing device is configured on a transmit signal processing path for processing a transmit signal. The correction device is coupled to the first signal processing device and the second signal processing device for correcting a characteristic value of the first signal processing device and a characteristic value of the second signal processing device in a correction process. The first signal processing device is coupled to an external signal receiving path and an internal signal receiving path, and is configured to sequentially process a receive signal received from the external signal receiving path and a receive signal received from the internal signal receiving path in the correction process. The second signal processing device is coupled to the first signal processing device via the internal signal receiving path, and is configured to provide the transmit signal to the first signal processing device in the correction process.

[0008] According to another embodiment of the present invention, a method is provided for calibrating a plurality of signal processing devices within an interface circuit of a memory controller, wherein the memory controller is coupled to a memory device for controlling access to the memory device, and the memory controller is contained in a data storage device, which is coupled to a host device. The method comprises: negotiating with the host device in a linking procedure an operating mode of the interface circuit in a calibration procedure; and calibrating a characteristic value of a first signal processing device and a characteristic value of a second signal processing device in the calibration procedure, wherein the first signal processing device is configured on a receiving signal processing path for processing a receiving signal, and the second signal processing device is configured on a transmitting signal processing path for processing a transmitting signal, and wherein the interface circuit operates according to the operating mode in the calibration procedure. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 An example block diagram of a data storage device according to an embodiment of the present invention is shown.

[0010] Figure 2 A block diagram of an interface circuit according to an embodiment of the present invention is shown.

[0011] Figure 3 An exemplary block diagram of a signal processing circuit according to an embodiment of the present invention is shown.

[0012] Figure 4 An example block diagram of a calibration device according to an embodiment of the present invention is shown.

[0013] Figure 5 An exemplary flow chart of a calibration procedure controlled by a calibration device according to an embodiment of the present invention is shown.

[0014] Figure 6 An exemplary flow chart of a method for calibrating a plurality of signal processing devices within an interface circuit of a memory controller according to an embodiment of the present invention is shown.

[0015] Figure 7 An exemplary flow chart illustrating a linking procedure performed by a Node A device and a Node B device according to an embodiment of the present invention is shown.

[0016] Figure 8 An example of a data structure of a capability indication command according to an embodiment of the present invention is shown.

[0017] Figure 9 An example of a waveform of a transmission signal transmitted by a device under test and an example of a waveform of a reception signal received by the device under test in an automatic mode of the device under test according to an embodiment of the present invention are shown.

[0018] Figure 10 Shown are waveform examples of the device's transmitted and received signals and waveform examples of the host's transmitted and received signals in a host-device interaction mode according to an embodiment of the present invention.

[0019] Figure 11 Shown are waveform examples of the transmitting signal and the receiving signal of the device and waveform examples of the transmitting signal and the receiving signal of the host in the initial adjustment mode of the host according to one embodiment of the present invention.

[0020] Figure 12 Shown are waveform examples of the device's transmitted and received signals and waveform examples of the host's transmitted and received signals in the device's initial adjustment mode according to an embodiment of the present invention.

[0021]

Explanation of symbols

[0022] 100: Data storage device

[0023] 110:Memory controller

[0024] 112: Microprocessor

[0025] 112C: Program code

[0026] 112M: Read-only memory

[0027] 114:Memory interface

[0028] 116: Buffer memory

[0029] 118:Host interface

[0030] 120: Memory device

[0031] 130,240: Host device

[0032] 132: Encoder

[0033] 134:Decoder

[0034] 200: Interface circuit

[0035] 210, 220, 230, 300: Signal processing circuit

[0036] 301: receiving circuit

[0037] 302: Equalization Circuit

[0038] 303: receiving data buffer circuit

[0039] 304: decoder circuit

[0040] 305: Transmit data buffer circuit

[0041] 306:Serializer

[0042] 307: swing control circuit

[0043] 308: Transmission Circuit

[0044] 309: Low-dropout voltage regulator circuit

[0045] 310: Bandgap filter circuit

[0046] 311:Frequency Synthesis Circuit

[0047] 312: External signal receiving path

[0048] 313: Internal signal receiving path

[0049] 330,400: Calibration device

[0050] 410: trigger detection circuit

[0051] 420: Control circuit

[0052] 430: Exploring the Circuit

[0053] Adjust_RX_Equalization,Adjust_TX_Swing: operation

[0054] ADAPT, ADAPT_1, ADAPT_2: Adaptation cycle

[0055] ESC_PA, ESCParam_PA, MaxHS, PACP_BEGIN, PACP_FunctionID, RxHSG4PrepareLength, RxHSG4SyncLength, RxHsAdaptResfresh, RxHsAdaptInitial: capability parameters

[0056] PACP_CAP_ind, PACP_CAP_EXT1_ind, PACP_CAP_EXT2_ind: Capability indication command

[0057] TADAPT: Time interval corresponding to the adaptation period

[0058] TRG_UPR 0, TRG_UPR 1, TRG_UPR 2: Trigger event message DETAILED DESCRIPTION

[0059] In the following, many specific details are described to provide a thorough understanding of the embodiments of the present invention. However, those skilled in the art will still understand how to implement the present invention in the absence of one or more specific details or in the case of relying on other methods, components or materials. In other cases, well-known structures, materials or operations are not shown or described in detail to avoid obscuring the main concepts of the present invention.

[0060] References throughout this specification to "one embodiment" or "an example" mean that a particular feature, structure, or characteristic described in connection with the embodiment or example is included in at least one of the multiple embodiments of the present invention. Thus, the phrases "in one embodiment of the present invention," "according to an embodiment of the present invention," "in an example," or "according to an example of the present invention" appearing in various places throughout this specification are not necessarily referring to the same embodiment or example. Furthermore, the particular features, structures, or characteristics may be combined in any suitable combinations and / or subcombinations in one or more embodiments or examples.

[0061] Furthermore, to further enhance the understanding of the objectives, features, and advantages of the present invention, specific embodiments of the present invention are described below with reference to the accompanying drawings. These embodiments are intended to illustrate the spirit of the present invention and are not intended to limit its scope. It should be understood that the following embodiments can be implemented using software, hardware, firmware, or any combination thereof.

[0062] Figure 1An example block diagram of a data storage device according to an embodiment of the present invention is shown. Data storage device 100 may include a memory device 120 and a memory controller 110. Memory controller 110 is used to access memory device 120 and control the operation of memory device 120. Memory device 120 may be a non-volatile (NV) memory device (e.g., a flash memory) and may include one or more memory elements (e.g., one or more flash memory dies, one or more flash memory chips, or other similar elements).

[0063] The data storage device 100 may be coupled to a host device 130. The host device 130 may include at least a processor, a power circuit, and at least one random access memory (RAM), such as at least one dynamic random access memory (DRAM), at least one static random access memory (SRAM), etc. (not shown). Figure 1 The processor and random access memory may be interconnected via a bus and may be coupled to a power circuit for power. The processor may control the operation of the host device 130. The power circuit may supply power to the processor, random access memory, and data storage device 100. For example, the power circuit may output one or more driving voltages to the data storage device 100. The data storage device 100 may receive these driving voltages from the host device 130 as power to the data storage device 100 and provide storage space for the host device 130.

[0064] According to one embodiment of the present invention, the host device 130 may issue instructions to the data storage device 100, such as a read instruction or a write instruction, to access data stored in the memory device 120, or the host device 130 may issue instructions to the data storage device 100 to further control and manage the data storage device 100.

[0065] According to one embodiment of the present invention, the memory controller 110 may include a microprocessor 112, a read-only memory (ROM) 112M, a memory interface 114, a buffer memory 116, and a host interface 118. The ROM 112M is used to store program code 112C. The microprocessor 112 is used to execute the program code 112C to control access to the memory device 120. The program code 112C may include one or more program modules, such as a bootloader program code. When the data storage device 100 obtains power from the host device 130, the microprocessor 112 may execute an initialization program for the data storage device 100 by executing the program code 112C. In the initialization program, the microprocessor 112 may load a set of in-system programming (ISP) program codes (not shown) from the memory device 120. Figure 1 The microprocessor 112 can execute the set of in-system programming codes, so that the data storage device 100 can have various functions. According to one embodiment of the present invention, the set of in-system programming codes may include, but are not limited to: one or more program modules related to memory access (e.g., reading, writing, and erasing), such as a read operation module, a table lookup module, a wear leveling module, a read refresh module, a read reclaim module, a garbage collection module, a sudden power off recovery (SPOR) module, and an uncorrectable error correction code (UECC) module, which are respectively provided to perform corresponding operations such as reading, table lookup, wear leveling, read refresh, read reclaim, garbage collection, sudden power off recovery, and error handling for detected UECC errors.

[0066] The memory interface 114 may include an encoder 132 and a decoder 134 . The encoder 132 is used to encode data to be written into the memory device 120 , for example, by performing ECC encoding. The decoder 134 is used to decode data read from the memory device 120 .

[0067] Typically, the memory device 120 includes multiple memory elements, such as multiple flash memory dies or multiple flash memory chips, each of which may include multiple memory blocks. The memory controller 110 performs data erase operations on the memory device 120 in units of blocks. Furthermore, a memory block may record (or include) a specific number of data pages, such as physical data pages, and the memory controller 110 performs data write operations on the memory device 120 in units of data pages.

[0068] In practice, the memory controller 110 may utilize its internal components to perform various control operations, such as utilizing the memory interface 114 to control access operations of the memory device 120 (particularly, access operations to at least one memory block or at least one data page), utilizing the buffer memory 116 to perform required buffering processing, and utilizing the host interface 118 to communicate with the host device 130.

[0069] In one embodiment, the memory controller 110 communicates with the host device 130 via the host interface 118 using a standard communication protocol. For example, the standard communication protocol includes (but is not limited to): the Universal Serial Bus (USB) standard, the SD interface standard, the Ultra High Speed-I (UHS-I) interface standard, the Ultra High Speed-II (UHS-II) interface standard, the CF interface standard, the MMC interface standard, the eMMC interface standard, the UFS interface standard, the Advanced Technology Attachment (ATA) standard, the Serial ATA (SATA) standard, the Peripheral Component Interconnect Express (PCI-E) standard, the Parallel Advanced Technology Attachment (PATA) standard, etc.

[0070] In one embodiment, the buffer memory 116 for providing data buffering is implemented as a random access memory. For example, the buffer memory 116 may be a static random access memory, but the present invention is not limited thereto. In other embodiments, the buffer memory 116 may be a dynamic random access memory.

[0071] In one embodiment, the data storage device 100 may be a portable memory device (e.g., a memory card conforming to the SD / MMC, CF, MS, or XD standards, a USB flash drive, etc.), and the host device 130 may be an electronic device connectable to the data storage device, such as a mobile phone, a laptop, a desktop computer, etc. In another embodiment, the data storage device 100 may be a solid-state drive or an embedded storage device conforming to the UFS or eMMC specifications, and may be installed in an electronic device, such as a mobile phone, a laptop, or a desktop computer. In this case, the host device 130 may be a processor of the electronic device.

[0072] According to one embodiment of the present invention, the host interface 118 of the memory controller 110 may include a serializer-deserializer (SerDes) for processing a receive signal received from the host device and a transmit signal transmitted to the host device to achieve high-speed data transmission between the data storage device 100 and the host device 130.

[0073] Figure 2 The block diagram of the interface circuit according to one embodiment of the present invention is shown. According to one embodiment of the present invention, the interface circuit 200 may be a host interface, which is configured between a predetermined device (e.g., a data storage device) and a host device 240, so that the host device 240 and the predetermined device can communicate with each other through the interface circuit 200 and transmit data signals and control signals. According to one embodiment of the present invention, the interface circuit 200 may be Figure 2 The host interface 118 is shown configured within the memory controller 110 .

[0074] The interface circuit 200 may include signal processing circuits 210, 220, and 230 that operate in accordance with different layer communication protocols. The signal processing circuit 210 may be a physical layer signal processing circuit that processes a receive signal from the host device 240 and a transmit signal to the host device 240 in accordance with the physical layer communication protocol. For example, the signal processing circuit 210 may perform operations such as amplification or attenuation, analog-to-digital conversion, frequency mixing, basic encoding or decoding, and physical layer packet decapsulation on the receive and transmit signals.

[0075] The signal processing circuit 220 may be a communication protocol layer signal processing circuit, configured to perform corresponding signal processing on the transmitted and received signals in accordance with a communication protocol higher than the physical layer. For example, the signal processing circuit 220 may perform corresponding signal processing on the transmitted and received signals in accordance with the Unified Protocol (UniPro) developed by the Mobile Industry Processor Interface (MIPI) Alliance. The signal processing circuit 220 may be further divided into multiple layers of signal processing circuits, such as a physical adapter (PA) layer signal processing circuit connected to the physical layer signal processing circuit, and other signal processing circuits higher than the PA layer. The signal processing circuit 230 may be an application layer signal processing circuit, configured to perform signal processing in accordance with a communication protocol of an application layer higher than the physical layer and the communication protocol layer.

[0076] In an embodiment of the present invention, the signal processing circuit 210 may be a serializer-deserializer (SerDes) or a physical layer signal processing circuit of SerDes to achieve high-speed data and signal transmission between the aforementioned predetermined device and the host device.

[0077] Figure 3 An exemplary block diagram of a signal processing circuit according to an embodiment of the present invention is shown. In this embodiment, the signal processing circuit 300 may be a physical layer signal processing circuit configured within an interface circuit, such as a physical layer signal processing circuit within a host interface of a memory controller. Alternatively, the signal processing circuit 300 may be a serializer-deserializer (SerDes) or a physical layer signal processing circuit within a serializer-deserializer within a memory controller, configured to process received signals and transmit signals.

[0078] The signal processing circuit 300 may include multiple signal processing devices and a calibration device 330. The calibration device 330 is coupled to the multiple signal processing devices and is used to sequentially calibrate a characteristic value of each signal processing device during a calibration process. The signal processing devices within the signal processing circuit 300 may include a receiving circuit 301, an equalization circuit 302, a received data buffer circuit 303, a decoder circuit 304, a transmitted data buffer circuit 305, a serializer 306, an amplitude control circuit 307, a transmitting circuit 308, a low dropout regulator circuit 309, a bandgap filter circuit 310, and a frequency synthesizer circuit 311.

[0079] It is worth noting that Figure 3 FIG1 is a simplified schematic diagram of a signal processing circuit, in which only the components related to the present invention are shown. A person skilled in the art will understand that a physical layer signal processing circuit may also include many components not shown in FIG1. Figure 3 components to implement the corresponding physical layer signal processing functions.

[0080] In the receive signal processing path, the receive circuit 301 is configured to receive a signal from either the external signal receive path 312 or the internal signal receive path 313. The equalization circuit 302 is configured to perform equalization processing on the receive signal received by the receive circuit 301. In the embodiment of the present invention, since the equalization circuit 302 is coupled to the external signal receive path 312 and the internal signal receive path 313 through the receive circuit 301, the equalization circuit 302 can perform equalization processing on the receive signal received by the receive circuit 301 from the external signal receive path 312, and can also perform equalization processing on the receive signal received by the receive circuit 301 from the internal signal receive path 313.

[0081] The equalization circuit 302 may include a continuous time linear equalizer (CTLE), a clock data recovery (CDR) circuit, and a deserializer (not shown). Figure 3). The continuous-time linear equalizer is used to perform equalization processing on the received signal, wherein the received signal is a serial signal. The clock data recovery circuit is used to regenerate a clock signal synchronized with the transmitting end based on the received signal, and to attempt to accurately recover the data signal content contained in the received signal based on the clock signal. The deserializer is used to convert the serial data signal into a parallel data signal, and to output the data signal, wherein the data signal is transmitted in parallel through multiple buses. The received data buffer circuit 303 is used to cache the received data output by the equalization circuit 302. The decoder circuit 304 is used to perform decoding operations on the received data. The decoded received data will be further provided to a higher-level signal processing circuit, such as the aforementioned physical adaptation layer signal processing circuit.

[0082] In the transmit signal processing path, the transmit data buffer circuit 305 is used to buffer transmit data provided by the upper-layer signal processing circuit. This data can be a parallel data signal. The serializer 306 is used to convert the parallel data signal into a serial data signal. The swing control circuit 307 is used to control the swing of the transmit signal, for example, adjusting the voltage of the transmit signal to an appropriate level. The transmit circuit 308 is used to transmit the transmit signal, for example, to a host device.

[0083] In addition to the signal processing devices on the transmit signal processing path and the receive signal processing path described above, the signal processing circuit 300 also includes some shared circuits for providing the frequency, current, voltage, and / or power required by other signal processing devices. The low-dropout voltage regulator 309 is used to provide a stable voltage signal. For example, it provides a stable voltage signal to the bandgap filter circuit 310. The bandgap filter circuit 310 is used to filter voltage noise to provide a clean voltage signal to other signal processing devices (as shown by the thin dashed line in the figure). The frequency synthesis circuit 311 is used to generate the clock signal required within the signal processing circuit 300 and provide the clock signal to other signal processing devices (as shown by the thick dashed line in the figure). In one embodiment of the present invention, the frequency synthesis circuit 311 can be implemented by a phase-locked loop (PLL) to generate an oscillating signal as the clock signal required within the signal processing circuit 300.

[0084] According to one embodiment of the present invention, the calibration device 330 is configured to sequentially calibrate a characteristic value of a plurality of signal processing devices (e.g., at least a first signal processing device and a second signal processing device) in a calibration process. Furthermore, according to one embodiment of the present invention, the calibration process may be triggered in response to a power mode change request issued by a host device, such as the host device 130 coupled to the data storage device 100 or the host device 240 coupled to the interface circuit 200.

[0085] Figure 4 An example block diagram of a calibration device according to an embodiment of the present invention is shown. Calibration device 400 may include a trigger detection circuit 410, a control circuit 420, and a probe circuit 430. Trigger detection circuit 410 is used to detect whether a calibration process is triggered by an upper-layer signal processing circuit. According to an embodiment of the present invention, trigger detection circuit 410 can detect whether a calibration process is triggered by an upper-layer signal processing circuit by detecting whether a physical adaptation layer signal processing circuit (e.g., the physical adaptation layer signal processing circuit within signal processing circuit 220) issues a trigger signal.

[0086] According to one embodiment of the present invention, upon receiving a power mode change request (e.g., power mode change request PACP_PWR_REQ) issued by a host device, the physical adaptation layer signal processing circuit may further detect whether the activation of adapt equalization is indicated in the power mode change request. The host device may include information related to the activation of adapt equalization and its parameters (e.g., adaptation length, adaptation range, adaptation period, etc.) in the power mode change request. When the power mode change request indicates the activation of adapt equalization, the physical adaptation layer signal processing circuit may transmit a trigger message to the calibration device 400. In response to receiving the trigger message, the trigger detection circuit 410 may notify the control circuit 420 to start executing the calibration procedure. Therefore, in an embodiment of the present invention, when the activation of adapt equalization is indicated in the power mode change request, the calibration procedure may be triggered.

[0087] It should be noted that in the embodiments of the present invention, the calibration procedure may be an advanced or improved adaptive equalization. In the calibration procedure, the calibration device (e.g., calibration device 330 or 400) may calibrate a characteristic value of a first signal processing device configured on a receiving signal processing path for processing a receiving signal, and may also calibrate a characteristic value of a second signal processing device configured on a transmitting signal processing path for processing a transmitting signal. In the embodiments of the present invention, the first signal processing device that may be calibrated in the calibration procedure may be Figure 3 The equalization circuit 302 shown in FIG. 1 and the second signal processing device that can be calibrated in the calibration process can be Figure 3The swing control circuit 307 is shown.

[0088] Control circuit 420 is coupled to trigger detection circuit 410 and probe circuit 430 and is configured to initiate a calibration process in one or more adaptation cycles in response to a notification from trigger detection circuit 410. Probe circuit 430 is coupled to control circuit 420 and at least a first signal processing device and a second signal processing device within the signal processing circuit, and sequentially probes the coupled signal processing devices to generate corresponding probe results. The obtained probe results are sequentially provided to control circuit 420, allowing control circuit 420 to sequentially adjust a characteristic value of each signal processing device during the calibration process.

[0089] According to a first embodiment of the present invention, the probing circuit 430 may include an analog-to-digital converter (ADC) circuit for sequentially probing parameters of the signal processing circuit, such as the current voltage level of a voltage source, the current voltage level of a ground voltage, and the parameters of the signal processing device to be calibrated. The order in which these signal processing device parameters are probed can be flexibly designed based on the operating mode configured by the interface circuit during the calibration process (the operating modes will be described in detail in the following paragraphs). Therefore, in the first embodiment of the present invention, the ADC circuit within the probing circuit 430 can be shared by the signal processing devices to be calibrated.

[0090] According to a second embodiment of the present invention, the detection circuit 430 may include multiple ADC circuits, and each signal processing device to be calibrated may be assigned a dedicated ADC circuit for detecting corresponding parameters. Furthermore, at least one ADC circuit may be configured to detect the current voltage level of a voltage source to be provided as a reference voltage and the current voltage level of a ground voltage.

[0091] As described above, in the embodiment of the present invention, the first signal processing device to be calibrated in the calibration process may be Figure 3 The equalization circuit 302 in the calibration process may be Figure 3 The swing control circuit 307 in.

[0092] Regarding the equalization circuit 302, during the calibration process, the detection circuit 430 can detect the voltage level of the data signal output by the equalization circuit 302, convert the detected voltage level value, which is an analog value, into a digital value (also known as a digital detection value), and provide these digital detection values ​​as detection results to the control circuit 420.

[0093] Regarding the swing control circuit 307, during the calibration process, the detection circuit 430 can detect the voltage level of the transmission signal output by the swing control circuit 307, convert the detected voltage level value, which is an analog value, into a digital value (also called a digital detection value), and provide these digital detection values ​​as detection results to the control circuit 420.

[0094] According to one embodiment of the present invention, the swing control circuit 307 is coupled to the equalization circuit 302 via the transmission circuit 308, the internal signal receiving path 313, and the receiving circuit 301. During a calibration process, the transmission signal output by the swing control circuit 307 is provided to the equalization circuit 302 via the internal signal receiving path 313 for performing an inner loop calibration.

[0095] Figure 5 A flow chart illustrating an example of a calibration process controlled by a calibration device according to an embodiment of the present invention is shown. In step S501, the trigger detection circuit 410 may operate in a standby state to detect or confirm whether the physical adaptation layer signal processing circuit has issued a trigger signal. When the trigger detection circuit 410 confirms that the trigger signal has been detected or found in step S502, the trigger detection circuit 410 may notify the control circuit 420 to begin executing the calibration process.

[0096] Before starting the calibration process, the control circuit 420 may first determine which operating mode the interface circuit (or a data processing device or memory controller including the interface circuit) is configured in. In step S503, the control circuit 420 may determine whether the operating mode currently configured for the interface circuit is the DUT (Device Under Test) auto mode. If the operating mode configured for the interface circuit is the DUT auto mode, the control circuit 420 may first perform an inner loop calibration in step S504 to calibrate the transmit swing voltage of the transmit signal output by the swing control circuit 307 and the equalization parameters of the equalization circuit 302 (i.e., receive equalization calibration) via the internal signal receiving path 313. Then, in step S505, the control circuit 420 may perform an outer loop calibration to calibrate the equalization parameters of the equalization circuit 302 via the external signal receiving path 312.

[0097] If the operating mode configured for the interface circuit is not the DUT automatic mode, the control circuit 420 may further determine whether the operating mode currently configured for the interface circuit is a host-device interaction mode in step S506. If the operating mode currently configured for the interface circuit is the host-device interaction mode, the control circuit 420 may first perform internal loop calibration in step S504 and then perform external loop calibration in step S505.

[0098] If the operating mode configured for the interface circuit is not the host-device interaction mode, the control circuit 420 may further determine whether the operating mode currently configured for the interface circuit is a device initialization adjustment mode in step S507. If the operating mode currently configured for the interface circuit is the device initialization adjustment mode, the control circuit 420 may first perform internal loop calibration in step S504 and then perform external loop calibration in step S505.

[0099] If the operating mode currently configured for the interface circuit is not the device initial adjustment mode, the control circuit 420 may further determine whether the operating mode currently configured for the interface circuit is a host initial adjustment mode in step S508. If the operating mode currently configured for the interface circuit is the host initial adjustment mode, the control circuit 420 may first perform external loop calibration in step S509 and then perform internal loop calibration in step S510. If the operating mode currently configured for the interface circuit is not the host initial adjustment mode, the control circuit 420 may only perform external loop calibration in step S505.

[0100] According to one embodiment of the invention, the calibration device (e.g., calibration device 330, 400) can operate according to the aforementioned operating mode of the interface circuit during a calibration procedure, and the interface circuit can negotiate the operating mode with the host device (e.g., host device 130, 240) during a link up procedure.

[0101] Figure 6 An exemplary flow chart is shown of a method for calibrating a plurality of signal processing devices within an interface circuit of a memory controller according to an embodiment of the present invention. The calibration method proposed by the present invention comprises the following steps:

[0102] Step S602: Negotiate with the host device in a link process an operation mode of the interface circuit in a calibration process.

[0103] Step S604: Calibrate a characteristic value of the first signal processing device and a characteristic value of the second signal processing device according to the operation mode in the calibration procedure.

[0104] In the embodiment of the present invention, the detailed process of the calibration performed according to the operation mode in step S604 can be referred to Figure 5 The example process shown.

[0105] Figure 7An example flow chart of a link procedure performed by a node A device (e.g., a host device) and a node B device (e.g., a data storage device or an interface circuit) according to an embodiment of the present invention is shown. In the link procedure, the node A device and the node B device attempt to link to each other, for example, by sending trigger event messages TRG_UPR 0, TRG_UPR 1, TRG_UPR 2, etc. in link startup phases 0 to 4. After linking to each other, the node A device and the node B device exchange capability information. According to an embodiment of the present invention, capability information can be exchanged between the node A device and the node B device via one or more capability indication commands. For example, Figure 7 The capability indication commands PACP_CAP_ind, PACP_CAP_EXT1_ind, and PACP_CAP_EXT2_ind are shown in FIG. According to one embodiment of the present invention, information regarding the operating modes supported by a node device may be carried in the capability indication command PACP_CAP_EXT2_ind. After exchanging information regarding the operating modes supported by the node device, the host device can make a final decision based on the exchanged capability information to determine which operating mode to configure for the interface circuit.

[0106] Figure 8 An example of the data structure of the capability indication command PACP_CAP_EXT2_ind according to an embodiment of the present invention is shown. The capability indication command may include multiple fields to carry the capability information of the corresponding device, for example, Figure 8 The capability parameters (and corresponding setting values) related to physical adaptation shown in : ESC_PA, EscParam_PA, PACP_BEGIN, PACP_FunctionID, etc., and the capability parameters related to the high speed (HS) mode: MaxHS, RxHsG4PrepareLength, RxHsG4SyncLength, RxHsAdaptResfresh, RxHsAdaptInitial, etc. According to one embodiment of the present invention, the information of the operation mode supported by the host device and / or the interface circuit, and / or the operation mode determined and configured by the host device can be carried in the reserved field of the capability indication command PACP_CAP_EXT2_ind, for example, Figure 8Parameter AdMod is shown. According to one embodiment of the present invention, a list of valid attribute values ​​for parameter AdMod may include 00, 01, 10, and 11, where the value 00 may represent the DUT auto mode, the value 01 may represent the host-device interaction mode, the value 10 may represent the host initial adjustment mode, and the value 11 may represent the device initial adjustment mode. The communication protocol layer signal processing circuit (e.g., signal processing circuit 220) may obtain information related to the configured operating mode from the received capability indication command and may provide the information related to the configured operating mode (or the corresponding operation to be performed in the calibration procedure) to the physical layer signal processing circuit (e.g., signal processing circuit 210).

[0107] According to one embodiment of the present invention, in the automatic mode of the device under test, the device under test performs an inner loop calibration in the first half of the adaptation cycle to calibrate the transmit swing voltage (e.g., the voltage level of the transmit signal) and the receive equalization (e.g., the parameters used by the equalization circuit 302) via the internal signal receiving path 313 (i.e., the inner loop). Furthermore, in the second half of the adaptation cycle, an outer loop calibration is performed to calibrate the receive equalization via the external signal receiving path 312 (i.e., the outer loop).

[0108] It should be noted that in embodiments of the present invention, the device under test can be a host device (hereinafter referred to as the host) or an interface circuit configured within a memory controller or data storage device (hereinafter referred to as the device). Furthermore, it should be noted that because the data storage system comprising the host and the device is a symmetrical system, the design of the interface circuit within the host and the interface circuit within the device can be substantially identical. Therefore, depending on the operating modes in which the host and the device are configured, as will be further explained in the following paragraphs, the host and the device can independently or jointly calibrate the transmit swing voltage and receive equalization during the adaptation cycle.

[0109] Figure 9 Shown are waveform examples of a transmission signal transmitted by the device under test in the automatic mode of the device under test (drawn in the upper row) and waveform examples of a reception signal received by the device under test (drawn in the lower row) according to an embodiment of the present invention. Figure 9As shown, a pseudorandom binary sequence (PRBS) PRBS9 (or a pseudorandom binary sequence PRBS9 plus one or more additional bits b0) is used in the first half of the adaptation period ADAPT (e.g., the first half of the time interval TADAPT corresponding to the adaptation period ADAPT), allowing the device under test to adjust or calibrate the transmit swing voltage (e.g., the Adjust_TX_Swing operation shown in the figure). The device under test can further use the transmit signal output by the swing control circuit 307 to adjust or calibrate the receive equalization through an internal loop (e.g., the Adjust_RX_Equalization operation corresponding to the internal loop shown in the figure). In the second half of the adaptation period ADAPT (e.g., the second half of the time interval TADAPT corresponding to the adaptation period ADAPT), the device under test adjusts or calibrates the receive equalization through an external loop (e.g., the Adjust_RX_Equalization operation corresponding to the external loop shown in the figure).

[0110] According to one embodiment of the present invention, in a host-device interaction mode, the host and the device each perform an inner loop calibration in the first half of an adaptation period (ADAPT) to adjust or calibrate the transmit swing voltage and receive equalization via the inner loop. Furthermore, the host and the device each perform an outer loop calibration in the second half of the adaptation period (ADAPT) to adjust or calibrate the receive equalization via the outer loop.

[0111] Figure 10 Shown are waveform examples of a transmit signal transmitted by a device (drawn in the first row), waveform examples of a receive signal received by the device (drawn in the second row), waveform examples of a transmit signal transmitted by the host (drawn in the third row), and waveform examples of a receive signal received by the host (drawn in the fourth row) in a host-device interaction mode according to an embodiment of the present invention. Figure 10As shown, a pseudo-random binary sequence PRBS9 (or a pseudo-random binary sequence PRBS9 plus one or more additional bits b0) is used in the first half of the adaptation period ADAPT (e.g., the first half of the time interval TADAPT corresponding to the adaptation period ADAPT). This allows the device and host to adjust or calibrate the transmit swing voltage (e.g., the Adjust_TX_Swing operation shown in the figure) and adjust or calibrate receive equalization (e.g., the Adjust_RX_Equalization operation corresponding to the inner loop shown in the figure) through an internal loop. In the second half of the adaptation period ADAPT (e.g., the second half of the time interval TADAPT corresponding to the adaptation period ADAPT), the device and host can adjust or calibrate receive equalization (e.g., the Adjust_RX_Equalization operation shown in the figure corresponding to the outer loop) through an external loop. The transmit signal output by the device / host can be provided to the device / host for internal loop calibration as well as to the host / device for external loop calibration.

[0112] According to one embodiment of the present invention, the host initial adjustment mode requires two adaptation cycles. In the first adaptation cycle, the host performs an internal loop calibration to adjust or calibrate the transmit voltage swing and receive equalization through the internal loop, while the device performs an external loop calibration to adjust or calibrate the receive equalization through the external loop. In the second adaptation cycle, the device performs an internal loop calibration to adjust or calibrate the transmit voltage swing and receive equalization through the internal loop, while the host performs an external loop calibration to adjust or calibrate the receive equalization through the external loop.

[0113] Figure 11 Shown are waveform examples of the transmission signal transmitted by the device in the host initial adjustment mode as described in one embodiment of the present invention (drawn in the first row), waveform examples of the reception signal received by the device (drawn in the second row), waveform examples of the transmission signal transmitted by the host (drawn in the third row), and waveform examples of the reception signal received by the host (drawn in the fourth row).

[0114] like Figure 11As shown, the device performs outer loop calibration in a first adaptation cycle (e.g., adaptation cycle ADAPT_1 shown in the figure) to adjust or correct receive equalization through the outer loop (e.g., operation Adjust_RX_Equalization corresponding to the outer loop shown in the figure), and performs inner loop calibration in a second adaptation cycle (e.g., adaptation cycle ADAPT_2 shown in the figure) to adjust or correct the transmit swing voltage (e.g., operation Adjust_TX_Swing shown in the figure) and adjust or correct receive equalization (e.g., operation Adjust_RX_Equalization corresponding to the inner loop shown in the figure) through the inner loop.

[0115] The host performs inner loop calibration in a first adaptation cycle (e.g., adaptation cycle ADAPT_1 shown in the figure) to adjust or calibrate the transmit swing voltage (e.g., operation Adjust_TX_Swing shown in the figure) and receive equalization (e.g., operation Adjust_RX_Equalization corresponding to the inner loop shown in the figure) through the inner loop, and performs outer loop calibration in a second adaptation cycle (e.g., adaptation cycle ADAPT_2 shown in the figure) to adjust or calibrate receive equalization (e.g., operation Adjust_RX_Equalization corresponding to the outer loop shown in the figure) through the outer loop. Therefore, in the host initial calibration mode, the host may first perform inner loop calibration and then perform outer loop calibration, while the calibration order arranged by the device may be the opposite of that of the host.

[0116] According to one embodiment of the present invention, the device's initial adjustment mode requires two adaptation cycles. During the first adaptation cycle, the device performs internal loop calibration to adjust or calibrate the transmit voltage swing and receive equalization via the internal loop, while the host performs external loop calibration to adjust or calibrate receive equalization via the external loop. During the second adaptation cycle, the host performs internal loop calibration to adjust or calibrate the transmit voltage swing and receive equalization via the internal loop, while the device performs external loop calibration to adjust or calibrate receive equalization via the external loop.

[0117] Figure 12 Shown are waveform examples of the transmission signal transmitted by the device in the initial adjustment mode of the device according to an embodiment of the present invention (drawn in the first row), waveform examples of the reception signal received by the device (drawn in the second row), waveform examples of the transmission signal transmitted by the host (drawn in the third row), and waveform examples of the reception signal received by the host (drawn in the fourth row).

[0118] like Figure 12As shown, the device performs inner loop calibration in a first adaptation cycle (e.g., adaptation cycle ADAPT_1 shown in the figure) to adjust or correct the transmit swing voltage (e.g., operation Adjust_TX_Swing shown in the figure) and adjust or correct receive equalization (e.g., operation Adjust_RX_Equalization corresponding to the inner loop shown in the figure) through the inner loop, and performs outer loop calibration in a second adaptation cycle (e.g., adaptation cycle ADAPT_2 shown in the figure) to adjust or correct receive equalization (e.g., operation Adjust_RX_Equalization corresponding to the outer loop shown in the figure) through the outer loop.

[0119] The host performs outer loop calibration in a first adaptation cycle (e.g., adaptation cycle ADAPT_1 shown in the figure) to adjust or calibrate receive equalization via the outer loop (e.g., the operation Adjust_RX_Equalization corresponding to the outer loop shown in the figure). Furthermore, in a second adaptation cycle (e.g., adaptation cycle ADAPT_2 shown in the figure), the host performs inner loop calibration to adjust or calibrate the transmit swing voltage (e.g., the operation Adjust_TX_Swing shown in the figure) and adjust or calibrate receive equalization (e.g., the operation Adjust_RX_Equalization corresponding to the inner loop shown in the figure) via the inner loop. Therefore, in the device initial calibration mode, the device may first perform inner loop calibration and then perform outer loop calibration, and the calibration order arranged by the host may be the opposite of that of the device.

[0120] It should be noted that in embodiments of the present invention, two power mode change requests are required for both host initial adjustment mode and device initial adjustment mode. For example, when operating in host initial adjustment mode or device initial adjustment mode, the host may issue two power mode change requests to obtain two adaptation cycles.

[0121] Furthermore, in an embodiment of the present invention, during a calibration process, such as the several operating modes described above, equalization circuit 302 may sequentially process signals received from external signal receiving path 312 and internal signal receiving path 313. In an embodiment of the present invention, calibration device 330 may select, via one or more switching devices (not shown), whether to provide the signal received from external signal receiving path 312 or the signal received from internal signal receiving path 313 to equalization circuit 302.

[0122] In an embodiment of the present invention, when in the calibration process, for example Figures 9 to 12During the adaptation cycle shown, when adjusting or calibrating the transmit swing voltage, the control circuit 420 may adjust the voltage level of the transmit signal output by the swing control circuit 307 based on the difference between the transmit signal voltage level detection result provided by the detection circuit 430 and a target transmit voltage level. Alternatively, the control circuit 420 may adjust the voltage level of the transmit signal output by the swing control circuit 307 based on the attribute value of the data signal output by the equalization circuit 302 detected by the detection circuit 430. For example, when the data signal output by the equalization circuit 302 is determined to be unrecognizable, or when the equalization circuit 302 is unable to successfully receive the transmit signal provided by the swing control circuit 307 via the internal signal receiving path 313, the control circuit 420 may determine to increase the voltage level of the transmit signal output by the swing control circuit 307 because the original setting appears insufficient for the equalization circuit 302 to successfully receive and / or reply the data.

[0123] In an embodiment of the present invention, when in the calibration process, for example Figures 9 to 12 During the adaptation period shown, when adjusting or correcting receive equalization, control circuit 420 may adjust equalization parameters of equalization circuit 302 based on the detection results provided by detection circuit 430. For example, control circuit 420 may generate an eye diagram corresponding to the voltage level of the data signal output by equalization circuit 302 and detected by detection circuit 430, and adjust equalization parameters based on the eye diagram. For example, until a clear eye diagram is present, control circuit 420 may continue to adaptively adjust the gain of the continuous time linear equalizer (CTLE) based on the eye diagram content established by the detection results provided by detection circuit 430. It should be noted that control circuit 420 may also similarly adjust the voltage level of the transmit signal output by swing control circuit 307 based on the eye diagram content.

[0124] By applying the calibration method proposed in the present invention to calibrate multiple signal processing devices within an interface circuit during a calibration procedure, the characteristic values ​​of the signal processing devices within the serializer-deserializer can be accurately calibrated. Compared to existing adaptive equalization methods, the adaptive equalization operation proposed in the present invention is a relatively advanced or improved adaptive equalization, thereby effectively avoiding frequency or voltage jitter caused by characteristic value deviation or offset in the signal processing devices, thereby preventing fatal errors in high-speed communication systems.

[0125] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made according to the scope of the patent application of the present invention should fall within the scope of the present invention.

Claims

1. An interface circuit comprising: a first signal processing device, disposed on a received signal processing path for processing a received signal; a second signal processing device, disposed on a transmission signal processing path for processing a transmission signal; as well as a calibration device coupled to the first signal processing device and the second signal processing device, for calibrating a characteristic value of the first signal processing device and a characteristic value of the second signal processing device in a calibration procedure, wherein the first signal processing device is coupled to an external signal receiving path and an internal signal receiving path, and is configured to sequentially process the received signal from the external signal receiving path and the received signal from the internal signal receiving path in the calibration procedure; The second signal processing device is coupled to the first signal processing device through the internal signal receiving path and is used to provide the transmission signal to the first signal processing device during the calibration process, and The first signal processing device is an equalization circuit for performing equalization processing on the received signal, and the second signal processing device is an amplitude control circuit for controlling an amplitude of the transmitted signal.

2. The interface circuit according to claim 1, wherein: The interface circuit is included in a data storage device, and the calibration procedure is triggered in response to a power mode change request issued by a host device coupled to the data storage device.

3. The interface circuit according to claim 2, wherein: The correction process is triggered when activation of an adaptive equalization is indicated in the power mode change request.

4. The interface circuit according to claim 2, wherein: The calibration device further operates according to an operation mode of the interface circuit in the calibration procedure, and the interface circuit negotiates the operation mode with the host device in a link procedure.

5. The interface circuit according to claim 4, wherein: During the link procedure, the operating mode is negotiated via at least one capability indication command.

6. The interface circuit according to claim 1, wherein: Also includes: A serializer-deserializer (SDS) physical layer signal processing circuit, wherein the first signal processing device, the second signal processing device, and the calibration device are included in the SDS physical layer signal processing circuit.

7. A memory controller coupled to a memory device for controlling access to the memory device, comprising: An interface circuit coupled to a host device for communicating with the host device, wherein the interface circuit includes: a first signal processing device, disposed on a received signal processing path for processing a received signal; a second signal processing device, disposed on a transmission signal processing path for processing a transmission signal; and a calibration device coupled to the first signal processing device and the second signal processing device, for calibrating a characteristic value of the first signal processing device and a characteristic value of the second signal processing device in a calibration procedure, wherein the first signal processing device is coupled to an external signal receiving path and an internal signal receiving path, and is configured to sequentially process the received signal from the external signal receiving path and the received signal from the internal signal receiving path in the calibration procedure; The second signal processing device is coupled to the first signal processing device through the internal signal receiving path and is used to provide the transmission signal to the first signal processing device during the calibration process, and The first signal processing device is an equalization circuit for performing equalization processing on the received signal, and the second signal processing device is an amplitude control circuit for controlling an amplitude of the transmitted signal.

8. The memory controller according to claim 7, wherein: The calibration process is triggered in response to a power mode change request issued by the host device.

9. The memory controller according to claim 8, wherein: The calibration procedure is triggered when activation of an adaptive equalization is indicated in the power mode change request.

10. The memory controller according to claim 7, wherein: The calibration device operates according to an operation mode of the interface circuit in the calibration procedure, and the interface circuit negotiates the operation mode with the host device in a link procedure.

11. The memory controller according to claim 10, wherein: During the link procedure, the operating mode is negotiated via at least one capability indication command.

12. The memory controller according to claim 7, wherein: Also includes: A serializer-deserializer (SDS) physical layer signal processing circuit, wherein the first signal processing device, the second signal processing device, and the calibration device are included in the SDS physical layer signal processing circuit.

13. A method for calibrating a plurality of signal processing devices in an interface circuit of a memory controller, wherein the memory controller is coupled to a memory device for controlling access to the memory device, and the memory controller is included in a data storage device, and the data storage device is coupled to a host device, the method comprising: negotiating with the host device in a linking process an operation mode of the interface circuit in a calibration process; as well as In the calibration procedure, a characteristic value of a first signal processing device and a characteristic value of a second signal processing device are calibrated, wherein the first signal processing device is configured on a receive signal processing path for processing a receive signal, and the second signal processing device is configured on a transmit signal processing path for processing a transmit signal. The first signal processing device is an equalization circuit for performing equalization processing on the received signal, and the second signal processing device is an amplitude control circuit for controlling an amplitude of the transmitted signal. The first signal processing device is coupled to an external signal receiving path and an internal signal receiving path, and is used to sequentially process the received signal received from the external signal receiving path and the received signal received from the internal signal receiving path in the calibration process. The second signal processing device is coupled to the first signal processing device through the internal signal receiving path, and is used to provide the transmitted signal to the first signal processing device in the calibration process. The interface circuit operates according to the operation mode in the calibration procedure.

14. The method according to claim 13, wherein The calibration process is triggered in response to a power mode change request issued by the host device.

15. The method according to claim 14, wherein The correction process is triggered when activation of an adaptive equalization is indicated in the power mode change request.

16. The method according to claim 13, wherein During the link procedure, the operating mode is negotiated via at least one capability indication command.

17. The method according to claim 13, wherein The step of calibrating the characteristic value of the first signal processing device and the characteristic value of the second signal processing device in the calibration procedure further includes: calibrating the characteristic value of the first signal processing device using an external signal receiving path and an internal signal receiving path, wherein the first signal processing device is coupled to the external signal receiving path and the internal signal receiving path, and is used to sequentially process the receiving signal received from the external signal receiving path and the receiving signal received from the internal signal receiving path in the calibration procedure; and The second signal processing device is coupled to the first signal processing device through the internal signal receiving path, and is used to provide the transmission signal to the first signal processing device during the calibration process.

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