Nor flash memory array and operation method thereof

Abstract

The present invention provides a Nor flash memory array. The Nor flash memory array includes a plurality of memory cells arranged in rows and columns, the plurality of memory cells are located within a well region of a substrate, and each memory cell includes a plurality of memory tubes connected in series; the top of the substrate of the well region has a first doping region, and in the same memory cell, the gate structures of the plurality of memory tubes are arranged above the substrate of the first doping region along the column direction, and the region in the first doping region corresponding to the position of the gate structure of a memory tube is the channel region of a memory tube, and there is no PN junction between the channel regions of two adjacent memory tubes, and the two adjacent memory tubes are connected through the first doping region between the gate structures of the two adjacent memory tubes, which is conducive to increasing the channel length of the memory tube, improving the controllability of the memory tube, and at the same time making the arrangement between the memory tubes more compact, thereby improving the performance and economy of the Nor flash memory array. The present invention also provides an operation method of the above-mentioned Nor flash memory array.

Description

Technical Field

[0001] The present invention relates to the field of storage technology, and in particular to a Nor flash memory array and an operation method thereof. Background Art

[0002] Flash memory is a non-volatile (or non-volatile) semiconductor memory chip that can maintain stored data information even when the power is off. Moreover, flash memory has the advantages of small size, low power consumption, and not susceptible to physical damage, so it has been widely used. Traditional NOR flash memory arrays have 1T (1-Transistor, single transistor) structure, 2T (2-Transistor, dual transistor) structure or split gate (SplitGate) structure. Although the 1T structure has a small unit storage area, the programming and reading power consumption is relatively large; the 2T structure adds a selection tube, the current is improved, but the unit storage area is larger.

[0003] In addition, as the process node shrinks, the storage tubes in the existing Nor flash memory array are prone to short channel effects, the leakage current of the storage tubes is large, and the control of the storage tubes is difficult. Summary of the invention

[0004] The present invention provides a Nor flash memory array, in which there is no PN junction between the channel regions of two adjacent storage tubes, which is beneficial to increase the channel length of the storage tubes, improve the controllability of the storage tubes, and make the arrangement between the storage tubes more compact, thereby improving the performance and economy of the Nor flash memory array. The present invention also provides an operation method of the Nor flash memory array.

[0005] In order to achieve the above-mentioned object, the present invention provides a Nor flash memory array. The Nor flash memory array includes a plurality of memory cells arranged in rows and columns, the plurality of memory cells are located within a well region of a substrate, and each of the memory cells includes a plurality of memory tubes connected in series; the top of the substrate of the well region has a first doping region, and in the same memory cell, the gate structures of the plurality of memory tubes are arranged above the substrate of the first doping region along the column direction, and the region in the first doping region corresponding to the position of the gate structure of a memory tube is a channel region of the memory tube, and there is no PN junction between the channel regions of two adjacent memory tubes, and the two adjacent memory tubes are connected through the first doping region between the gate structures of the two adjacent memory tubes.

[0006] Optionally, each of the storage cells further includes a bit line selection tube and a source line selection tube; in the same storage cell, the bit line selection tube and the source line selection tube are located at both ends of the multiple storage tubes connected in series, the end of the bit line selection tube close to the storage tube is connected to the adjacent storage tube, the end of the source line selection tube close to the storage tube is connected to the adjacent storage tube, and the end of the source line selection tube away from the storage tube is connected to the common source line; the gate structures of the bit line selection tubes of the storage cells in the same row are electrically connected to the same bit line selection line; the gate structures of the source line selection tubes of the storage cells in the same row are electrically connected to the same source line selection line.

[0007] Optionally, the Nor flash memory array also includes multiple bit lines and multiple word lines; one of the bit lines is electrically connected to an end of the bit line selection tube away from the storage tube in the storage cells in the same column; and one of the word lines is electrically connected to the gate structure of the storage tube in the same row of the storage cells in the same row.

[0008] Optionally, the top of the substrate of the well region has a second doping region and a third doping region located on both sides of the first doping region, and the second doping region and the third doping region are both connected to the first doping region; the gate structure of the bit line selection tube is located above the substrate of the second doping region, and the second doping region is the channel region of the bit line selection tube; the gate structure of the source line selection tube is located above the substrate of the third doping region, and the third doping region is the channel region of the source line selection tube.

[0009] Optionally, the first doped region extends to below the side surface of the gate structure of the bit line selection tube close to the storage tube, and the first doped region extends to below the side surface of the gate structure of the source line selection tube close to the storage tube; the bit line selection tube is connected to the adjacent storage tube through the first doped region; the source line selection tube is connected to the adjacent storage tube through the first doped region.

[0010] Optionally, the channel of the bit line selection tube and the channel of the source line selection tube are both enhancement channels.

[0011] Optionally, the channel of the storage tube is a self-aligned intrinsic depletion channel.

[0012] The present invention also provides an operation method of a Nor flash memory array, which is used to perform a read operation on the above-mentioned Nor flash memory array. The operation method of the Nor flash memory array includes: calling a storage cell to be read a selected storage cell, and calling a storage tube to be read in the selected storage cell a selected storage tube; applying a first turn-on voltage to a bit line selection line connected to the selected storage cell; applying a first read voltage to a word line connected to the selected storage tube, and applying a second turn-on voltage to other word lines connected to the selected storage cell; applying a third turn-on voltage to a source line selection line connected to the selected storage cell; applying a zero volt voltage to a common source line connected to the source line selection tube of the selected storage cell; applying a zero volt voltage to the well region; applying a second read voltage to the bit line connected to the selected storage cell; applying a zero volt voltage to both the bit line selection line and the source line selection line connected to the unselected storage cells in different rows from the selected storage cell; and applying a zero volt voltage or suspending the word lines connected to the unselected storage cells in different rows from the selected storage cell.

[0013] The present invention also provides an operation method of a Nor flash memory array, which is used to perform a programming operation on the above-mentioned Nor flash memory array. The operation method of the Nor flash memory array includes: calling a storage cell to be programmed a selected storage cell, and calling a storage tube to be programmed in the selected storage cell a selected storage tube; applying an inhibition voltage to a bit line selection line connected to the selected storage cell; applying a first positive voltage to a word line connected to the selected storage tube, applying a first negative voltage to a word line connected to a storage tube adjacent to the selected storage tube in the selected storage cell, and applying an opening voltage to a word line connected to the remaining storage tubes in the selected storage cell; applying a second negative voltage to a source line selection line connected to the selected storage cell, the second negative voltage being less than the first negative voltage; applying a second negative voltage to a common source line connected to a source line selection tube of the selected storage cell; applying a second negative voltage to the well region; applying a second negative voltage to a bit line connected to the selected storage cell, and applying an inhibition voltage to bit lines connected to other storage cells in the same row as the selected storage cell; and applying a second negative voltage to the bit line selection line, source line selection line and word line connected to unselected storage cells in different rows from the selected storage cell.

[0014] The present invention also provides an operation method of a Nor flash memory array, which is used to perform an erasing operation on the above-mentioned Nor flash memory array. The operation method of the Nor flash memory array includes: calling a storage cell to be erased a selected storage cell; applying a positive voltage to a bit line selection line connected to the selected storage cell; applying a negative voltage to a word line connected to the selected storage cell; applying a positive voltage to a source line selection line connected to the selected storage cell; applying a positive voltage to a common source line connected to a source line selection tube of the selected storage cell; applying a positive voltage to the well region; applying a positive voltage to the bit line connected to the selected storage cell; and applying positive voltages to the bit line selection line, source line selection line and word line connected to unselected storage cells in different rows from the selected storage cell.

[0015] Compared with the conventional Nor flash memory array, the Nor flash memory array provided by the present invention has the following characteristics: in the same storage unit, it is not necessary to form a source-drain region with a conductivity type different from that of the channel region between the channel regions of two adjacent storage tubes; there is no PN junction between the channel regions of the two adjacent storage tubes; and the two adjacent storage tubes are connected via the first doped region between the gate structures of the two adjacent storage tubes, which is beneficial to increase the channel length of the storage tubes, enhance the controllability of the storage tubes, improve the performance of the Nor flash memory array, and make the arrangement between the storage tubes more compact, which can save the effective area of ​​the chip, thereby reducing the chip size and improving the economy of the Nor flash memory array.

[0016] Furthermore, each storage unit also includes a bit line selection tube and a source line selection tube located at both ends of the plurality of storage tubes connected in series. The addition of the bit line selection tube and the source line selection tube makes the reading operation of the Nor flash memory array simple and convenient. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to better describe and illustrate the embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more drawings. The additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the embodiments and / or examples currently described, and the best modes of these inventions currently understood.

[0018] Figure 1 A partial cross-sectional schematic diagram of a Nor flash memory array provided in accordance with an embodiment of the present invention.

[0019] Figure 2 An architectural diagram of a Nor flash memory array provided in accordance with an embodiment of the present invention.

[0020] Figure 3 A schematic diagram of voltage application during a read operation of a Nor flash memory array provided by an embodiment of the present invention.

[0021] Figure 4A schematic diagram of voltage application during programming operation of a Nor flash memory array provided by an embodiment of the present invention.

[0022] Figure 5 A schematic diagram of voltage application during an erase operation of a Nor flash memory array provided by an embodiment of the present invention.

[0023] Description of reference numerals:

[0024] 10-substrate; 100-well region; 101-first doping region; 102-second doping region; 103-third doping region; 104-fourth doping region; 105-fifth doping region; 20-storage tube; 201-ONO layer; 202-gate electrode; 30-bit line selection tube; 301-first oxide layer; 302-first gate; 40-source line selection tube; 401-second oxide layer; 402-second gate; 50-insulating material. DETAILED DESCRIPTION

[0025] In current Nor flash memory arrays, there is a PN junction between the channel regions of two adjacent storage tubes. The PN junction will cause a short channel effect, increase the leakage current of the storage tube, reduce the threshold voltage of the storage tube, and make the storage tube increasingly difficult to control and manufacture as the process node shrinks.

[0026] To this end, the present invention provides a Nor flash memory array, in which there is no PN junction between the channel regions of two adjacent storage tubes in the Nor flash memory array, which is beneficial to increasing the channel length of the storage tube, improving the controllability of the storage tube, and at the same time making the arrangement between the storage tubes more compact, thereby improving the performance and economy of the Nor flash memory array.

[0027] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the accompanying drawings are in very simplified form and in non-precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0028] Figure 1 A partial cross-sectional schematic diagram of a Nor flash memory array provided in accordance with an embodiment of the present invention. Figure 2 The following is a diagram of the architecture of a Nor flash memory array provided by an embodiment of the present invention. Figure 1 and Figure 2As shown, the Nor flash memory array provided in this embodiment includes a plurality of memory cells arranged in rows and columns, the plurality of memory cells are located within a well region 100 of a substrate 10, and each of the memory cells includes a plurality of memory tubes 20 connected in series; a first doping region 101 is provided at the top of the substrate of the well region 100, and in the same memory cell, gate structures of the plurality of memory tubes 20 are arranged above the substrate of the first doping region 101 along a column direction, and a region in the first doping region 101 corresponding to a position of a gate structure of a memory tube 20 is a channel region of a memory tube 20, no PN junction exists between the channel regions of two adjacent memory tubes 20, and two adjacent memory tubes 20 are connected in series via the first doping region 101 between the gate structures of the two adjacent memory tubes 20.

[0029] In this embodiment, the substrate 10 may be a silicon substrate, but is not limited thereto. In other embodiments, the substrate 10 may also be a germanium substrate, a silicon germanium substrate, a silicon on insulator (SOI) or a germanium on insulator (GOI), etc., and certain doping particles may be injected into the substrate 10 according to design requirements to change electrical parameters.

[0030] In this embodiment, the well region 100 may be formed by implanting dopants into the substrate 10 through an ion implantation process, and the well region 100 may be a P-well, but is not limited thereto. In other embodiments, the well region 100 may be an N-well.

[0031] In this embodiment, Figure 1 As shown, one storage unit includes 8 storage tubes, but is not limited thereto. In other embodiments, the number of storage tubes in one storage unit may be greater than 8.

[0032] In this embodiment, the storage tube 20 is a charge trap type storage tube, but is not limited thereto. In other embodiments, the storage tube 20 may also be a floating gate type storage tube. For example, Figure 1 As shown, the gate structure of the storage tube 20 may include a tunnel insulating layer, a charge trap layer, a blocking insulating layer and a gate electrode 202 stacked sequentially from bottom to top on the substrate 10. The materials of the tunnel insulating layer and the blocking insulating layer include silicon oxide, the material of the charge trap layer includes silicon nitride, and the tunnel insulating layer, the charge trap layer and the blocking insulating layer may be combined into an ONO layer 201.

[0033] In this embodiment, the region in the first doping region 101 corresponding to the gate structure position of a storage tube 20 is a channel region of a storage tube 20, and the channel of the storage tube 20 is a self-aligned channel. The first doping region 101 can be formed by ion implantation at the top of the substrate of the well region 100, and the threshold voltage of the storage tube 20 can be adjusted by controlling the conditions of the ion implantation process, so that the channel of the storage tube 20 is an intrinsic depletion mode channel, that is, the storage tube 20 is in a normally open mode. The storage tube 20 can obtain different threshold voltages by erasing or programming during data operation. The channels between the storage tubes 20 remain in a normally open mode.

[0034] refer to Figure 1 As shown, the gate structures of two adjacent storage tubes 20 are filled with an insulating material 50. The insulating material 50 may include at least one of oxide or nitride. In this embodiment, the distance between the gate structures of two adjacent storage tubes of the same storage unit is about 10 nm.

[0035] Continue to refer Figure 1 and Figure 2 As shown, each memory cell further includes a bit line selection tube 30 and a source line selection tube 40; in the same memory cell, the bit line selection tube 30 and the source line selection tube 40 are located at both ends of a plurality of memory tubes 20 connected in series, the end of the bit line selection tube 30 close to the memory tube is connected to the adjacent memory tube 20, the end of the source line selection tube 40 close to the memory tube is connected to the adjacent memory tube 20, and the end of the source line selection tube 40 away from the memory tube is connected to the common source line CSL. The bit line selection line BLG can extend along the row direction, and the gate structures of the bit line selection tubes 30 of the memory cells in the same row are electrically connected to the same bit line selection line, wherein the row direction is perpendicular to the column direction. The source line selection line SLG can extend along the row direction, and the gate structures of the source line selection tubes 40 of the memory cells in the same row are electrically connected to the same source line selection line.

[0036] In this embodiment, the bit line selection tube 30 and the source line selection tube 40 can be NMOS transistors, but are not limited thereto. In other embodiments, the bit line selection tube 30 and the source line selection tube 40 can also be PMOS transistors.

[0037] refer to Figure 1 and Figure 2 As shown, the Nor flash memory array also includes a plurality of bit lines (BL) and a plurality of word lines (WL). The bit lines can extend along the arrangement direction of the plurality of storage tubes 20 in the storage unit, that is, the bit lines can extend along the column direction, and one bit line electrically connects the ends of all the bit line selection tubes 30 in the storage units in the same column that are away from the storage tubes. The word lines can extend along the row direction, and one word line electrically connects the gate structures of all the storage tubes 20 in the same row of the storage units in the same row.

[0038] In this embodiment, multiple storage tubes 20 in the storage unit are connected to the bit line through the bit line selection tube 30 in the same storage unit, and multiple storage tubes 20 in the storage unit are connected to the common source line through the source line selection tube 40 in the same storage unit.

[0039] refer to Figure 1 As shown, the top of the substrate of the well region 100 has a second doping region 102 and a third doping region 103 located on both sides of the first doping region 101, and the second doping region 102 and the third doping region 103 are both connected to the first doping region 101; the gate structure of the bit line selection tube 30 is located above the substrate of the second doping region 102, and the second doping region 102 is the channel region of the bit line selection tube 30; the gate structure of the source line selection tube 40 is located above the substrate of the third doping region 103, and the third doping region 103 is the channel region of the source line selection tube 40.

[0040] It should be noted that by adjusting the injection conditions of the second doping region 102 and the third doping region 103, the threshold voltages of the bit line selection tube 30 and the source line selection tube 40 can be adjusted so that the channels of the bit line selection tube 30 and the source line selection tube 40 are both enhancement mode channels.

[0041] refer to Figure 1 As shown, the gate structure of the bit line selection transistor 30 includes a first oxide layer 301 on the substrate 10 and a first gate 302 on the first oxide layer 301. The gate structure of the source line selection transistor 40 includes a second oxide layer 401 on the substrate 10 and a second gate 402 on the second oxide layer 401.

[0042] In this embodiment, reference Figure 1 As shown, the first doped region 101 can extend to below the side surface of the gate structure of the bit line selection tube 30 close to the storage tube 20, that is, in the thickness direction of the substrate 10, the boundary of the first doped region 101 can be aligned with the side surface of the gate structure of the bit line selection tube 30 close to the storage tube 20. The first doped region 101 can also extend to below the side surface of the gate structure of the source line selection tube 40 close to the storage tube 20, that is, in the thickness direction of the substrate 10, the boundary of the first doped region 101 can be aligned with the side surface of the gate structure of the source line selection tube 40 close to the storage tube 20. Figure 1 In the horizontal direction, the first doping region 101 may be connected to the second doping region 102 , and the first doping region 101 may also be connected to the third doping region 103 .

[0043] The bit line selection tube 30 and the adjacent storage tube 20 can be connected through the first doping region 101; the source line selection tube 40 and the adjacent storage tube 20 can be connected through the first doping region 101, so that there is no need to form a doping region with a conductivity type different from that of the channel region of the storage tube between the gate structure of the bit line selection tube 30 and the gate structure of the adjacent storage tube, and between the gate structure of the source line selection tube 40 and the gate structure of the adjacent storage tube, which helps to shorten the distance between the gate structure of the storage tube and the gate structure of the bit line selection tube 30, and shorten the distance between the gate structure of the storage tube and the gate structure of the source line selection tube 40.

[0044] refer to Figure 1 As shown, a fourth doping region 104 and a fifth doping region 105 may also be formed on the top of the substrate of the well region 100. The fourth doping region 104 is located on the side of the gate structure of the bit line selection tube 30 away from the storage tube and connected to the second doping region 102. The fifth doping region 105 is located on the side of the gate structure of the source line selection tube 40 away from the storage tube and connected to the third doping region 103. In this embodiment, the fourth doping region 104 and the fifth doping region 105 can both be N-type doping regions, but are not limited thereto. The fourth doping region 104 is a source and drain region of the bit line selection tube 30, and the portion of the first doping region 101 close to the first gate 302 is another source and drain region of the bit line selection tube 30. The fifth doping region 105 is a source and drain region of the source line selection tube 40, and the portion of the first doping region 101 close to the second gate 402 is another source and drain region of the source line selection tube 40.

[0045] A bit line BL is formed on the substrate of the fourth doping region 104 and is electrically connected to the bit line BL. A common source line CSL is formed on the substrate of the fifth doping region 105 and is electrically connected to the common source line CSL.

[0046] In this embodiment, the FN tunneling effect can be used to perform both the erasing operation and the programming operation on the storage tube 20 .

[0047] Compared with the conventional Nor flash memory array, the Nor flash memory array provided in the present embodiment has the following characteristics: in the same storage unit, there is no need to form a source-drain region with a conductivity type different from that of the channel region between the channel regions of two adjacent storage tubes, there is no PN junction between the channel regions of two adjacent storage tubes 20, and the two adjacent storage tubes are connected through the first doping region between the gate structures of the two adjacent storage tubes, which is conducive to increasing the channel length of the storage tubes, enhancing the controllability of the storage tubes, improving the performance of the Nor flash memory array, and making the arrangement between the storage tubes more compact, which can save the effective area of ​​the chip, thereby reducing the chip size and improving the economy of the Nor flash memory array. In addition, the bit line selection tube and the source line selection tube are added to the storage unit, making the reading operation of the Nor flash memory array simple and convenient.

[0048] The present embodiment also provides an operation method of a Nor flash memory array, which is used to perform a read operation on the above-mentioned Nor flash memory array. The operation method of the Nor flash memory array includes: the storage cell to be read is called a selected storage cell, and the storage tube to be read in the selected storage cell is called a selected storage tube; the bit line selection line connected to the selected storage cell is applied with a first start-up voltage; the word line connected to the selected storage tube is applied with a first read voltage, and the other word lines connected to the selected storage cell are all applied with a second start-up voltage; the source line selection line connected to the selected storage cell is applied with a third start-up voltage; the common source line connected to the source line selection tube of the selected storage cell is applied with a zero volt voltage; the well region is applied with a zero volt voltage; the bit line connected to the selected storage cell is applied with a second read voltage; the bit line selection line and the source line selection line connected to the unselected storage cell in a different row from the selected storage cell are both applied with a zero volt voltage; and the word lines connected to the unselected storage cell in a different row from the selected storage cell are all applied with a zero volt voltage or suspended.

[0049] Figure 3 A schematic diagram of voltage application during a read operation of a Nor flash memory array provided by an embodiment of the present invention. Figure 3 As shown, taking the memory cell in the first row as the selected memory cell and the memory tube in the second row of the selected memory cell as the selected memory tube as an example, when performing a read operation, the bit line selection line BLG connected to the selected memory cell applies the first enable voltage Vpass1, so that the bit line selection tube 30 of the selected memory cell is turned on; the word line WL01 connected to the selected memory tube applies the first read voltage Vread1, and the other word lines WL00, WL02, ..., WLn connected to the selected memory cell all apply the second enable voltage Vpass2, so that the voltage on the bit line can be transmitted to the selected memory tube; the source line selection line SLG connected to the selected memory cell applies the third enable voltage Vpass2. The voltage Vpass3 turns on the source line selection tube 40 of the selected memory cell; a zero volt voltage is applied to the common source line CSL connected to the source line selection tube 40 of the selected memory cell; a zero volt voltage is applied to the well region, i.e., Vwell=0V; a second read voltage Vread2 is applied to the bit lines BL00, BL01, ..., BLm connected to the selected memory cell; a zero volt voltage is applied to the bit line selection line BLG and the source line selection line SLG connected to the unselected memory cells in different rows from the selected memory cell, i.e., the memory cells in the second row; and a zero volt voltage or a floating voltage is applied to the word lines connected to the unselected memory cells in different rows from the selected memory cell.

[0050] The second read voltage may be greater than the first read voltage; the first pass voltage may be equal to the third pass voltage. Exemplarily, during a read operation, the first pass voltage Vpass1 is 3V, the second pass voltage Vpass2 is 2.5V, the first read voltage Vread1 is 0V, the third pass voltage Vpass3 is 3V, and the second read voltage Vread2 is 0.6V, but not limited thereto.

[0051] The present embodiment also provides an operation method of a Nor flash memory array, which is used to perform programming operations on the above-mentioned Nor flash memory array. The operation method of the Nor flash memory array includes: calling a storage cell to be programmed a selected storage cell, calling a storage tube to be programmed in the selected storage cell a selected storage tube; applying a suppression voltage to a bit line selection line connected to the selected storage cell; applying a first positive voltage to a word line connected to the selected storage tube, applying a first negative voltage to a word line connected to a storage tube adjacent to the selected storage tube in the selected storage cell, and applying a start voltage to a word line connected to the remaining storage tubes in the selected storage cell; applying a second negative voltage to a source line selection line connected to the selected storage cell, the second negative voltage being less than the first negative voltage; applying a second negative voltage to a common source line connected to a source line selection tube of the selected storage cell; applying a second negative voltage to the well region; applying a second negative voltage to a bit line connected to the selected storage cell, applying a suppression voltage to a bit line connected to an unselected storage cell in the same row as the selected storage cell; and applying a second negative voltage to a bit line selection line, a source line selection line, and a word line connected to an unselected storage cell in a different row from the selected storage cell.

[0052] Figure 4 A schematic diagram of voltage application during programming operation of a Nor flash memory array provided by an embodiment of the present invention. Figure 4As shown, the memory cells in the first row and the first column are selected memory cells, the memory cells in the second row of the selected memory cells are selected memory cells, the memory cells in the second row and the memory cells in the second column to the m+1th column are all unselected memory cells, and when performing a programming operation, the bit line selection line BLG connected to the selected memory cells applies an inhibition voltage Vinhibit; the word line WL01 connected to the selected memory tube applies a first positive voltage Vhigh, the word lines WL00 and WL02 connected to the memory tubes adjacent to the selected memory tube in the selected memory cells apply a first negative voltage Vdecouple, and the word lines WLn connected to the remaining memory tubes in the selected memory cells apply a turn-on voltage Vpass; the bit line selection line BLG connected to the selected memory cells applies an inhibition voltage Vinhibit; the word line selection line WL01 connected to the selected memory tube applies a first positive voltage Vhigh; the word line selection line WL00 and WL02 connected to the memory tubes adjacent to the selected memory tube in the selected memory cells apply a first negative voltage Vdecouple; the word line selection line WLn connected to the selected memory cells applies a turn-on voltage Vpass; the word line selection line WLn connected to the selected memory cells applies a first positive voltage Vhigh ... negative voltage Vdecouple; the word line selection line WLn connected to the selected memory cells applies a first positive voltage Vhigh. The source line selection line SLG applies a second negative voltage Vlow, which is less than the first negative voltage Vdecouple; the common source line CSL connected to the source line selection tube 40 of the selected storage cell applies a second negative voltage Vlow; the second negative voltage is applied to the well region, that is, Vwell=Vlow; and the bit line BL00 connected to the selected storage cell is applied with a second negative voltage Vlow, and the bit lines BL01, ..., BLm connected to the unselected storage cells in the same row as the selected storage cell are applied with an inhibition voltage Vinhibit; and the bit line selection line BLG, the source line selection line SLG and the word line connected to the unselected storage cells in different rows from the selected storage cell are all applied with a second negative voltage Vlow.

[0053] Exemplarily, when performing a programming operation, the inhibition voltage Vinhibit is -1V, the first negative voltage Vdecouple is -3V, the second negative voltage Vlow is -6V, the first positive voltage Vhigh is 5V, and the pass voltage Vpass is -1V.

[0054] It should be noted that when the Nor flash memory array is programmed, a first negative voltage Vdecouple is applied to a word line connected to a storage tube adjacent to the selected storage tube in the selected storage cell. The first negative voltage Vdecouple is a clamping voltage, which turns off the storage tube adjacent to the selected storage tube. In this way, the channel region of the selected storage tube is isolated by the channel region of the adjacent storage tube, so that the parasitic capacitance of the selected storage tube becomes much smaller and the potential difference of the selected storage tube is higher, thereby helping to reduce the interference of the programming operation on the storage tube adjacent to the selected storage tube.

[0055] This embodiment also provides an operation method of a Nor flash memory array, which is used to perform an erasing operation on the above-mentioned Nor flash memory array. The operation method of the Nor flash memory array includes: the memory cell to be erased is called a selected memory cell; a positive voltage is applied to the bit line selection line connected to the selected memory cell; a negative voltage is applied to the word line connected to the selected memory cell; a positive voltage is applied to the source line selection line connected to the selected memory cell; a positive voltage is applied to the common source line connected to the source line selection tube of the selected memory cell; a positive voltage is applied to the well region; a positive voltage is applied to the bit line connected to the selected memory cell; and a positive voltage is applied to the bit line selection line, source line selection line and word line connected to the unselected memory cells in different rows from the selected memory cell.

[0056] Figure 5 A schematic diagram of voltage application during an erase operation of a Nor flash memory array provided by an embodiment of the present invention. Figure 5 As shown, the memory cells in the first row are selected memory cells. Taking all the memory tubes in the selected memory cells as the selected memory tubes as an example, when performing an erase operation, a positive voltage Vhigh is applied to the bit line selection line BLG connected to the selected memory cell; a negative voltage Vlow is applied to the word lines WL00, ..., WLn connected to the selected memory cell, and a positive voltage Vhigh is applied to the source line selection line SLG connected to the selected memory cell; a positive voltage Vhigh is applied to the common source line CSL connected to the source line selection tube of the selected memory cell; a positive voltage is applied to the well region, that is, Vwell=Vhigh; a positive voltage Vhigh is applied to the bit lines BL00, ..., BLm connected to the selected memory cell; and a positive voltage Vhigh is applied to the bit line selection line, source line selection line and word line of the unselected memory cells in different rows from the selected memory cells, that is, the memory cells in the second row.

[0057] Exemplarily, during the erase operation, the positive voltage Vhigh is 6V and the negative voltage Vlow is -6V, but this is not limited thereto.

[0058] It should be noted that when the read operation, programming operation and erasing operation are performed on the above-mentioned Nor flash memory array, the operations are performed based on the threshold voltage distribution of the erased state of the storage tube being negative and the threshold voltage distribution of the programmed state being positive.

[0059] The above description is only a description of the preferred embodiment of the present invention, and is not any limitation on the scope of rights of the present invention. Any technical personnel in this field can make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.

Claims

1. A Nor flash memory array, characterized in that: The invention comprises a plurality of memory cells arranged in rows and columns, wherein the plurality of memory cells are located within a well region of a substrate, and each of the memory cells comprises a plurality of memory tubes connected in series; the top of the substrate of the well region has a first doping region, and in the same memory cell, the gate structures of the plurality of memory tubes are arranged above the substrate of the first doping region in a column direction, and only insulating material is filled between the gate structures of two adjacent memory tubes, and the region in the first doping region corresponding to the position of the gate structure of one memory tube is a channel region of one memory tube, and no PN junction exists between the channel regions of the two adjacent memory tubes, And two adjacent storage tubes are connected through the first doping region between the gate structures of the two adjacent storage tubes; each of the storage units also includes a bit line selection tube and a source line selection tube; in the same storage unit, the bit line selection tube and the source line selection tube are located at both ends of the multiple storage tubes connected in series, the end of the bit line selection tube close to the storage tube is connected to the adjacent storage tube, the end of the bit line selection tube away from the storage tube is connected to the bit line, the end of the source line selection tube close to the storage tube is connected to the adjacent storage tube, and the end of the source line selection tube away from the storage tube is connected to the common source line.

2. The Nor flash memory array according to claim 1, wherein: The gate structures of the bit line selection tubes of the storage cells in the same row are electrically connected to the same bit line selection line; the gate structures of the source line selection tubes of the storage cells in the same row are electrically connected to the same source line selection line.

3. The Nor flash memory array according to claim 2, wherein: The Nor flash memory array also includes multiple bit lines and multiple word lines; one of the bit lines is electrically connected to the end of the bit line selection tube away from the storage tube in the storage cells in the same column; and one of the word lines is electrically connected to the gate structure of the storage tube in the same row of the storage cells in the same row.

4. The Nor flash memory array according to claim 2, wherein: The top of the substrate of the well region has a second doping region and a third doping region located on both sides of the first doping region, and the second doping region and the third doping region are both connected to the first doping region; the gate structure of the bit line selection tube is located above the substrate of the second doping region, and the second doping region is the channel region of the bit line selection tube; the gate structure of the source line selection tube is located above the substrate of the third doping region, and the third doping region is the channel region of the source line selection tube; a fourth doping region and a fifth doping region are also formed on the top of the substrate of the well region, the fourth doping region is located on the side of the gate structure of the bit line selection tube away from the storage tube and connected to the second doping region, the fifth doping region is located on the side of the gate structure of the source line selection tube away from the storage tube and connected to the third doping region, a bit line is formed above the substrate of the fourth doping region, and the fourth doping region is electrically connected to the bit line, a common source line is formed above the substrate of the fifth doping region, and the fifth doping region is electrically connected to the common source line.

5. The Nor flash memory array according to claim 4, wherein: The bit line selection tube is connected to the adjacent storage tube via the first doping region; the source line selection tube is connected to the adjacent storage tube via the first doping region.

6. The Nor flash memory array according to claim 4, wherein: The channel of the bit line selection tube and the channel of the source line selection tube are both enhancement type channels.

7. The Nor flash memory array according to any one of claims 1 to 6, characterized in that: The channel of the storage tube is a self-aligned intrinsic depletion channel.

8. A method for operating a Nor flash memory array, for performing a read operation on the Nor flash memory array as claimed in claim 3, characterized in that: include: The storage unit to be read is called a selected storage unit, and the storage tube to be read in the selected storage unit is called a selected storage tube; Applying a first turn-on voltage to the bit line selection line connected to the selected memory cell; The word line connected to the selected storage tube is applied with a first read voltage, and the other word lines connected to the selected storage unit are all applied with a second start voltage; Applying a third start-up voltage to the source line selection line connected to the selected storage unit; A zero volt voltage is applied to the common source line connected to the source line selection tube of the selected storage unit; applying a zero volt voltage to the well region; Applying a second read voltage to the bit line connected to the selected memory cell; A zero volt voltage is applied to both the bit line selection line and the source line selection line connected to the unselected memory cells in the different rows from the selected memory cell; and The word lines connected to the unselected memory cells in different rows from the selected memory cell are all applied with a zero volt voltage or are suspended.

9. A method for operating a Nor flash memory array, for performing a programming operation on the Nor flash memory array as claimed in claim 3, characterized in that: include: The storage unit that needs to be programmed is called a selected storage unit, and the storage tube that needs to be programmed in the selected storage unit is called a selected storage tube; The bit line selection line connected to the selected memory cell applies an inhibition voltage; A first positive voltage is applied to the word line connected to the selected storage tube, a first negative voltage is applied to the word line connected to the storage tube adjacent to the selected storage tube in the selected storage unit, and a turn-on voltage is applied to the word lines connected to the remaining storage tubes in the selected storage unit; A second negative voltage is applied to the source line selection line connected to the selected storage unit, and the second negative voltage is less than the first negative voltage; A second negative voltage is applied to the common source line connected to the source line selection tube of the selected storage unit; applying a second negative voltage to the well region; A second negative voltage is applied to the bit line connected to the selected memory cell, and an inhibition voltage is applied to the bit lines connected to other memory cells in the same row as the selected memory cell; as well as The second negative voltage is applied to the bit line selection line, the source line selection line and the word line connected to the unselected memory cells in the different row from the selected memory cell.

10. A method for operating a Nor flash memory array, for performing an erase operation on the Nor flash memory array as claimed in claim 3, characterized in that: include: The storage cell that needs to be erased is called a selected storage cell; A positive voltage is applied to the bit line selection line connected to the selected memory cell; A negative voltage is applied to the word line connected to the selected memory cell; A positive voltage is applied to the source line selection line connected to the selected storage unit; A positive voltage is applied to the common source line connected to the source line selection tube of the selected storage unit; applying a positive voltage to the well region; A positive voltage is applied to the bit line connected to the selected memory cell; as well as Positive voltages are applied to the bit line selection lines, source line selection lines and word lines connected to the unselected memory cells in different rows from the selected memory cell.

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