A self-aligned trench silicon carbide hybrid diode structure and preparation method thereof

Abstract

The present invention belongs to the field of semiconductor technology, and specifically relates to a self-aligned trench-type silicon carbide hybrid diode structure and a preparation method thereof. The semiconductor structure disclosed in the present invention includes: an N+ silicon carbide substrate; an N-buffer layer, arranged above the N+ silicon carbide substrate; an N-drift layer, arranged above the N-buffer layer; a plurality of grooves are etched in the N-drift layer, and the plurality of grooves are not interconnected and are arranged in a vertical direction; an oxide layer, arranged on the inner surface of the groove; a filling layer, arranged in the oxide layer, the top of the filling layer coincides with the upper surface of the N-drift layer and a first P-type barrier region, etc. The semiconductor structure of the present invention has the characteristics of low conduction voltage drop and low leakage current. Based on the self-alignment process, the present invention can realize a multi-level trench-type silicon carbide hybrid diode device structure without adding an additional mask layer, so as to optimize the forward conduction characteristics and the reverse leakage current performance.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductors, and in particular relates to a self-aligned trench type silicon carbide hybrid diode structure and a preparation method thereof. Background Art

[0002] The existing method for manufacturing trench-type silicon carbide diodes is to first make a trench structure on the surface of a silicon carbide wafer, then perform ion implantation on the surface and sides of the trench, form a P-type ion implantation area after high-temperature annealing, and use the conductive channel formed between the two P-type implantation areas to achieve the control of the forward conduction voltage drop and reverse leakage current of the device. This method is prone to uneven distribution of implanted ions on both sides of the trench when ion implantation is performed on the sidewalls of the trench, which has high requirements on equipment and high process difficulty.

[0003] As a wide bandgap semiconductor material, silicon carbide has better properties than silicon. Its bandgap width is three times that of silicon, its critical breakdown electric field is 10 times that of silicon, and its thermal conductivity is four times that of silicon. Power devices made of silicon carbide have higher operating frequencies, lower losses, higher operating temperatures and power densities than silicon devices, and are particularly suitable for use in high-voltage, high-power, high-temperature, and radiation-resistant power electronic devices.

[0004] Due to the high breakdown field strength of silicon carbide materials, silicon carbide diodes can easily achieve device characteristics with both low on-state voltage drop and high withstand voltage (1200V and above). Among the silicon carbide diodes reported so far, devices with a breakdown capability of more than 10kV have been manufactured, and have very broad application prospects in the fields of rail transportation and ultra-high voltage power transmission. A trench silicon carbide diode is a diode that changes the leakage current of the device by utilizing a trench structure to reduce the surface electric field of the device when a reverse bias is applied to the device. Silicon carbide diode devices with this structure have the characteristics of low leakage and low forward conduction voltage drop, and are suitable for use in high-voltage devices.

[0005] like Figure 1 and Figure 2 , the patent CN 114628499 A in the prior art discloses a silicon carbide diode with a groove. The invention forms a P-type injection region by ion implantation on the sidewall and bottom of the groove, sets an ohmic contact in the groove, and sets a Schottky contact on the surface of the epitaxial layer between the two grooves. The silicon carbide diode with this structure overcomes the Schottky barrier at low voltage and achieves the effect of forward conduction. In the surge state (VF>2.7V), the silicon carbide PN junction is turned on, the current increases, and a better surge current discharge effect is achieved. Figure 2Although the structure has good forward conduction capability, at low voltage (VF<2.7V), only the Schottky interface is turned on, the current density is small, and the device loss is large, so it still has major defects.

[0006] In addition, the existing method for making trench-type silicon carbide diodes is to first make a trench structure on the surface of a silicon carbide wafer, then perform ion implantation on the surface and side of the trench, form a P-type ion implantation area after high-temperature annealing, and use the conductive channel formed between the two P-type implantation areas to achieve the control of the forward conduction voltage drop and reverse leakage current of the device. When this method performs ion implantation on the sidewalls of the trench, it is easy to cause uneven distribution of implanted ions on both sides of the trench, which has high requirements on equipment and high process difficulty. Summary of the invention

[0007] An object of the present invention is to provide a self-aligned trench type silicon carbide hybrid diode structure.

[0008] The second object of the present invention is to provide a method for preparing the above structure.

[0009] The structure provided by the present invention is based on the traditional trench Schottky diode, and a gate-controlled diode is introduced at the anode to form a trench hybrid silicon carbide diode structure. The structure has the characteristics of low conduction voltage drop and low leakage current. At the same time, based on the self-alignment process, the present invention can realize a multi-level trench hybrid silicon carbide diode device structure without adding an additional mask layer, so as to achieve the performance of optimizing the forward conduction characteristics and reverse leakage current. The manufacturing method proposed by the present invention has low requirements on equipment, is compatible with existing manufacturing processes, has low cost, and can achieve large-scale production.

[0010] According to a first aspect of the present invention, the present invention discloses a self-aligned trench type silicon carbide hybrid diode structure, comprising:

[0011] N+ silicon carbide substrate;

[0012] An N-buffer layer, disposed above the N+ silicon carbide substrate;

[0013] An N-drift layer, disposed above the N-buffer layer;

[0014] A plurality of grooves are formed by etching in the N-drift layer, wherein the plurality of grooves are not interconnected and are arranged in a vertical direction;

[0015] An oxide layer, disposed on the inner surface of the groove;

[0016] A filling layer, disposed in the oxide layer, wherein a top of the filling layer overlaps with an upper surface of the N-drift layer;

[0017] a first P-type barrier region, wherein an upper surface of the first P-type barrier region coincides with a bottom surface of the trench;

[0018] An N-type implantation region is disposed on the sidewall of the trench and has an upper surface that overlaps with an upper surface of the N-drift layer;

[0019] A P-type base region, arranged on the bottom surface and side walls of the N-type implantation region;

[0020] A first ohmic contact layer is disposed on the upper surface of the P-type base region, the N-type implantation region and the trench;

[0021] A Schottky contact layer, disposed on the upper surfaces of the N-drift layer and the first ohmic contact layer;

[0022] An anode metal layer is disposed on the upper surface of the Schottky contact layer;

[0023] A second ohmic contact layer is disposed on the lower surface of the N+ silicon carbide substrate;

[0024] The cathode metal layer is disposed on the lower surface of the second ohmic contact layer.

[0025] According to one embodiment of the present invention, the doping concentration of the N+ silicon carbide substrate is 1e19cm -3 above.

[0026] According to one embodiment of the present invention, the doping concentration of the N-buffer layer is 1e18-9e18cm -3 , thickness is 0.2-0.8μm.

[0027] According to one embodiment of the present invention, the doping concentration of the N-drift layer is 5e14-9e17cm -3 , thickness is 3-30μm.

[0028] According to one embodiment of the present invention, the doping concentration of the first P-type barrier region is 1e18 cm -3 The thickness is smaller than the depth of the trench or the depth of the N-type implantation region.

[0029] According to an embodiment of the present invention, the thickness of the P-type base region is smaller than the depth of the trench.

[0030] According to one embodiment of the present invention, the doping concentration of the N-type implantation region is 1e19cm -3 In the above, the bottom of the N-type implantation region is higher than the bottom of the trench.

[0031] According to an embodiment of the present invention, the bottom of the trench further includes a multi-step structure, and the step structure is provided with a second P-type barrier region whose top overlaps with an upper surface of the step structure and whose sidewalls overlap with sidewalls of the step structure.

[0032] According to an embodiment of the present invention, the bottom of the second P-type barrier region is higher than the top of the first P-type barrier region.

[0033] According to a second aspect of the present invention, the present invention further discloses a method for preparing a self-aligned trench-type silicon carbide hybrid diode structure, comprising:

[0034] S01, providing an N+ silicon carbide substrate, forming an N-buffer layer by epitaxial growth on the N+ silicon carbide substrate, and forming an N-drift layer by epitaxial growth on the N-buffer layer;

[0035] S02, forming a first barrier layer on the N-drift layer, etching the first barrier layer to form an implantation region, and forming a P-type base region by ion implantation into the N-drift layer;

[0036] S03, forming a second barrier layer on the P-type base region, etching the second barrier layer to form an implantation region, and performing ion implantation on the N-drift layer to form an N-type implantation region;

[0037] S04, forming a third barrier layer on the N-type implantation region, etching the third barrier layer to open a window, and forming a groove by etching the N-drift layer;

[0038] S05, performing ion implantation at the bottom of the trench to form a first P-type barrier region, and then removing the first barrier layer, the second barrier layer, and the third barrier layer that have not been etched;

[0039] S06, forming an oxide layer on the inner surface of the groove;

[0040] S07, forming a filling layer in the oxide layer;

[0041] S08, forming a first ohmic contact layer on the P-type base region, the N-type implantation region and the trench;

[0042] S09, forming a Schottky contact layer on the N-drift layer and the first ohmic contact layer;

[0043] forming an anode metal layer on the Schottky contact layer;

[0044] S10, forming a second ohmic contact layer on the lower surface of the N+ silicon carbide substrate;

[0045] A cathode metal layer is formed on the lower surface of the second ohmic contact layer.

[0046] According to an embodiment of the present invention, the etching depth of the trench in step S04 is greater than the thickness of the P-type base region.

[0047] According to an embodiment of the present invention, in step S04, a trench is formed between the N-drift layer, the P-type base region and the N-type implantation region.

[0048] The present invention has the following beneficial effects:

[0049] 1. The structure of the present invention has the characteristics of low on-state voltage drop and low leakage current;

[0050] 2. Based on the self-alignment process, the present invention can realize a multi-level trench-type silicon carbide hybrid diode device structure without adding an additional mask layer, thereby optimizing the forward conduction characteristics and the reverse leakage current performance;

[0051] 3. The production method proposed in the present invention has low requirements on equipment, is compatible with existing manufacturing processes, has low cost, and can achieve large-scale production. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Figure 1 It is a schematic diagram of the forward conduction current density of a silicon carbide diode with a groove at low voltage in the prior art;

[0053] Figure 2 It is a schematic diagram of the forward conduction current density of a silicon carbide diode with a groove in the prior art under surge voltage;

[0054] Figure 3 A schematic diagram of the structure of a self-aligned trench-type silicon carbide hybrid diode provided by the present invention;

[0055] Figure 4 A schematic diagram of a local equivalent circuit of a self-aligned trench silicon carbide hybrid diode structure provided by the present invention;

[0056] Figure 5 A schematic diagram of the circuit structure of a self-aligned trench silicon carbide hybrid diode structure provided by the present invention;

[0057] Figure 6 A schematic diagram of the forward conduction current density of a self-aligned trench silicon carbide hybrid diode structure provided by the present invention at low voltage;

[0058] Figure 7 A schematic diagram of the forward conduction current density of a self-aligned trench silicon carbide hybrid diode structure provided by the present invention under surge voltage;

[0059] Figure 8 A flow chart of a method for preparing a self-aligned trench-type silicon carbide hybrid diode structure in one embodiment of the present invention;

[0060] Fig. 9This is a schematic diagram of a structure obtained in step S01 of a method for preparing a self-aligned trench type silicon carbide hybrid diode structure in one embodiment of the present invention;

[0061] Fig.10 This is a schematic diagram of a structure obtained in step S02 of a method for preparing a self-aligned trench-type silicon carbide hybrid diode structure in one embodiment of the present invention;

[0062] Fig.11 This is a schematic diagram of a structure obtained in step S03 of a method for preparing a self-aligned trench-type silicon carbide hybrid diode structure in one embodiment of the present invention;

[0063] Fig.12 This is a schematic diagram of a structure obtained in step S04 of a method for preparing a self-aligned trench type silicon carbide hybrid diode structure in one embodiment of the present invention;

[0064] Fig.13 This is a schematic diagram of a structure obtained in step S05 of a method for preparing a self-aligned trench type silicon carbide hybrid diode structure in one embodiment of the present invention;

[0065] Fig.14 This is a schematic diagram of a structure obtained in step S06 of a method for preparing a self-aligned trench type silicon carbide hybrid diode structure in one embodiment of the present invention;

[0066] Fig.15 This is a schematic diagram of a structure obtained in step S07 of a method for preparing a self-aligned trench-type silicon carbide hybrid diode structure in one embodiment of the present invention;

[0067] Fig.16 This is a schematic diagram of a structure obtained in step S08 of a method for preparing a self-aligned trench type silicon carbide hybrid diode structure in one embodiment of the present invention;

[0068] Fig.17 This is a schematic diagram of a structure obtained in step S09 of a method for preparing a self-aligned trench-type silicon carbide hybrid diode structure in one embodiment of the present invention;

[0069] Fig.18 A schematic diagram of the device structure of another self-aligned trench silicon carbide hybrid diode structure provided by the present invention. DETAILED DESCRIPTION

[0070] The technical solution of the embodiment of the present invention is described in detail below with reference to the accompanying drawings.

[0071] The following embodiments are only used to more clearly illustrate the technical solutions of the present invention, and are therefore only used as examples, and cannot be used to limit the scope of protection of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0072] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs; the terms used herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0073] In the description of the present invention, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device comprising a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products or devices.

[0074] In the description of the embodiments of the present invention, the orientations or positional relationships indicated by technical terms such as "up", "down", "top", "bottom", "side", "height", "width", "thickness", "depth", "horizontal" and "vertical" are based on the orientations or positional relationships shown in the accompanying drawings and are only for the convenience of describing the embodiments of the present invention and simplifying the description. They do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the embodiments of the present invention.

[0075] In the description of the embodiments of the present invention, the term "and / or" is only a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B may represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0076] In the description of the embodiments of the present invention, the technical terms "first", "second", "third", etc. are only used to distinguish different objects, and cannot be understood as indicating or implying relative importance or implicitly indicating the number, specific order or primary and secondary relationship of the indicated technical features. In the description of the embodiments of the present invention, the meaning of "multiple" is more than two, unless otherwise clearly and specifically defined.

[0077] Reference to "embodiments" in the present invention means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present invention. The appearance of the phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described in the present invention may be combined with other embodiments.

[0078] Please refer to Figure 3 , Figure 4 and Figure 5 According to one embodiment of the present invention, a self-aligned trench-type silicon carbide hybrid diode structure comprises:

[0079] N+ silicon carbide substrate;

[0080] An N-buffer layer, disposed above the N+ silicon carbide substrate;

[0081] An N-drift layer, disposed above the N-buffer layer;

[0082] A plurality of grooves are formed by etching in the N-drift layer, wherein the plurality of grooves are not interconnected and are arranged in a vertical direction;

[0083] An oxide layer, disposed on the inner surface of the groove;

[0084] A filling layer, disposed in the oxide layer, wherein a top of the filling layer overlaps with an upper surface of the N-drift layer;

[0085] a first P-type barrier region, wherein an upper surface of the first P-type barrier region coincides with a bottom surface of the trench;

[0086] An N-type implantation region is disposed on the sidewall of the trench and has an upper surface that overlaps with an upper surface of the N-drift layer;

[0087] A P-type base region, arranged on the bottom surface and side walls of the N-type implantation region;

[0088] A first ohmic contact layer is disposed on the upper surface of the P-type base region, the N-type implantation region and the trench;

[0089] A Schottky contact layer, disposed on the upper surfaces of the N-drift layer and the first ohmic contact layer;

[0090] An anode metal layer is disposed on the upper surface of the Schottky contact layer;

[0091] A second ohmic contact layer is disposed on the lower surface of the N+ silicon carbide substrate;

[0092] The cathode metal layer is disposed on the lower surface of the second ohmic contact layer.

[0093] Correspondingly, the description of each structure is as follows:

[0094] N+ SiC substrate: doping concentration is 1e19cm -3 above.

[0095] N-buffer layer: doping concentration is 1e18-9e18cm -3 , the thickness is 0.2-0.8μm, more preferably 0.5μm.

[0096] N-drift layer: The doping concentration is determined according to the device withstand voltage setting, and the doping concentration is 5e14-9e17cm -3 , thickness is 3-30μm.

[0097] The first P-type barrier region is doped with Al impurities at a concentration of 1e18 cm -3 The first P-type barrier region is located directly below the trench structure and wraps the bottom of the trench, thereby reducing the electric field strength at the bottom of the trench when the device is in reverse cutoff and protecting the trench structure.

[0098] Oxide layer: The material of the oxide layer can be selected from at least one of SiO2, SiN, and HfO2, and is arranged on the inner surface of the groove to have an insulating effect. Moreover, the filling layer arranged in the oxide layer in the groove is made of a conductive material, including but not limited to highly doped polysilicon.

[0099] P-type base region: doped with Al impurities, the doping concentration is determined according to design requirements, affected by the concentration of the N-drift layer and the thickness of the oxide layer in the trench, and its thickness is less than the depth of the trench;

[0100] N-type implantation area: doping concentration is 1e19cm -3 In the above, the depth of the N-type injection region is less than the depth of the P-type base region, and is formed by high-temperature annealing after ion implantation. The doped impurity is N. The upper surface of the N-type injection region can form a good ohmic contact with the ohmic contact layer, and its bottom is higher than the bottom of the groove. The N-type injection region and the N-drift layer are separated by the P-type base region.

[0101] The first ohmic contact layer is formed by depositing metal on the P-type base region, the N-type implantation region and the upper surface of the trench, wherein the metal includes but is not limited to Ti, Ni or Pt.

[0102] Schottky contact layer: A Schottky contact layer is arranged above the N-drift layer except for the ohmic contact layer region to form a good Schottky contact with the N-drift layer. Meanwhile, an anode metal layer is arranged above the Schottky contact layer to serve as the anode of the trench silicon carbide hybrid diode.

[0103] First ohmic contact layer: an ohmic contact layer is arranged on the lower surface of the N+ silicon carbide substrate to form a good ohmic contact; a cathode metal layer is arranged on the lower surface of the ohmic contact layer to serve as the cathode of the trench silicon carbide hybrid diode.

[0104] In one embodiment of the present invention, the bottom of the groove also includes a multi-step structure, and the step structure is provided with a second P-type barrier region whose top coincides with the upper surface of the step structure and whose sidewalls coincide with the sidewalls of the step structure, wherein the bottom of the second P-type barrier region is higher than the top of the first P-type barrier region.

[0105] The present invention introduces a gate-controlled diode at the anode on the basis of the traditional trench-type Schottky diode to form a trench-type silicon carbide hybrid diode structure. Figure 4 and Figure 5 As shown, the Schottky contact layer and the epitaxial layer interface form a Schottky diode, wherein the trench structure is equivalent to the gate of the trench field effect transistor, and the anode metal layer is equivalent to the source of the field effect transistor. The gate source is short-circuited in the present invention to form a gate-controlled diode, which is connected in parallel with the Schottky diode to form a hybrid diode structure. When a positive voltage is applied to the anode, the Schottky diode and the gate-controlled diode can be turned on, thereby increasing the on-current density of the device and reducing the on-power consumption of the device.

[0106] Correspondingly, when it is in the forward conduction state, a positive voltage is applied to the anode, and when the cathode voltage is 0, the potential of the anode metal layer and the filling layer in the groove are the same. As the positive voltage applied to the anode continues to increase, the Schottky barrier is broken through, and a forward conduction current is generated. At the same time, as the anode voltage increases, the potential of the filling layer in the groove is the same as the potential of the anode metal layer. Therefore, an enhanced conductive channel is formed at the interface between the oxide layer on the side of the groove and the silicon carbide in the P-type base region, and the gate-controlled diode device is turned on. The current density is as follows Figure 6 shown.

[0107] In the surge state, the voltage applied by the anode is very high, exceeding the turn-on voltage of the silicon carbide PN junction (about 2.7V). The PN junction between the P-type base region and the N-drift layer is turned on, and ions are implanted into the N-drift layer, which greatly reduces the on-resistance of the device and increases the forward current sharply. Figure 7 This structure can effectively increase the current density of the diode and improve the forward surge capability.

[0108] In some embodiments of the present invention, the N-buffer layer is N-type doped, with a doping concentration ranging from 1e18 cm-3 to 9e18 cm-3 and a thickness of about 0.5 μm.

[0109] In some embodiments of the present invention, the N-drift layer is located above the N-buffer layer, has a doping concentration of 5e14 cm-3 to 9e17 cm-3, and a thickness of 3 μm-30 μm.

[0110] In some embodiments of the present invention, the first P-type barrier region is P-type doped with a doping concentration of 1e18 cm-3 or more, and can be formed by, for example, implantation of Al ions.

[0111] According to an embodiment of the present invention, the N-type implantation region is N-type doped, with a doping concentration of 1e19 cm-3, which can be formed by, for example, N doping.

[0112] According to one embodiment of the present invention, the P-type base region is P-type doped with a doping concentration of 1e19 cm-3, which can be formed by, for example, implantation of Al ions.

[0113] The above structure has the characteristics of low on-state voltage drop and low leakage current.

[0114] The method for preparing the above structure comprises:

[0115] S01, providing an N+ silicon carbide substrate, forming an N-buffer layer by epitaxial growth on the N+ silicon carbide substrate, and forming an N-drift layer by epitaxial growth on the N-buffer layer;

[0116] S02, forming a first barrier layer on the N-drift layer, etching the first barrier layer to form an implantation region, and forming a P-type base region by ion implantation into the N-drift layer;

[0117] S03, forming a second barrier layer on the P-type base region, etching the second barrier layer to form an implantation region, and performing ion implantation on the N-drift layer to form an N-type implantation region;

[0118] S04, forming a third barrier layer on the N-type implantation region, etching the third barrier layer to open a window, and forming a groove by etching the N-drift layer;

[0119] S05, performing ion implantation at the bottom of the trench to form a first P-type barrier region, and then removing the first barrier layer, the second barrier layer, and the third barrier layer that have not been etched;

[0120] S06, forming an oxide layer on the inner surface of the groove;

[0121] S07, forming a filling layer in the oxide layer;

[0122] S08, forming a first ohmic contact layer on the P-type base region, the N-type implantation region and the trench;

[0123] S09, forming a Schottky contact layer on the N-drift layer and the first ohmic contact layer;

[0124] forming an anode metal layer on the Schottky contact layer;

[0125] S10, forming a second ohmic contact layer on the lower surface of the N+ silicon carbide substrate;

[0126] A cathode metal layer is formed on the lower surface of the second ohmic contact layer.

[0127] In one embodiment of the present invention, the etching depth of the trench in step S04 is greater than the thickness of the P-type base region.

[0128] In one embodiment of the present invention, in step S04, a trench is formed between the N-drift layer, the P-type base region and the N-type implantation region.

[0129] The present invention is based on a self-alignment process and can realize a multi-level trench-type silicon carbide hybrid diode device structure without adding an additional mask layer, thereby optimizing the forward conduction characteristics and the reverse leakage current performance; and has low requirements on equipment, is compatible with existing manufacturing processes, has low cost, and can be mass-produced.

[0130] Please refer to the attached Figure 8 And attached Figure 9-17 In one embodiment of the present invention, the method for preparing the above device comprises:

[0131] S01, providing an N+ silicon carbide substrate, forming an N-buffer layer by epitaxial growth on the N+ silicon carbide substrate, and forming an N-drift layer by epitaxial growth on the N-buffer layer, see Fig. 9 ;

[0132] S02, forming a first barrier layer on the N-drift layer, and etching the first barrier layer to form an implantation region, and forming a P-type base region by ion implantation into the N-drift layer, see Fig.10 ;

[0133] In one embodiment of the present invention, S02, a first barrier layer is grown and implanted on the N-drift layer and a window is opened, and then P-type ion implantation is performed on the N-drift layer to form a P-type base region;

[0134] S03, forming a second barrier layer on the P-type base region, and etching the second barrier layer to form an implantation region, and forming an N-type implantation region by ion implantation into the N-drift layer, see Fig.11 ;

[0135] In one embodiment of the present invention, S03, on the basis of S02, a second barrier layer is deposited and injected, and the second barrier layer covers the top, sidewall and top of the P-type base region of the first barrier layer in S02, and then dry etching is performed, and the etching depth is the thickness of the injected second barrier layer, and the first barrier layer and part of the second barrier layer above the P-type base region are removed, so that the second barrier layer on the sidewall of the injected first barrier layer is retained, and the thickness of the retained second barrier layer is the same above each P-type base region, forming a self-aligned process; then N-type ion implantation is performed to form an N-type implantation region, wherein the thickness of the retained second barrier layer is the distance between the left and right edges of the P-type base region and the left and right edges of the N-type implantation region, see Fig.11 ;

[0136] S04, forming a third barrier layer on the N-type implantation region, etching the third barrier layer to open a window, and etching the N-drift layer to form a groove, see Fig.12 ;

[0137] In one embodiment of the present invention, S04, on the basis of S03, a third barrier layer is deposited and etched on the implanted first barrier layer, the retained second barrier layer and the N-type implant region, and a partial area above the N-type implant region is etched by a self-aligned process to expose the surface of the silicon carbide material, and the exposed silicon carbide material is etched to a depth greater than a depth of the P-type base region, thereby forming a trench structure in the N-drift layer, the P-type base region and the N-type implant region;

[0138] S05, performing ion implantation at the bottom of the trench to form a first P-type barrier region, and then removing the unetched first barrier layer, the second barrier layer and the third barrier layer, see Fig.13 ;

[0139] S06, forming an oxide layer on the inner surface of the groove, see Fig.14 ;

[0140] S07, forming a filling layer in the oxide layer, see Fig.15 ;

[0141] S08, forming a first ohmic contact layer on the P-type base region, the N-type implantation region and the trench, see Fig.16 ;

[0142] S09, forming a Schottky contact layer on the N-drift layer and the first ohmic contact layer;

[0143] An anode metal layer is formed on the Schottky contact layer. Fig.17 ;

[0144] S10, forming a second ohmic contact layer on the lower surface of the N+ silicon carbide substrate;

[0145] A cathode metal layer is formed on the lower surface of the second ohmic contact layer to obtain Figure 3 The structure shown.

[0146] Furthermore, the preparation method provided by the present invention can be used to prepare a conventional trench structure, and can also be used to prepare a multi-level trench diode device structure. Fig.18 The bottom of the groove also includes a multi-step structure, which includes a groove bottom and steps higher than the groove bottom and located on both sides. Each step of the step structure is provided with a second blocking region whose top overlaps with the upper surface of the step structure and whose sidewall overlaps with the sidewall of the step structure. The width of the first P-type blocking region at the bottom of the groove is greater than that of the second P-type blocking region.

[0147] Furthermore, as a further improvement to the above structure, the height of the second barrier region is lower than the step height. The doping concentration of the second P-type barrier region can be consistent with that of the first P-type barrier region, or can be adjusted to change the current density.

[0148] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention, and they should all be included in the scope of the claims and specification of the present invention. In particular, as long as there is no structural conflict, the various technical features mentioned in each embodiment can be combined in any way. The present invention is not limited to the specific embodiments disclosed herein, but includes all technical solutions that fall within the scope of the claims.

Claims

1. A method for preparing a self-aligned trench-type silicon carbide hybrid diode structure, characterized in that: The following steps are involved: S01, providing an N+ silicon carbide substrate, forming an N-buffer layer by epitaxial growth on the N+ silicon carbide substrate, and forming an N-drift layer by epitaxial growth on the N-buffer layer; S02, forming a first barrier layer on the N-drift layer, etching the first barrier layer to form an implantation region, and forming a P-type base region by ion implantation into the N-drift layer; S03, forming a second barrier layer on the P-type base region, etching the second barrier layer to form an implantation region, and performing ion implantation on the N-drift layer to form an N-type implantation region; S04, forming a third barrier layer on the N-type implantation region, etching the third barrier layer to open a window, and forming a groove by etching the N-drift layer; S05, performing ion implantation at the bottom of the trench to form a first P-type barrier region, and then removing the first barrier layer, the second barrier layer, and the third barrier layer that have not been etched; S06, forming an oxide layer on the inner surface of the groove; S07, forming a filling layer in the oxide layer; S08, forming a first ohmic contact layer on the P-type base region, the N-type implantation region and the trench; S09, forming a Schottky contact layer on the N-drift layer and the first ohmic contact layer; forming an anode metal layer on the Schottky contact layer; S10, forming a second ohmic contact layer on the lower surface of the N+ silicon carbide substrate; forming a cathode metal layer on the lower surface of the second ohmic contact layer; The etching depth of the trench in step S04 is greater than the thickness of the P-type base region; the doping concentration of the first P-type barrier region is 1e 18 cm -3 and above, and the thickness is less than the depth of the trench or the depth of the N-type implantation region; The thickness of the P-type base region is less than the depth of the trench; The doping concentration of the N-type implantation region is 1e 19 cm -3 In the above, the bottom of the N-type implantation region is higher than the bottom of the trench.

2. The method for preparing a self-aligned trench type silicon carbide hybrid diode structure according to claim 1, characterized in that: In the step S04, a trench is formed between the N-drift layer, the P-type base region and the N-type implantation region.

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