A processor debugging method and device, computer equipment and processor

Abstract

The application provides a processor debugging method and device, computer equipment and a processor. The method comprises the following steps: setting a digital stack monitoring module of a target stack of a processor; monitoring a monitoring address in the target stack based on the digital stack monitoring module; and determining that an overflow exception occurs in the target stack if data of the monitoring address changes. The method provided by the application can accurately locate a stack overflow problem and improve the efficiency of processor debugging.

Description

Technical Field

[0001] This application relates to the field of microprocessor technology, and in particular to a processor debugging method, apparatus, computer equipment, and processor. Background Technology

[0002] With the increasing scale of integrated circuits and the improvement of process technology, the testability of integrated circuits has become an important indicator of product reliability and yield. In the product development process of microprocessors, program debugging has become extremely complex due to changes in hardware platforms and operating environments. Software debugging and successful operation have become crucial for the research, development, and deployment of application products.

[0003] A powerful and user-friendly debug interface is essential for shortening time-to-market and ensuring product quality, with processor debugging technology being one of its key parameters. The Joint Test Action Group (JTAG) debug technology is currently one of the main and effective debugging methods for RISC-V CPUs. ARM / RISC-V CPU designs integrate the JTAG protocol, enabling system-level and chip-level debugging, diagnostics, and testing.

[0004] A stack is a linear list that allows insertion and deletion operations only at one end. The end where insertion and deletion operations are performed is called the top of the stack, and the other end is called the bottom. An empty stack without any elements is called an empty stack. Because stacks only allow operations at one end, they operate according to the Last-In-First-Out (LIFO) rule. Based on the definition and structure of a stack, the position of the top of the stack is variable. When the stack is empty, the top and bottom coincide; when the stack is full, the top is furthest from the bottom. ARM provides hardware support for stacks, using a dedicated register, the stack pointer (SP), to point to the top of the stack. Different modes have their own independent stack pointer and their own independent stack space.

[0005] Existing RISC-V core MCU debugging modes can include: a debugger writing a specific program into the MCU's RAM; the MCU continuously switching between debug and operating modes to complete the download of the debugged program; in debug mode, the debugger writes the parameters of the executed function into RAM, changes the value in the DPC register to the starting address of the executed function, and sets the DMControl register to put the MCU into operating mode; in operating mode, the corresponding function of the specific program is executed according to the value in the DPC register, and the execution result is written into RAM; the executed function ends with an ebreak instruction, and when ebreak is executed, the MCU enters debug mode from operating mode. The specific program can include erase functions, programming functions, and verification functions. However, existing debugging methods struggle to avoid scenarios where CPU debugging quickly locates stack overflows and have poor versatility. Summary of the Invention

[0006] To address the problem of difficulty in detecting stack overflows during existing processor debugging processes, this application provides a processor debugging method, apparatus, computer equipment, and processor that can accurately locate stack overflow problems and improve processor debugging efficiency.

[0007] On the one hand, a processor debugging method is provided, the method comprising:

[0008] Configure the digital stack monitoring module for the processor target stack;

[0009] The monitoring module monitors the addresses in the target stack based on the digital stack monitoring module.

[0010] If the data at the monitored address changes, it is determined that an overflow exception has occurred in the target stack.

[0011] In some embodiments, the digital stack monitoring module for setting the processor target stack includes:

[0012] The digital stack monitoring module is set up based on the CPU debugging unit of the JTAG / SWD protocol.

[0013] In some embodiments, before monitoring the monitoring addresses in the target stack based on the digital stack monitoring module, the method further includes:

[0014] The register that sets the first address of the real-time operating system task stack based on the digital monitoring module; the first address includes the sum of the stack top address and a first constant;

[0015] Fill the address space of each task stack with first fixed data or default data, and fill the space between the first address and the stack top address with second fixed data or default data.

[0016] In some embodiments, before monitoring the monitoring addresses in the target stack based on the digital stack monitoring module, the method further includes:

[0017] When each function returns during the compilation of the RTOS program, a monitoring flag is set in the register of the digital stack monitoring module;

[0018] The address where the monitoring tag is set will be used as the monitoring address.

[0019] In some embodiments, after determining that an overflow exception has occurred in the target stack, the method further includes:

[0020] The digital stack monitoring module is interrupted, and the CPU automatically saves its state.

[0021] The stack pointer points to the task to be executed, and the CPU pops the stack and restores the context using a stack frame.

[0022] Continue running the application.

[0023] In some embodiments, after determining that an overflow exception has occurred in the target stack, the method further includes:

[0024] Issue an overflow exception warning; the warning may include a display screen notification or a serial port log notification.

[0025] On the other hand, a processor debugging apparatus is provided, the apparatus comprising:

[0026] A digital stack monitoring module building unit, used to set up a digital stack monitoring module for the processor target stack;

[0027] The monitoring unit is used to monitor the monitoring addresses in the target stack based on the digital stack monitoring module;

[0028] An overflow exception determination unit is used to determine that an overflow exception has occurred in the target stack if the data at the monitored address changes.

[0029] In some embodiments, the digital stack monitoring module building unit is specifically used for:

[0030] The digital stack monitoring module is set up based on the CPU debugging unit of the JTAG / SWD protocol.

[0031] In some embodiments, the apparatus further includes a first monitoring address determination unit, configured to:

[0032] The register that sets the first address of the real-time operating system task stack based on the digital monitoring module; the first address includes the sum of the stack top address and a first constant;

[0033] Fill the address space of each task stack with first fixed data or default data, and fill the space between the first address and the stack top address with second fixed data or default data.

[0034] In some embodiments, the apparatus further includes a second monitoring address determination unit, configured to:

[0035] When each function returns during the compilation of the RTOS program, a monitoring flag is set in the register of the digital stack monitoring module;

[0036] The address where the monitoring tag is set will be used as the monitoring address.

[0037] In some embodiments, the device further includes an automatic recovery unit for:

[0038] The digital stack monitoring module is interrupted, and the CPU automatically saves its state.

[0039] The stack pointer points to the task to be executed, and the CPU pops the stack and restores the context using a stack frame.

[0040] Continue running the application.

[0041] In some embodiments, the device further includes a prompting unit for:

[0042] Issue an overflow exception warning; the warning may include a display screen notification or a serial port log notification.

[0043] On the other hand, a computer device is provided, which includes a processor and a memory. The memory stores at least one instruction, at least one program, code set, or instruction set. The processor can load and execute at least one instruction, at least one program, code set, or instruction set to implement the processor debugging method provided in the above-mentioned embodiments.

[0044] On the other hand, a processor is provided, including the computer device described above.

[0045] On the other hand, a computer-readable storage medium is provided, which stores at least one instruction, at least one program, code set, or instruction set. A processor can load and execute at least one instruction, at least one program, code set, or instruction set to implement the processor debugging method provided in the embodiments of this application.

[0046] On the other hand, a computer program product or computer program is provided, which includes computer program instructions stored in a computer-readable storage medium. A processor reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform any of the processor debugging methods described in the above embodiments.

[0047] The beneficial effects of the technical solution provided in this application include at least the following: Embodiments of the present invention provide a processor debugging method, apparatus, computer device, and processor. The method includes setting a digital stack monitoring module for a target processor stack; monitoring monitoring addresses in the target stack based on the digital stack monitoring module; and determining that an overflow exception has occurred in the target stack if the data at the monitoring address changes. The method provided by embodiments of the present invention can accurately locate stack overflow problems and improve processor debugging efficiency. Attached Figure Description

[0048] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0049] Figure 1 This illustration shows a schematic diagram of the stack memory layout of a processor debugging method provided in an exemplary embodiment of this application;

[0050] Figure 2 This illustration shows a schematic diagram of function call relationships for a processor debugging method provided in an exemplary embodiment of this application;

[0051] Figure 3 This illustration shows a schematic diagram of the implementation flow of a processor debugging method provided in an exemplary embodiment of this application;

[0052] Figure 4 This illustration shows a schematic diagram of the stack monitoring address memory layout in a processor debugging method provided by an exemplary embodiment of this application;

[0053] Figure 5 This illustration shows a schematic diagram of a processor debugging method according to an exemplary embodiment of this application, after inserting a monitor marker into the function call stack;

[0054] Figure 6 This illustration shows another implementation flow diagram of a processor debugging method provided in an exemplary embodiment of this application;

[0055] Figure 7 This application shows a structural diagram of a processor debugging apparatus provided in an exemplary embodiment;

[0056] Figure 8 This illustration shows a schematic diagram of the structure of a computer device corresponding to a processor debugging method provided in an exemplary embodiment of this application. Detailed Implementation

[0057] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0058] The processor debugging method provided in this application can accurately locate stack overflow problems and improve processor debugging efficiency.

[0059] Example 1

[0060] An embedded operating system task consists of three parts: the Task Control Block (TCB) contains the relevant parameters and information for each task; a stack is created when a task is created to store the CPU registers, and the CPU registers are saved when switching tasks; and the task function is the task code written by the user.

[0061] Figure 1 A schematic diagram of the stack memory layout of a processor debugging method provided by an embodiment of the present invention is shown.

[0062] See Figure 1 Following the stack's growth direction from high to low, the embedded operating system (RTOS) creates three or more tasks, storing them sequentially from high to low memory addresses. Within each task's stack, function calls occupy the stack, and items such as local variables and passed parameters are placed on the stack.

[0063] Figure 2 This diagram illustrates the function call relationships of a processor debugging method provided by an embodiment of the present invention.

[0064] See Figure 2 In a specific example, the function call relationship is function_i calls function_m, and function_m calls function_n. If the function call hierarchy in a task is too deep, or if a function requires a large stack, the stack will grow beyond the stack allocated to the task and be written to the stack of other tasks. Figure 2 If function_n in Task2 continues to recursively call other functions layer by layer, the stack will grow beyond the stack frame of Task2 and enter Task3, corrupting the stack frame of Task3 and causing Task3 to run abnormally.

[0065] Figure 3 The diagram illustrates the implementation flow of the processor debugging method provided in this embodiment of the invention.

[0066] See Figure 3 The processor debugging method provided in this embodiment of the invention may include steps 101 to 103.

[0067] Step 101: Configure the digital stack monitoring module for the processor target stack.

[0068] In some embodiments, step 101 includes:

[0069] The digital stack monitoring module is set up based on the CPU debugging unit of the JTAG / SWD protocol.

[0070] Specifically, a digital stack monitoring (STACK_MONITOR) digital circuit (IP) module is designed based on the CPU debugging unit based on the JTAG / SWD protocol to monitor the stack.

[0071] Step 102: Monitor the monitoring addresses in the target stack based on the digital stack monitoring module.

[0072] In some embodiments, prior to step 102, the method further includes:

[0073] The register that sets the first address of the real-time operating system task stack based on the digital monitoring module; the first address includes the sum of the stack top address and a first constant;

[0074] Fill the address space of each task stack with first fixed data or default data, and fill the space between the first address and the stack top address with second fixed data or default data.

[0075] Figure 4 This diagram illustrates the memory layout of the stack monitoring address in the processor debugging method provided by an embodiment of the present invention.

[0076] See Figure 4 The STACK_MONITOR module is designed to store several registers near the top of the task stack of the real-time operating system (RTOS). The address near the top of the stack can include addr1, addr2, addr3, ..., where addr1 = stack top address + 8, addr2 = stack top address + 8, and addr3 = stack top address + 8.

[0077] Before creating a task, the stack address space of each task is filled with fixed data such as 0x5A5A5A5A or the system default value. Each task's task control block is initialized. The task control block contains CPU context information, and the space between each task's address addr1 (addr2, addr3) and the top of the stack is filled with fixed data such as DEAD or the system default value.

[0078] The minimum address of each task stack that can trigger the STACK_MONITOR module, i.e. the data at the top of the stack, is monitored. If the CPU or DMA module writes to memory address addr1(addr2, addr3, ...), or the data in address addr1(addr2, addr3, ...) changes, the STACK_MONITOR module will generate an abnormal interrupt, indicating a stack overflow exception.

[0079] In some embodiments, prior to step 102, the method further includes:

[0080] When each function returns during the compilation of the RTOS program, a monitoring flag is set in the register of the digital stack monitoring module;

[0081] The address where the monitoring tag is set will be used as the monitoring address.

[0082] Figure 5 This diagram illustrates the process of inserting a monitor marker into the function call stack in the processor debugging method provided by an embodiment of the present invention.

[0083] See Figure 5 During the compilation of RTOS-based programs, the compiler adds monitor flags when each function returns. At system runtime, the addresses of these monitor flags are set in the registers of the STACK_MONITOR digital circuit module. If a monitored address is accessed or the data within that monitored address is modified, it indicates that the call stack has been corrupted. The STACK_MONITOR module then generates an exception interrupt, indicating a function call stack overflow exception.

[0084] Step 103: If the data at the monitored address changes, it is determined that an overflow exception has occurred in the target stack.

[0085] In some embodiments, after step 103, the method further includes:

[0086] The digital stack monitoring module is interrupted, and the CPU automatically saves its state.

[0087] The stack pointer points to the task to be executed, and the CPU pops the stack and restores the context using a stack frame.

[0088] Continue running the application.

[0089] Specifically, when the stack is about to overflow, a STACK_MONITOR interrupt occurs, and the CPU automatically saves the context. This automatic context saving involves the CPU determining which Service Provider (SP) is currently in use. If the MSP / PSP is used directly, the hardware automatically saves half of the context registers to the stack, such as R0-R3, R12, LR, PC, and XPSR.

[0090] The CPU calculates EXC_RETURN based on the MSP used in the current mode and assigns EXC_RETURN the value LR. The software saves r4~r11 and psp to the callee_saved of the current task. The STACK_MONITOR interrupt service routine is executed; the task to be executed is popped from callee_saved into r4~r11 and psp, and the stack pointer points to the task to be executed.

[0091] The CPU automatically pops data from the stack and restores the current context using the stack frame. Specifically, the CPU determines the applicable MSP based on the value of LR, and then pops R0-R3, R12, LR, PC, and XPSR from the stack.

[0092] In some embodiments, after step 103, the method further includes:

[0093] Issue an overflow exception warning; the warning may include a display screen notification or a serial port log notification.

[0094] Furthermore, after a stack overflow exception occurs, the STACK_MONITOR module's hardware interrupt system executes a recovery procedure, handling the issue according to the user's specific strategy within the interrupt service routine. This can be indicated via display, sound, or serial port logs, eliminating the need for backtracking and analyzing the call stack. This simplifies the stack overflow analysis process for developers and maintainers, improving efficiency.

[0095] In embedded systems, the stack size of each task is specified during static or dynamic creation and cannot be modified during runtime. The task's execution context is stored in its stack. If a task's independent stack is corrupted, its execution context is also corrupted, leading to unpredictable exceptions. The method provided in this invention offers monitoring and prevention mechanisms for potential task stack corruption through CPU hardware debugging. This hardware mechanism simplifies debugging methods for CPU task stack exceptions, thereby improving debugging efficiency.

[0096] Existing technologies actively monitor data by polling with CPU software. If a task that checks the fill value in the buffer at predetermined intervals experiences a stack overflow, it cannot detect stack overflows in other tasks, leading to a system crash. This application, however, uses a STACK_MONITOR digital circuit module to monitor address or data changes via interrupts. The task stack buffer does not need to be filled with fixed data, and there is no need to check for changes in the buffer's fill value at predetermined intervals. This passive monitoring method prevents system crashes and provides alerts via display, sound, or serial port logs. It eliminates the need for backtracking and analyzing the call stack, simplifying the stack overflow analysis process for developers and maintainers and improving efficiency. Even if a task experiences a stack overflow, the overflowing task can be terminated according to a pre-stored strategy, while other tasks continue to run normally.

[0097] Example 2

[0098] Figure 6 This diagram illustrates another implementation flow of the processor debugging method provided in this embodiment of the invention.

[0099] See Figure 6 In a specific example, the processor debugging method provided in this embodiment of the invention is implemented as follows.

[0100] When a function is executing and the stack is about to overflow, a STACK_MONITOR interrupt occurs, and the CPU automatically saves the context. This automatic context saving involves the CPU determining which Service Provider (SP) is currently in use. If the MSP / PSP is used, the hardware automatically saves half of the context registers to the stack, such as R0-R3, R12, LR, PC, and XPSR.

[0101] The CPU calculates EXC_RETURN based on the MSP used in the current mode and assigns the value LR to EXC_RETURN.

[0102] The software saves r4~r11 and psp to the current task's callee_saved. It executes the STACK_MONITOR interrupt service routine; the task to be executed is popped from callee_saved into r4~r11 and psp, and the stack pointer points to the task to be executed.

[0103] The CPU automatically pops data from the stack and restores the current context using the stack frame. Specifically, the CPU determines the applicable MSP based on the value of LR, and then pops R0-R3, R12, LR, PC, and XPSR from the stack.

[0104] Continue running the application until it terminates.

[0105] This invention provides a general and efficient CPU design and debugging method for preventing stack overflows. Firstly, it involves a digital stack monitoring module (STACK_MONITOR, IP) for monitoring stack overflows, based on a CPU debugging unit using the JTAG / SWD protocol. The STACK_MONITOR module sets up several registers to configure the starting address of the real-time operating system task stack. Then, it fills the stack address of each task with fixed data such as 0x5A5A5A5A or uses default system data. Each task structure is initialized, containing the task control block and CPU context information, which triggers the STACK_MONITOR module to monitor the address data of each task's stack with the minimum address plus 8, i.e., monitoring the data near the top of the stack.

[0106] If the CPU or DMA accesses a monitored address or the data in that monitored address changes, the STACK_MONITOR module generates an exception interrupt, indicating a stack overflow exception. During system runtime, the addresses of each monitor are set in the STACK_MONITOR's digital circuit module register. If the monitored address is accessed or the data in that monitored address is modified, it indicates that the call stack has been corrupted, and the STACK_MONITOR module generates an exception interrupt, indicating a function call stack overwrite exception.

[0107] In summary, the processor debugging method provided by the embodiments of the present invention can accurately locate stack overflow problems and improve processor debugging efficiency.

[0108] Example 3

[0109] Figure 7 A schematic diagram of the processor debugging device provided in an embodiment of the present invention is shown.

[0110] See Figure 7 The processor debugging apparatus provided in this embodiment of the invention may include:

[0111] On the other hand, a processor debugging apparatus is provided, the apparatus comprising:

[0112] A digital stack monitoring module building unit, used to set up a digital stack monitoring module for the processor target stack;

[0113] The monitoring unit is used to monitor the monitoring addresses in the target stack based on the digital stack monitoring module;

[0114] An overflow exception determination unit is used to determine that an overflow exception has occurred in the target stack if the data at the monitored address changes.

[0115] In some embodiments, the digital stack monitoring module building unit is specifically used for:

[0116] The digital stack monitoring module is set up based on the CPU debugging unit of the JTAG / SWD protocol.

[0117] In some embodiments, the apparatus further includes a first monitoring address determination unit, configured to:

[0118] The register that sets the first address of the real-time operating system task stack based on the digital monitoring module; the first address includes the sum of the stack top address and a first constant;

[0119] Fill the address space of each task stack with first fixed data or default data, and fill the space between the first address and the stack top address with second fixed data or default data.

[0120] In some embodiments, the apparatus further includes a second monitoring address determination unit, configured to:

[0121] When each function returns during the compilation of the RTOS program, a monitoring flag is set in the register of the digital stack monitoring module;

[0122] The address where the monitoring tag is set will be used as the monitoring address.

[0123] In some embodiments, the device further includes an automatic recovery unit for:

[0124] The digital stack monitoring module is interrupted, and the CPU automatically saves its state.

[0125] The stack pointer points to the task to be executed, and the CPU pops the stack and restores the context using a stack frame.

[0126] Continue running the application.

[0127] In some embodiments, the device further includes a prompting unit for:

[0128] Issue an overflow exception warning; the warning may include a display screen notification or a serial port log notification.

[0129] In summary, the device provided by the embodiments of the present invention can accurately locate stack overflow problems and improve processor debugging efficiency.

[0130] Example 4

[0131] Figure 8 This application shows a schematic diagram of the structure of a computer device provided in an exemplary embodiment, the computer device comprising:

[0132] The processor 301 includes one or more processing cores. The processor 301 executes various functional applications and data processing by running software programs and modules.

[0133] The receiver 302 and transmitter 303 can be implemented as a communication component, which can be a communication chip. Optionally, this communication component can include signal transmission functionality. That is, the transmitter 303 can be used to transmit control signals to the image acquisition device and the scanning device, and the receiver 302 can be used to receive corresponding feedback commands.

[0134] The memory 304 is connected to the processor 301 via the bus 305.

[0135] The memory 304 can be used to store at least one instruction, and the processor 301 is used to execute the at least one instruction to implement steps 101 to 102 in the above-described processor debugging method embodiment.

[0136] Those skilled in the art will understand that Figure 8 This is merely an example of a computer device and does not constitute a limitation on the computer device. It may include more or fewer components than shown, or combine certain components, or different components. For example, the computer device may also include network access devices, etc.

[0137] The processor 301 may be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor.

[0138] The memory 304 can be an internal storage unit of the computer device, such as a hard drive or RAM. The memory 304 can also be an external storage device of the computer device, such as a plug-in hard drive, Smart Media Card (SMC), Secure Digital (SD) card, or Flash Card. Furthermore, the memory 304 can include both internal and external storage units. The memory 304 is used to store the computer program and other programs and data required by the terminal device. The memory 304 can also be used to temporarily store data that has been output or will be output.

[0139] Example 5

[0140] This application also provides a processor, including the computer device described above.

[0141] Example 6

[0142] This application also provides a computer-readable storage medium storing at least one instruction, at least one program, code set, or instruction set, which can be loaded and executed by a processor to implement the processor debugging method described above.

[0143] Optionally, the computer-readable storage medium may include: read-only memory (ROM), random access memory (RAM), solid-state drives (SSDs), or optical discs, etc. The random access memory may include resistive random access memory (ReRAM) and dynamic random access memory (DRAM).

[0144] Example 7

[0145] This application also provides a computer program product or computer program that includes computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform any of the processor debugging methods described in the above embodiments.

[0146] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the implementation.

[0147] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware, or by a program instructing related hardware. The program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is used as an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0148] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0149] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0150] The computer program includes computer program code, which can be in the form of source code, object code, executable file, or some intermediate form. The computer-readable medium can include any entity or device capable of carrying the computer program code, recording media, USB flash drive, portable hard drive, magnetic disk, optical disk, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc. It should be noted that the content included in the computer-readable medium can be appropriately added or removed according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media do not include electrical carrier signals and telecommunication signals.

[0151] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A processor debugging method, characterized in that, The method includes: Configure the digital stack monitoring module for the processor target stack; The monitoring module monitors the addresses in the target stack based on the digital stack monitoring module. If the data at the monitored address changes, it is determined that an overflow exception has occurred in the target stack; Before monitoring the monitoring addresses in the target stack based on the digital stack monitoring module, the method further includes: The register that sets the first address of the real-time operating system task stack is based on the digital stack monitoring module; the first address includes the sum of the stack top address and a first constant; Fill the address space of each task stack with first fixed data or default data, and fill the space between the first address and the stack top address with second fixed data or default data. Before monitoring the monitoring addresses in the target stack based on the digital stack monitoring module, the method further includes: When each function returns during the compilation of the RTOS program, a monitoring flag is set in the register of the digital stack monitoring module; The address where the monitoring tag is set will be used as the monitoring address.

2. The method according to claim 1, characterized in that, The digital stack monitoring module for setting the processor target stack includes: The digital stack monitoring module is set up based on the CPU debugging unit of the JTAG / SWD protocol.

3. The method according to claim 1, characterized in that, After determining that an overflow exception has occurred in the target stack, the method further includes: The digital stack monitoring module is interrupted, and the CPU automatically saves its state. The stack pointer points to the task to be executed, and the CPU pops the stack and restores the context using a stack frame. Continue running the application.

4. The method according to any one of claims 1 to 3, characterized in that, After determining that an overflow exception has occurred in the target stack, the method further includes: Issue an overflow exception warning; the warning may include a display screen notification or a serial port log notification.

5. A processor debugging device, characterized in that, The device includes: Digital stack monitoring module building unit, used to set up a digital stack monitoring module for the processor target stack; The monitoring unit is used to monitor the monitoring addresses in the target stack based on the digital stack monitoring module; An overflow exception determination unit is used to determine that an overflow exception has occurred in the target stack if the data at the monitored address changes. The device further includes a first monitoring address determination unit, used for: The register that sets the first address of the real-time operating system task stack is based on the digital stack monitoring module; the first address includes the sum of the stack top address and a first constant; Fill the address space of each task stack with first fixed data or default data, and fill the space between the first address and the stack top address with second fixed data or default data. The device further includes a second monitoring address determination unit, used for: When each function returns during the compilation of the RTOS program, a monitoring flag is set in the register of the digital stack monitoring module; The address where the monitoring tag is set will be used as the monitoring address.

6. A computer device, characterized in that, The computer device includes a processor and a memory, the memory storing at least one instruction, at least one program, code set, or instruction set, the at least one instruction, at least one program, code set, or instruction set being loaded and executed by the processor to implement the processor debugging method as described in any one of claims 1 to 4.

7. A processor, characterized in that, Includes the computer device as described in claim 6.

8. A computer-readable storage medium, characterized in that, The readable storage medium stores at least one instruction, at least one program, code set, or instruction set, said at least one instruction, at least one program, code set, or instruction set being loaded and executed by a processor to implement the processor debugging method as described in any one of claims 1 to 4.

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