A surge suppressor chip and high-side intelligent driver

Abstract

The application relates to the field of surge suppression, in particular to a surge suppressor chip and a high-side intelligent driver. The chip comprises a surge suppression unit and a gate voltage limiting unit; the surge suppression unit is used for detecting the voltage at the VBB end and judging whether the voltage exceeds a preset value, so as to judge whether a surge voltage occurs, and when the surge voltage occurs, the gate voltage limiting unit is controlled to work; the input end of the surge suppression unit is connected with the OUT end, and the output end is connected with the input end of the logic control unit and the gate voltage limiting unit respectively; the output end of the gate voltage limiting unit is connected with the GATE end, and is used for keeping the voltage at the GATE end within a set range. In the application, when the surge suppression unit detects the surge voltage, the output signal makes the gate voltage limiting unit work, and the voltage at the GATE end is kept at the preset value through the gate voltage limiting unit.

Description

Technical Field

[0001] This invention relates to a surge suppression device, specifically to a surge suppressor chip and a high-side intelligent driver. Background Technology

[0002] When an electronic system is turned on or off, or when it is subjected to external interference (such as lightning strikes or power supply disruptions), transient voltages or currents exceeding the normal operating range of the electronic system may occur. Therefore, surge suppression chips are typically installed in electronic systems to prevent irreversible damage to electronic components caused by such situations and to protect the electronic system from operating within its normal current and voltage range.

[0003] Surge suppression circuit reference for traditional surge suppressor chips Figure 1 This includes MOSFETs M1 and M2, comparator A0, resistors R1 and R2, and a charge pump. The resistor divider network consisting of resistors R1 and R2 is used to detect the voltage V at the OUT terminal. OUT Size. When the electronic system is operating normally, V OUT When the voltage is less than the preset value, comparator A0 outputs a low level, MOSFET M2 is turned off, and the gate voltage of MOSFET M1 is raised by the charge pump, making the OUT terminal voltage equal to the VIN terminal voltage. When the electronic system experiences a surge voltage that causes the VIN terminal voltage to be too high, the OUT terminal voltage will also be higher than the preset value. Comparator AO outputs a high level, MOSFET M2 is turned on, and the gate voltage of MOSFET M1 is pulled to the OUT terminal voltage. When MOSFET M1 is turned off, the OUT terminal voltage is clamped to the level shown in the formula VOUT=(1+R1 / R2)*Vref, where Vref is the reference voltage and VOUT is the OUT terminal voltage.

[0004] The above analysis shows that existing surge suppression chips need to meet the following conditions to operate normally: VOUT = VIN, where VIN is the voltage at the VIN terminal. Since VOUT and VIN fluctuate greatly across the entire range, when detecting the voltage difference between VOUT and VIN, the gate oxide withstand voltage requirement of the internal devices of the surge suppression chip is too high (0~VIN, up to several hundred volts). No process can meet the design requirements. Therefore, how to detect the normal operating conditions of the surge suppression chip has become a design challenge for surge suppression chips. Summary of the Invention

[0005] The purpose of this invention is to solve the technical problem that existing surge suppressor chips have large fluctuations in VOUT and VIN across the entire range, which requires excessively high gate oxide withstand voltage when detecting the voltage difference between VOUT and VIN, potentially damaging power MOSFETs and loads, and making it difficult to detect the normal operating conditions of surge suppressor chips. The invention provides a surge suppressor chip and a high-side intelligent driver.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows: A surge suppressor chip includes a logic control unit, a charge pump connected to the logic control unit, and an input / output interface; the input / output interface includes an IN terminal for input, an OUT terminal for output, a GATE terminal for power transistor control, and a VBB terminal and GND terminal for power supply. Its special feature is: Includes surge suppression unit and gate voltage limiting unit; The surge suppression unit is used to detect the VBB terminal voltage and determine whether the voltage exceeds a preset value, thereby determining whether a surge voltage has occurred. When a surge voltage occurs, it controls the gate voltage limiting unit to operate. The input terminal of the surge suppression unit is connected to the OUT terminal, and the output terminal is connected to the input terminals of the logic control unit and the gate voltage limiting unit, respectively. The output of the gate voltage limiting unit is connected to the GATE terminal to keep the voltage at the GATE terminal within a set range.

[0007] Furthermore, the surge suppression unit includes a high-side reference generation module, a high-side ground generation module, a surge judgment and comparison module, a slope detection module, as well as a power MOSFET, resistor R5, resistor R6 and capacitor C4. Resistors R5 and R6 are connected in series between the OUT terminal and GND, and the connection point of resistors R5 and R6 serves as the FB terminal for output feedback. The high-side reference generation module is used to generate a reference voltage. Its input is connected to an external voltage Vref1, and its output is connected to the first input of the surge judgment and comparison module. The high-side ground generation module is used to generate high-side ground voltage. Its input terminal is connected to the OUT terminal, and its output terminal is connected to the third input terminal of the surge judgment and comparison module. The surge detection and comparison module is used to determine whether the voltage at the VBB terminal exceeds the preset value. Its second input terminal is connected to the FB terminal, its output terminal is connected to the input terminal of the gate voltage limiting unit and the logic control unit respectively, and its fourth input terminal is connected to the OUT terminal. The slope detection module is used to detect the rising slope of the voltage at the VBB terminal. When the rising slope is higher than the preset slope, the gate voltage of the power MOSFET is pulled down to turn it off. The first input terminal of the slope detection module and the drain of the power MOSFET are both connected to the VBB terminal, the second input terminal of the slope detection module is connected to the OUT terminal, and the output terminal of the slope detection module and the gate of the power MOSFET are both connected to the GATE terminal. The source of the power MOSFET is connected to the OUT terminal, and the gate is connected to the GATE terminal; one end of capacitor C4 is connected to the OUT terminal, and the other end is connected to GND.

[0008] Furthermore, it also includes a reference current I1; the gate voltage limiting unit includes MOSFETs M2, M3, M4, M5, and M6, and NOT gate U3; The source of MOSFET M2 is connected to a charge pump, and its gate is connected to the input of NOT gate U3. The source of MOSFET M3 is connected to the reference current I1, the gate is connected to the output terminal of NOT gate U3, and the drain is connected to the drain of MOSFET M2 and the drain of MOSFET M4; the drains of MOSFET M3, MOSFET M2 and MOSFET M4 are all connected to the gate of the power MOSFET. The source of MOSFET M4 is connected to the source of MOSFET M5, and the gate is connected to the gate of MOSFET M5 and the drain of MOSFET M6. The drain of MOSFET M2 serves as the output of the gate voltage limiting unit and is connected to the gate of the power MOSFET; the gate of MOSFET M6 and the input of NOT gate U3 serve as the input of the gate voltage limiting unit and are connected to the output of the surge judgment and comparison module.

[0009] Furthermore, the high-side reference generation module includes a first comparator U1, a MOS transistor N1, a resistor R1, and a resistor R2; The non-inverting input of the first comparator U1 serves as the input of the high-side reference generation module, connected to the external reference voltage Vref1. The inverting input is connected to the source of MOSFET N1, and the output is connected to the gate of MOSFET N1. The source of MOSFET N1 is connected to GND through resistor R1, and the drain is connected to the OUT terminal through resistor R2, which is also connected to the first input terminal of the surge detection and comparison module.

[0010] Furthermore, the high-side reference generation module also includes a filtering circuit; The filter circuit includes resistor R3 and capacitor C1; One end of resistor R3 is connected to the drain of MOSFET N1, and the other end is connected to the first input terminal of the surge detection and comparison module. The two ends of capacitor C1 are connected to the other end of resistor R3 and the OUT terminal, respectively.

[0011] Furthermore, the high-side ground generation module includes Zener diode D1, Zener diode D2, capacitor C2, MOSFET P1, MOSFET N2, MOSFET N3 and MOSFET N4; The positive terminal of Zener diode D1 is connected to the drain of MOSFET N2, the positive terminal of Zener diode D2 is connected to the drain of MOSFET P1, and the negative terminals of both Zener diode D1 and Zener diode D2 are connected to the OUT terminal. The gates of MOSFET N2, MOSFET N3, and MOSFET N4 are connected together and then connected to GND; the source of MOSFET N2 is connected to the drain of MOSFET N3, the source of MOSFET N3 is connected to the drain of MOSFET N4, the source of MOSFET N4 is connected to GND, the gate of MOSFET P1 is connected to the drain of MOSFET N2, and the source of MOSFET P1 is connected to GND. The two ends of capacitor C2 are connected to the OUT terminal and the drain of MOSFET P1, respectively; The drain of MOSFET P1 is connected to the third input terminal of the surge detection and comparison module.

[0012] Furthermore, the slope detection module includes MOSFET N5, MOSFET N6, resistor R4, and capacitor C3; The sources of MOSFETs N5 and N6 and one end of resistor R4 serve as the second input terminals of the slope detection module, connected to the OUT terminal. The gate and drain of MOSFET N5 are shorted and then connected to the gate of MOSFET N6. The drain of MOSFET N5 is connected to the other end of resistor R4. One end of capacitor C3 serves as the first input terminal of the slope detection module, connected to the VBB terminal, and the other end is connected to the drain of MOSFET N5. The drain of MOSFET N6 serves as the output terminal of the slope detection module and is connected to the GATE terminal.

[0013] Furthermore, the surge judgment and comparison module includes a second comparator U2; The non-inverting input of the second comparator U2 is connected to the output of the high-side reference generation module, the inverting input is connected to the FB terminal, and the output is connected to the input of the gate voltage limiting unit and the logic control unit, respectively. The third and fourth inputs of the surge judgment comparison module are the low power supply side and the high power supply side of the second comparator U2, respectively. The low power supply side of the second comparator U2 is connected to the output of the high-side ground generation module, and the high power supply side is connected to the OUT terminal.

[0014] Meanwhile, the present invention also provides a high-side intelligent driver, which is special in that it includes the aforementioned surge suppressor chip.

[0015] Compared with the prior art, the beneficial effects of the present invention are: 1. In the solution of the present invention, the surge judgment comparison module in the surge suppression unit detects the VBB voltage in real time. When the VBB terminal voltage exceeds the preset value, it is determined that a surge voltage or surge current has been generated. The slope detection module detects the rise slope of the VBB voltage. When the rise slope is higher than the preset slope, the gate voltage of the power MOSFET is pulled down to turn it off, preventing the power MOSFET and load device from being burned out due to transient large current or high voltage. The surge judgment comparison module outputs a signal to make the gate voltage limiting unit work. The gate voltage limiting unit keeps the GATE terminal voltage within the set range to protect the power MOSFET and load device.

[0016] 2. In the prior art, the chip ground and the load ground may often be different. If the voltage across the pull-down resistor is directly detected, the output voltage may exceed the preset range due to the difference in reference ground. Since the chip and the load share the same OUT terminal, the solution of this invention detects the voltage of the OUT terminal by detecting the voltage across the R5 resistor. Therefore, detecting the pull-up resistor voltage (i.e., Vout-VFB) can avoid the output voltage exceeding the preset range due to the difference in reference ground, which could damage the power MOSFET and the load. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the structure of an existing surge suppressor chip; Figure 2 A schematic diagram of the structure of a surge suppressor chip embodiment of the present invention; Figure 3 This is a schematic diagram of the surge suppression unit in an embodiment of the surge suppressor chip of the present invention; Figure 4 This is a schematic diagram of the gate voltage limiting unit in an embodiment of a surge suppressor chip according to the present invention; Figure 5 This is an output waveform diagram of an embodiment of a surge suppressor chip according to the present invention. Detailed Implementation

[0018] To make the objectives, advantages, and features of the present invention clearer, a surge suppressor chip and a high-side intelligent driver proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following detailed description.

[0019] refer to Figure 2A surge suppressor chip typically includes a current source, a voltage source, an electrostatic discharge (ESD) protection unit, a charge pump and potential shift rectifier, a logic control unit, an over-temperature protection unit, a current limiting unit, a gate voltage protection unit, and an inductor demagnetizing clamping unit, as well as input / output interfaces. These interfaces include a VBB terminal for power supply, an OUT terminal for output, a GATE terminal for power transistor control, an IN terminal for input, and GND. The two ends of the current source are connected to the VBB terminal and the IN terminal, respectively. The two ends of the voltage source are connected to the VBB terminal and the first port of the logic control unit, respectively. The first port of the ESD protection unit is connected to the IN terminal, the second port is connected to GND, the third port is connected to the second port of the logic control unit, the third port of the logic control unit is connected to the over-temperature protection unit, the fourth port is connected to the first port of the charge pump and potential shift rectifier, the second port of the charge pump and potential shift rectifier is connected to the VBB terminal, and the third port is connected to one end of the current limiting unit, the gate voltage protection unit, and the inductor demagnetizing clamping unit. The other ends of the current limiting unit and the gate voltage protection unit are connected to the OUT terminal.

[0020] The surge suppressor chip provided in this embodiment is based on the above-mentioned chip structure, and further includes a surge suppression unit and a gate voltage limiting unit.

[0021] The surge suppression unit is mainly used to detect the VBB terminal voltage and determine whether the voltage exceeds the preset value, thereby determining whether a surge voltage or current has occurred. When a surge voltage or current occurs, it controls the gate voltage limiting unit to work. The input terminal of the surge suppression unit is connected to the OUT terminal, and the output terminal is connected to the logic control unit and the gate voltage limiting unit respectively.

[0022] For details, please refer to Figure 3 The surge suppression unit includes a high-side reference generation module, a high-side ground generation module, a surge judgment and comparison module, a slope detection module, as well as a power MOSFET, resistor R5, resistor R6 and capacitor C4.

[0023] In this configuration, resistors R5 and R6 are connected in series between the OUT terminal and GND, and the connection point between resistors R5 and R6 serves as the FB terminal for output feedback. The source of the power MOSFET is connected to the OUT terminal, and the gate is connected to the GATE terminal; one end of capacitor C4 is connected to the OUT terminal, and the other end is connected to GND.

[0024] The high-side reference generation module generates a reference voltage. Its input is connected to an external voltage Vref1, and its output is connected to the first input of the surge detection comparison module. The high-side reference generation module includes a first comparator U1, a MOSFET N1, resistors R1, R2, and R3, and a capacitor C1. The non-inverting input of the first comparator U1 serves as the input of the high-side reference generation module, connected to the external reference voltage Vref1. Its inverting input is connected to the source of the MOSFET N1, and its output is connected to the gate of the MOSFET N1. The source of the MOSFET N1 is connected to GND through resistor R1, and its drain is connected to the OUT terminal through resistor R2, and is also connected to the first input of the surge detection comparison module. One end of resistor R3 is connected to the drain of the MOSFET N1, and the other end is connected to the first input of the surge detection comparison module. The two ends of capacitor C1 are connected to the other end of resistor R3 and the OUT terminal, respectively. Among them, resistor R3 and capacitor C1 form a filter circuit; the resistance ratio of resistor R1 to resistor R2 is 1:n. When operating stably, the voltage at the non-inverting input terminal of the second comparator U2 is equal to the voltage at the inverting input terminal, and the voltage at the FB terminal is Vout-(Vref1 / R1)*n.

[0025] The high-side ground generation module is mainly used to generate high-side ground voltage. Its input terminal is connected to the OUT terminal, and its output terminal is connected to the third input terminal of the surge judgment and comparison module. Specifically, the high-side ground generation module includes Zener diode D1, Zener diode D2, capacitor C2, MOSFET P1, MOSFET N2, MOSFET N3, and MOSFET N4. The positive terminal of Zener diode D1 is connected to the drain of MOSFET N2, and the positive terminal of Zener diode D2 is connected to the drain of MOSFET P1. The negative terminals of both Zener diodes D1 and D2 are connected to the OUT terminal. The gates of MOSFETs N2, N3, and N4 are connected together and then connected to GND. The source of MOSFET N2 is connected to the drain of MOSFET N3, and the source of MOSFET N3 is connected to the drain of MOSFET N4. The source of MOSFET N4 is connected to GND. The gate of MOSFET P1 is connected to the drain of MOSFET N2, and the source of MOSFET P1 is connected to GND. The two ends of capacitor C2 are connected to the OUT terminal and the drain of MOSFET P1, respectively. The drain of MOSFET P1 is connected to the third input terminal of the surge detection and comparison module. In other embodiments of the present invention, MOSFETs N2, N3, and N4 can be replaced with current sources.

[0026] The slope detection module is mainly used to detect the rising slope of the voltage at the VBB terminal. When the rising slope is higher than the preset slope, it pulls down the gate voltage of the power MOSFET to turn it off. The first input terminal of the slope detection module and the drain of the power MOSFET are both connected to the VBB terminal. The second input terminal of the slope detection module is connected to the OUT terminal. The output terminal of the slope detection module and the gate of the power MOSFET are both connected to the GATE terminal. Specifically, the slope detection module includes MOSFETs N5 and N6, resistor R4, and capacitor C3. The sources of MOSFETs N5 and N6 and one end of resistor R4 serve as the second input terminals of the slope detection module, connected to the OUT terminal. The gate and drain of MOSFET N5 are shorted and then connected to the gate of MOSFET N6. The drain of MOSFET N5 is connected to the other end of resistor R4. One end of capacitor C3 serves as the first input terminal of the slope detection module, connected to the VBB terminal, and the other end is connected to the drain of MOSFET N5. The drain of MOSFET N6 serves as the output terminal of the slope detection module, connected to the GATE terminal.

[0027] The surge detection and comparison module is mainly used to determine whether the VBB terminal voltage exceeds a preset value. Its second input terminal is connected to the FB terminal, its output terminal is connected to the input terminal of the gate voltage limiting unit and the logic control unit, and its fourth input terminal is connected to the OUT terminal. Specifically, in this embodiment, the surge detection and comparison module is implemented using a second comparator U2. The non-inverting input terminal of the second comparator U2 is connected to the output terminal of the high-side reference generation module, the inverting input terminal is connected to the FB terminal, and its output terminal is connected to the input terminal of the gate voltage limiting unit and the logic control unit, respectively. The third and fourth input terminals of the surge detection and comparison module are the low-side and high-side power supply terminals of the second comparator U2, respectively. The low-side power supply terminal of the second comparator U2 is connected to the output terminal of the high-side ground generation module, and the high-side power supply terminal is connected to the OUT terminal. Of course, in other embodiments of the present invention, those skilled in the art can also implement the above functions using other circuits.

[0028] The output of the gate voltage limiting unit is connected to the GATE terminal, primarily used to maintain the GATE terminal voltage within a set range. For details, please refer to [link / reference]. Figure 4(Vref2 in the diagram is the output voltage of the high-side reference generation module). The gate voltage limiting unit includes MOSFETs M2, M3, M4, M5, and M6, and NOT gate U3. The source of MOSFET M2 is connected to the charge pump, and its gate is connected to the input of NOT gate U3. The source of MOSFET M3 is connected to the reference current I1 in the surge suppressor chip, its gate is connected to the output of NOT gate U3, and its drain is connected to the drains of MOSFETs M2 and M4. The drains of MOSFETs M3, M2, and M4 are all connected to the gates of the power MOSFETs. The source of MOSFET M4 is connected to the source of MOSFET M5, and its gate is connected to the gate of MOSFET M5 and the drain of MOSFET M6. The drain of MOSFET M2 serves as the output of the gate voltage limiting unit and is connected to the gate of the power MOSFET. The gate of MOSFET M6 and the input of NOT gate U3 serve as the input of the gate voltage limiting unit and are connected to the output of the surge judgment comparison module.

[0029] The scheme in this application realizes the voltage detection of the OUT terminal through the voltage on resistor R5. The voltage Vout is detected by the voltage divider network of resistors R5 and R6. Under normal operation, comparator U2 outputs a low level, MOSFET M6 is off, MOSFET M2 is on, and MOSFET M3 is off. The gate voltage of the power MOSFET is provided by the charge pump, and Vout=Vbb. When a surge voltage is detected, MOSFET M6 is turned on, MOSFET M2 is off, and MOSFET M3 is on. The gate voltage of the power MOSFET is determined by the current source I1 and MOSFET M6. The gate voltage is limited, and the power MOSFET withstands the surge. When stable, the voltages at the non-inverting input and the inverting input of comparator U2 are equal.

[0030] refer to Figure 5 In the diagram, the horizontal axis represents time, and the vertical axis represents voltage. From top to bottom, VBB, Vin, and V are respectively. GATE V OUT , Gate-source voltage V of power MOSFET GS .

[0031] After VBB is powered on, it supplies power to the chip to enable normal operation. At time T1, the VIN terminal signal is high, and the power MOSFET is normally turned on. At time T2, a surge voltage is generated, and the VBB voltage suddenly rises. The surge detection module detects that VBB is higher than the preset value and determines that a surge voltage or surge current has occurred. It then pulls the voltage at the GATE terminal down to the OUT terminal through the slope detection module, turning off the power MOSFET. At this time, due to the power consumption of the external load, the voltage at the OUT terminal drops. GSWhen the power MOSFET is turned on again, the current source I1 supplies power to the GATE terminal. The system is stabilized through the loop regulation of the OUT terminal, surge suppression unit, gate voltage limiting unit, GATE terminal, and OUT terminal. At this time, the values ​​of the non-inverting input terminal and the inverting input terminal of the surge suppression detection unit are equal, and the output signal makes the gate voltage limiting unit work, thus limiting the gate voltage of the power MOSFET.

[0032] This embodiment provides a high-side intelligent driver, on which the aforementioned surge suppressor chip is disposed.

Claims

1. A surge suppressor chip, comprising a logic control unit, a charge pump connected to the logic control unit, and an input / output interface; the input / output interface includes an IN terminal for input, an OUT terminal for output, a GATE terminal for power transistor control, and a VBB terminal and GND terminal for power supply; Its features are: It also includes a surge suppression unit and a gate voltage limiting unit; The surge suppression unit is used to detect the VBB terminal voltage and determine whether the voltage exceeds a preset value, thereby determining whether a surge voltage has occurred. When a surge voltage occurs, it controls the gate voltage limiting unit to work. The input terminal of the surge suppression unit is connected to the OUT terminal, and the output terminal is connected to the input terminal of the logic control unit and the gate voltage limiting unit, respectively. The output terminal of the gate voltage limiting unit is connected to the GATE terminal to keep the voltage of the GATE terminal within a set range. The surge suppression unit includes a high-side reference generation module, a high-side ground generation module, a surge judgment and comparison module, a slope detection module, as well as a power MOSFET, resistor R5, resistor R6 and capacitor C4. The resistors R5 and R6 are connected in series between the OUT terminal and GND, and the connection point of the resistors R5 and R6 serves as the FB terminal for output feedback. The high-side reference generation module is used to generate a reference voltage. Its input terminal is connected to an external voltage Vref1, and its output terminal is connected to the first input terminal of the surge judgment and comparison module. The high-side ground generation module is used to generate high-side ground voltage. Its input terminal is connected to the OUT terminal, and its output terminal is connected to the third input terminal of the surge judgment and comparison module. The surge judgment and comparison module is used to determine whether the voltage at the VBB terminal exceeds a preset value. Its second input terminal is connected to the FB terminal, its fourth input terminal is connected to the OUT terminal, and its output terminal is connected to the input terminal of the gate voltage limiting unit and the logic control unit, respectively. The slope detection module is used to detect the voltage rise slope at the VBB terminal. When the rise slope is higher than the preset slope, the gate voltage of the power MOSFET is pulled down to turn it off. The first input terminal of the slope detection module and the drain of the power MOSFET are both connected to the VBB terminal, the second input terminal of the slope detection module is connected to the OUT terminal, and the output terminal of the slope detection module and the gate of the power MOSFET are both connected to the GATE terminal. The source of the power MOSFET is connected to the OUT terminal, and the gate is connected to the GATE terminal; one end of the capacitor C4 is connected to the OUT terminal, and the other end is connected to GND. The slope detection module includes MOSFET N5, MOSFET N6, resistor R4 and capacitor C3; The source of MOSFET N5 and MOSFET N6 and one end of resistor R4 are respectively used as the second input terminal of the slope detection module and connected to the OUT terminal. The gate and drain of MOSFET N5 are shorted and then connected to the gate of MOSFET N6. The drain of MOSFET N5 is connected to the other end of resistor R4. One end of capacitor C3 is used as the first input terminal of the slope detection module and connected to the VBB terminal. The other end is connected to the drain of MOSFET N5. The drain of the MOS transistor N6 serves as the output terminal of the slope detection module and is connected to the GATE terminal.

2. The surge suppressor chip according to claim 1, characterized in that: It also includes the reference current I1; The gate voltage limiting unit includes MOSFETs M2, M3, M4, M5, and M6, and NOT gate U3; The source of the MOS transistor M2 is connected to a charge pump, and its gate is connected to the input of the NOT gate U3. The source of the MOSFET M3 is connected to the reference current I1, the gate is connected to the output terminal of the NOT gate U3, and the drain is connected to the drain of the MOSFET M2 and the drain of the MOSFET M4; the drains of the MOSFETs M3, M2 and M4 are all connected to the gate of the power MOSFET. The source of MOS transistor M4 is connected to the source of MOS transistor M5, and the gate is connected to the gate of MOS transistor M5 and the drain of M6. The drain of MOSFET M2 serves as the output of the gate voltage limiting unit and is connected to the gate of the power MOSFET; the gate of MOSFET M6 and the input of NOT gate U3 serve as the input of the gate voltage limiting unit and are connected to the output of the surge judgment and comparison module.

3. A surge suppressor chip according to claim 2, characterized in that: The high-side reference generation module includes a first comparator U1, a MOS transistor N1, a resistor R1, and a resistor R2; The non-inverting input of the first comparator U1 serves as the input of the high-side reference generation module, connected to the external reference voltage Vref1. The inverting input is connected to the source of MOSFET N1, and the output is connected to the gate of MOSFET N1. The source of the MOS transistor N1 is connected to GND through resistor R1, and the drain is connected to the OUT terminal through resistor R2, and is connected to the first input terminal of the surge detection and comparison module.

4. A surge suppressor chip according to claim 3, characterized in that: The high-side reference generation module also includes a filtering circuit; The filter circuit includes a resistor R3 and a capacitor C1; One end of the resistor R3 is connected to the drain of the MOSFET N1, and the other end is connected to the first input terminal of the surge detection and comparison module. The two ends of the capacitor C1 are connected to the other end of the resistor R3 and the OUT terminal, respectively.

5. A surge suppressor chip according to claim 4, characterized in that: The high-side ground generation module includes a Zener diode D1, a Zener diode D2, a capacitor C2, a MOSFET P1, a MOSFET N2, a MOSFET N3, and a MOSFET N4; The positive terminal of Zener diode D1 is connected to the drain of MOSFET N2, the positive terminal of Zener diode D2 is connected to the drain of MOSFET P1, and the negative terminals of both Zener diode D1 and Zener diode D2 are connected to the OUT terminal. The gates of MOS transistors N2, N3, and N4 are connected and then connected to GND; the source of MOS transistor N2 is connected to the drain of MOS transistor N3, the source of MOS transistor N3 is connected to the drain of MOS transistor N4, the source of MOS transistor N4 is connected to GND, the gate of MOS transistor P1 is connected to the drain of MOS transistor N2, and the source of MOS transistor P1 is connected to GND. The two ends of the capacitor C2 are connected to the OUT terminal and the drain of the MOS transistor P1, respectively. The drain of the MOS transistor P1 is connected to the third input terminal of the surge detection and comparison module.

6. A surge suppressor chip according to claim 1, characterized in that: The surge judgment and comparison module includes a second comparator U2; The non-inverting input of the second comparator U2 is connected to the output of the high-side reference generation module, the inverting input is connected to the FB terminal, and the output is connected to the input of the gate voltage limiting unit and the logic control unit, respectively. The third and fourth inputs of the surge judgment comparison module are the low power supply side and the high power supply side of the second comparator U2, respectively. The low power supply side of the second comparator U2 is connected to the output of the high-side ground generation module, and the high power supply side is connected to the OUT terminal.

7. A high-edge intelligent actuator, characterized in that: Includes the surge suppressor chip according to any one of claims 1-6.

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