MOSFET packaging structure and manufacturing method thereof, circuit board assembly, and electronic device

Abstract

The MOSFET packaging structure and its manufacturing method, circuit board assembly, and electronic device provided by the present application, the MOSFET packaging structure is formed by mounting the first surface of the MOSFET chip in the installation area of ​​the carrier chip, the interconnection distance between the MOSFET chip and the carrier chip is short, the parasitic inductance is small, and it is easy to achieve high-frequency drive. In addition, the MOSFET component is formed by mounting a conductive member on the second surface of the MOSFET chip, the input pad, the output pad, and the ground pad on the MOSFET chip are large current passing areas, and three conductive members are set to be electrically connected to the input pad, the output pad, and the ground pad respectively, and the large current passing area of ​​the MOSFET chip is interconnected with the circuit board through the conductive member, and the conductive member not only has a high current carrying capacity, but also can reduce the resistance of the interconnection, reduce the heat generation of the MOSFET chip, and the conductive member has a strong thermal conductivity, which can improve the heat dissipation performance of the MOSFET chip. In addition, the MOSFET component is directly mounted on the carrier chip to form the MOSFET packaging structure, and the packaging volume is small, which is conducive to the miniaturization of the MOSFET packaging structure.

Description

Technical Field

[0001] The present application relates to the field of semiconductor packaging technology, and in particular to a MOSFET packaging structure and a manufacturing method thereof, a circuit board assembly, and an electronic device. Background Art

[0002] With the trend of thinner, lower power consumption and more diversified functions in consumer electronics, more and more devices are required to be integrated on the motherboard, and the space reserved for devices is getting smaller and smaller. The packaged chips must be thin, light and short, thus providing more choices for product design between thinness and high performance.

[0003] Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is a field-effect transistor that uses electric field effects to control semiconductors. Due to the characteristics of MOSFET that can achieve low-power voltage control, it has been widely used in electronic devices (such as mobile phones) in recent years. Among them, gallium nitride (GaN) MOS has lower on-resistance and fast switching speed compared to traditional silicon MOS, which can achieve lower switching losses and has broad application prospects. At present, most gallium nitride MOS are discrete device packages and driven by separate drivers.

[0004] However, independently packaged GaN MOS and drivers occupy a large volume and require electrical connections through a large number of leads. The leads introduce parasitic inductance, resulting in switching losses and other problems. Summary of the invention

[0005] The present application provides a MOSFET packaging structure and a manufacturing method thereof, a circuit board assembly, and an electronic device. The MOSFET packaging structure has a simple structure, a small size, and a small parasitic inductance, and can achieve high current carrying capacity and low thermal resistance, thereby solving problems such as switching loss.

[0006] In a first aspect, the present application provides a MOSFET packaging structure, including a carrier chip, a MOSFET chip, and three conductive members;

[0007] One side surface of the carrier chip is a mounting surface, a plurality of first pads are distributed on the mounting surface, the mounting surface has a mounting area, a plurality of first pads are arranged in the mounting area, the MOSFET chip has a first surface and a second surface opposite to each other, the first surface is mounted in the mounting area and connected to the first pads in the mounting area, and the three conductive members are all mounted on the second surface and are arranged at intervals;

[0008] The MOSFET chip includes an input pad, an output pad and a ground pad, and three conductive parts are electrically connected to the input pad, the output pad and the ground pad respectively.

[0009] The MOSFET packaging structure provided by the present application realizes the interconnection of the control signals of the MOSFET chip and the carrier chip by mounting the first surface of the MOSFET chip in the mounting area of ​​the carrier chip through the first pad on the carrier chip, the interconnection distance between the MOSFET chip and the carrier chip is short, the parasitic inductance is small, and high-frequency driving is easy to realize. In addition, the MOSFET component is formed by mounting a conductive member on the second surface of the MOSFET chip, the input pad, the output pad and the ground pad on the MOSFET chip are large current passing areas, and three conductive members are respectively electrically connected to the input pad, the output pad and the ground pad, and the large current area of ​​the MOSFET chip is interconnected with the circuit board through the conductive member, the conductive member not only has a high current carrying capacity, but also can reduce the resistance of the interconnection, the heat generation of the MOSFET chip is less, and the heat conductivity of the conductive member is strong, which can effectively improve the heat dissipation performance of the MOSFET chip. In addition, the MOSFET component is directly mounted on the carrier chip to form the MOSFET packaging structure, and the packaging volume is small, which is conducive to the miniaturization of the MOSFET packaging structure.

[0010] When the MOSFET package structure is assembled on a circuit board, the high current area of ​​the MOSFET chip is interconnected with the circuit board through a conductive member, and other areas of the MOSFET chip and the circuit board, as well as the carrier chip and the circuit board, are interconnected through conductive materials.

[0011] In a possible embodiment, the input pad, the output pad and the ground pad are all located on the side where the first surface is located, the first pad in the mounting area includes an input terminal pad, an output terminal pad and a ground terminal pad, the input pad is connected to the input terminal pad accordingly, the output pad is connected to the output terminal pad accordingly, and the ground pad is connected to the ground terminal pad accordingly.

[0012] The input pad, output pad and ground pad are arranged on the first surface of the MOSFET chip, and the first surface of the MOSFET chip is its active surface, so that the carrier chip can transmit the driving signal to the active surface of the MOSFET chip. At this time, the input terminal pad, output terminal pad and ground terminal pad corresponding to the input pad, output pad and ground pad are arranged in the mounting area of ​​the carrier chip, so as to realize the transmission of large current between the MOSFET chip and the circuit board.

[0013] In a possible implementation, the conductive member is a conductive frame, the conductive frame includes a main board portion and a side board portion, the main board portion covers the second surface, one end of the side board portion is connected to a side edge of the main board portion, and the other end of the side board portion extends toward the carrier chip;

[0014] The side plates of the three conductive frames are respectively connected to the input terminal pad, the output terminal pad and the ground terminal pad.

[0015] By setting the conductive frame to include a main board portion and a side board portion, the main board portion is correspondingly attached to the second surface of the MOSFET chip, the side board portion is connected to the side of the main board portion and extends toward the carrier chip, and the side board portion is connected to the first pad on the carrier chip through a conductive material, so as to connect the conductive frame to the corresponding input pad, output pad or ground pad on the MOSFET core through the first pad, thereby realizing high current transmission between the circuit board and the MOSFET chip.

[0016] In a possible implementation manner, an adhesive layer is provided between the conductive frame and the MOSFET chip.

[0017] The conductive frame is an independent structural component. By providing a glue layer between the conductive frame and the MOSFET chip, the MOSFET chip is mounted on the conductive frame to form a MOSFET component.

[0018] In a possible implementation, the conductive frame includes a copper frame or a copper alloy frame.

[0019] By using copper or copper alloy materials to make a conductive frame, copper and copper alloys have high electrical and thermal conductivity. Using the copper frame as a conductive part can not only achieve a high current-carrying capacity of the conductive part, but also efficiently conduct the heat generated by the MOSFET chip, thereby improving the performance of the MOSFET packaging structure.

[0020] In a possible implementation manner, the input pad, the output pad, and the ground pad are all located on the side where the second surface is located, and the three conductive members cover the input pad, the output pad, and the ground pad respectively.

[0021] In the case where the input pad, output pad and ground pad are all arranged on the side where the second surface of the MOSFET chip is located, the three conductive parts attached to the second surface of the MOSFET chip can respectively cover the input pad, output pad and ground pad to achieve connection between the input pad, output pad and ground pad and the corresponding conductive parts.

[0022] In a possible implementation manner, the conductive member is a conductive layer covering the second surface.

[0023] Conductive layers are deposited on the second surface of the MOSFET chip so that each conductive layer covers the corresponding input pad, output pad and ground pad, thereby achieving electrical connection between the input pad, output pad and ground pad and the corresponding conductive layer.

[0024] In a possible implementation, the conductive layer includes a copper layer or an aluminum layer.

[0025] By setting the conductive layer as a copper layer or an aluminum layer, it can be ensured that the conductive layer has high electrical conductivity and thermal conductivity. The conductive layer can not only realize the high current carrying capacity of the conductive part, but also efficiently conduct the heat generated by the MOSFET chip to improve the performance of the MOSFET packaging structure.

[0026] In a possible implementation, a plurality of conductive pads are distributed on the first surface, and the conductive pads are connected to the first pads in the mounting area in a one-to-one correspondence.

[0027] By providing a conductive pad, the conductive pad is electrically connected to the first pad on the carrier chip, so as to achieve the transmission of the driving signal between the MOSFET chip and the carrier chip. By providing the conductive pad on the first surface of the MOSFET chip, the conductive pad is opposite to the first pad, and the two are connected by a conductive material, the interconnection distance of the driving signal between the MOSFET chip and the carrier chip is short, the parasitic inductance is small, and high-frequency driving is easy to achieve.

[0028] In a possible implementation manner, the MOSFET chip is a GaN MOSFET.

[0029] By setting the MOSFET chip to GaN MOSFET, GaN MOSFET has lower on-resistance and fast switching speed, which can reduce the area of ​​peripheral devices and the volume of MOSFET packaging structure; in addition, GaN MOSFET can effectively reduce switching losses and improve power efficiency.

[0030] In a possible implementation, the carrier chip includes a chip body, a dielectric layer and a wiring layer;

[0031] The dielectric layer covers the chip body, the wiring layer is arranged in the dielectric layer, and the side of the wiring layer facing the chip body is connected to the conductive structure in the chip body. The surface of the wiring layer facing away from the chip body has an exposed area exposed outside the dielectric layer, and the first pad corresponds to the exposed area.

[0032] An insulating dielectric layer is provided on the chip body, and a wiring layer is provided in the dielectric layer, so that the dielectric layer protects the wiring layer. Each conductive wire in the wiring layer is connected to a conductive structure in the chip body, and the dielectric layer realizes electrical isolation between the conductive wire and other areas on the chip body. In addition, an exposed area is provided on a surface of the wiring layer facing away from the chip body, and the exposed area is exposed outside the dielectric layer. The first pad is provided corresponding to the exposed area, so as to realize electrical connection between the carrier chip and the MOSFET chip and the circuit board.

[0033] In a possible implementation, the dielectric layer includes a first dielectric layer and a second dielectric layer sequentially stacked on the chip body, and the wiring layer is arranged between the first dielectric layer and the second dielectric layer;

[0034] The first dielectric layer is provided with a via hole, and the wiring layer is electrically connected to the chip body through the via hole; the second dielectric layer has an opening, and the exposed area is exposed in the opening.

[0035] By arranging a first dielectric layer on the chip body, a wiring layer is arranged on the first dielectric layer, and the conductive wires in the wiring layer are connected to the conductive structure in the chip body through the vias in the first dielectric layer, the first dielectric layer realizes electrical isolation between the wiring layer and other areas of the chip body. By stacking a second dielectric layer on the first dielectric layer, the second dielectric layer covers the wiring layer to form protection for the wiring layer, and by opening the second dielectric layer, a local area of ​​the conductive wire is exposed in the opening, and a first pad is arranged corresponding to the exposed area of ​​the conductive wire, so as to realize electrical connection between the carrier chip and the MOSFET chip and the circuit board.

[0036] In a second aspect, the present application provides a method for manufacturing a MOSFET packaging structure, comprising:

[0037] A plurality of MOSFET components are provided; the MOSFET components include a MOSFET chip and three conductive members, the MOSFET chip has a first surface and a second surface opposite to each other, the three conductive members are mounted on the second surface and are arranged at intervals; wherein the MOSFET chip includes an input pad, an output pad and a ground pad, and the three conductive members are electrically connected to the input pad, the output pad and the ground pad respectively;

[0038] Providing a wafer, wherein the wafer includes a plurality of chip bodies arranged in an array;

[0039] A dielectric layer and a wiring layer are formed on one side surface of the wafer; the dielectric layer covers the wafer, the wiring layer is arranged in the dielectric layer, and the side of the wiring layer facing the wafer is connected to the conductive structure in the chip body, and the surface of the wiring layer facing away from the wafer has an exposed area exposed outside the dielectric layer, and a first pad is formed corresponding to the exposed area;

[0040] Mounting the MOSFET component on the wafer, wherein the first surface of the MOSFET chip is connected to the first pad via a conductive material;

[0041] Cut the wafer to form a single MOSFET package structure.

[0042] The manufacturing method of the MOSFET packaging structure provided by the present application provides a plurality of MOSFET components, forms a dielectric layer and a wiring layer on the surface of a wafer, and then mounts each MOSFET component on the wafer in an area corresponding to each carrier chip, and then cuts the wafer to form a plurality of single MOSFET packaging structures. In this way, the volume of the MOSFET packaging structure is reduced through the wafer-level chip packaging method, which is conducive to the miniaturization of the MOSFET packaging structure, and simplifies the packaging process steps, reduces the packaging cost, and improves the packaging efficiency.

[0043] In a possible implementation, the input pad, the output pad, and the ground pad are all located on the side where the first surface is located, and providing a MOSFET component includes:

[0044] A conductive frame is provided as a conductive member; the conductive frame comprises a main board portion and a side board portion, one end of the side board portion is connected to a side edge of the main board portion, and the other end of the side board portion extends toward one side of the main board portion;

[0045] The MOSFET chip is connected to the conductive frame, and the MOSFET chip is located in the area surrounded by the main board part and the side board part.

[0046] In one possible implementation, a plurality of MOSFET components are provided, including:

[0047] Providing a conductive plate;

[0048] Processing the conductive plate to form a plurality of interconnected conductive frames;

[0049] Connect each MOSFET chip to each conductive frame accordingly;

[0050] Cut the conductive sheet to form multiple MOSFET components.

[0051] By providing a conductive plate, the conductive plate is first processed into a plurality of interconnected conductive frames, each MOSFET chip is mounted on a corresponding conductive frame, and then the conductive plate is cut to form a plurality of separate MOSFET components. In this way, a plurality of MOSFET components can be formed at the same time, and MOSFET components can be manufactured in batches, thereby improving the manufacturing efficiency of MOSFET components.

[0052] In a possible implementation manner, processing the conductive plate includes:

[0053] The conductive plate is formed into a plurality of interconnected conductive frames by adopting a photolithography process or a stamping process.

[0054] In a possible implementation, the input pad, the output pad, and the ground pad are all located on the side where the second surface is located, and providing a MOSFET component includes:

[0055] Provide MOSFET chips;

[0056] A conductive layer is formed on the second surface of the MOSFET chip, the conductive layer serving as a conductive member, and three conductive layers cover the input pad, the output pad and the ground pad respectively.

[0057] In a possible implementation manner, forming a dielectric layer and a wiring layer on a surface of one side of a wafer includes:

[0058] forming a first dielectric layer having a via hole on a surface of one side of the wafer;

[0059] Laying a wiring layer on the first dielectric layer, wherein the wiring layer is electrically connected to the chip body through the via hole;

[0060] A second dielectric layer having an opening is formed on the first dielectric layer, the second dielectric layer covers the wiring layer, and the exposed area is exposed in the opening.

[0061] In a third aspect, the present application provides a circuit board assembly, including a circuit board and the MOSFET packaging structure as described above, wherein a plurality of second pads are distributed on the circuit board, and the MOSFET packaging structure is connected to the second pads via a conductive material.

[0062] The circuit board assembly provided by the present application includes a circuit board and a MOSFET packaging structure mounted on the circuit board. The MOSFET packaging structure realizes the interconnection of the control signal of the MOSFET chip and the carrier chip by mounting the first surface of the MOSFET chip in the mounting area of ​​the carrier chip through the first pad on the carrier chip. The interconnection distance between the MOSFET chip and the carrier chip is short, the parasitic inductance is small, and it is easy to realize high-frequency driving. In addition, the MOSFET component is formed by mounting a conductive member on the second surface of the MOSFET chip. The input pad, output pad and ground pad on the MOSFET chip are large current passing areas. By setting three conductive members, they are electrically connected to the input pad, output pad and ground pad respectively. The large current area of ​​the MOSFET chip is interconnected with the circuit board through the conductive member. The conductive member not only has a high current carrying capacity, but also can reduce the resistance of the interconnection, the heat generation of the MOSFET chip is less, and the heat conductivity of the conductive member is strong, which can effectively improve the heat dissipation performance of the MOSFET chip. In addition, the MOSFET component is directly mounted on the carrier chip to form the MOSFET packaging structure, and the packaging volume is small, which is conducive to the miniaturization of the MOSFET packaging structure.

[0063] In a fourth aspect, the present application provides an electronic device, comprising a housing and the circuit board assembly as described above, wherein the circuit board assembly is disposed in the housing.

[0064] The electronic device provided by the present application includes a housing and a circuit board assembly arranged in the housing, the circuit board assembly includes a circuit board and a MOSFET packaging structure mounted on the circuit board, the MOSFET packaging structure realizes the control signal interconnection between the MOSFET chip and the carrier chip by mounting the first surface of the MOSFET chip in the mounting area of ​​the carrier chip through the first pad on the carrier chip, the interconnection distance between the MOSFET chip and the carrier chip is short, the parasitic inductance is small, and it is easy to realize high-frequency driving. In addition, the MOSFET component is formed by mounting a conductive member on the second surface of the MOSFET chip, the input pad, the output pad and the grounding pad on the MOSFET chip are large current passing areas, and three conductive members are respectively electrically connected to the input pad, the output pad and the grounding pad, and the large current area of ​​the MOSFET chip is interconnected with the circuit board through the conductive member, the conductive member not only has a high current carrying capacity, but also can reduce the resistance of the interconnection, the heat generation of the MOSFET chip is less, and the heat conductivity of the conductive member is strong, which can effectively improve the heat dissipation performance of the MOSFET chip. In addition, the MOSFET component is directly mounted on the carrier chip to form the MOSFET packaging structure, and the packaging volume is small, which is conducive to the miniaturization of the MOSFET packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0065] Figure 1 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application;

[0066] Figure 2 A top view of a circuit board assembly provided in an embodiment of the present application;

[0067] Figure 3 A schematic diagram of the packaging structure of a GaN MOSFET in the related art;

[0068] Figure 4 for Figure 2 Schematic diagram of the cross section at AA in the middle;

[0069] Figure 5 for Figure 4 A schematic cross-sectional view of the MOSFET package structure in FIG.

[0070] Figure 6 A planar structural diagram of a MOSFET packaging structure provided in an embodiment of the present application;

[0071] Figure 7 A circuit diagram of a MOSFET packaging structure provided in an embodiment of the present application;

[0072] Figure 8a for Figure 6 A schematic cross-section diagram at BB in the middle;

[0073] Figure 8b for Figure 6 A schematic cross-sectional view at CC in the middle;

[0074] Figure 9a for Figure 6 Another cross-sectional schematic diagram at the middle BB;

[0075] Figure 9b for Figure 6 Another cross-sectional schematic diagram at CC in the middle;

[0076] Fig.10 A flowchart of the steps of the method for manufacturing the MOSFET packaging structure provided in the embodiment of the present application;

[0077] Fig.11 A schematic diagram of manufacturing a MOSFET component provided in an embodiment of the present application;

[0078] Fig.12 A schematic diagram of forming a dielectric layer and a wiring layer on a wafer provided in an embodiment of the present application;

[0079] Fig.13 A schematic diagram of forming a MOSFET packaging structure provided in an embodiment of the present application. DETAILED DESCRIPTION

[0080] The terms used in the implementation section of this application are only used to explain the specific embodiments of this application and are not intended to limit this application.

[0081] MOSFET is a field effect transistor that uses electric field effect to control semiconductors. Since MOSFET can work under low current and low voltage conditions, and its manufacturing process is convenient for integrated design, MOSFET has been widely used in large-scale integrated circuits. For example, MOSFET can be used in power supplies for consumer electronic products, such as mobile phone fast charging power supplies, adapters, and personal computer (PC) power lights; in addition, MOSFET can also be used in industrial power supplies (such as server power supplies, communication power supplies, etc.), electric vehicle on-board chargers, on-board DC (direct current)-DC converters, etc.

[0082] The present application provides an electronic device, which may be the above electronic device or other electronic devices provided with MOSFET. Figure 1 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application. Figure 1As shown, taking the electronic device as a mobile phone charger as an example, the electronic device may include a housing 2 and a charging plug 3, the housing 2 may be provided with a connecting wire socket 2a, and the charging plug 3 and the connecting wire socket 2a may be respectively located at opposite sides of the housing 2. When working, the charging plug 3 of the mobile phone charger is plugged into an external power source (such as a socket), one end of a data cable adapted to the mobile phone is connected to the connecting wire socket 2a of the mobile phone charger, and the other end of the data cable is connected to the mobile phone to charge the mobile phone.

[0083] Continue to refer to Figure 1 As shown, a circuit board assembly 1 is also provided in the housing 2, and the circuit board assembly 1 is used to absorb the current of the external power supply and then transmit the current to the electrical device (such as the battery of a mobile phone). The circuit board assembly 1 includes a circuit board (not shown in the figure) and a MOSFET packaging structure (not shown in the figure). The circuit board is, for example, a printed circuit board (Printed Circuit Board, PCB). The MOSFET packaging structure is connected to the circuit board through a conductive material to achieve the fixation of the MOSFET packaging structure and the electrical connection between the MOSFET packaging structure and the circuit board. Exemplarily, for the circuit board assembly 1 used in the power supply, the MOSFET packaging structure is mainly used as a switch in the circuit board assembly 1, which acts as a bridge to transmit the current of the external power supply to the electrical device through the circuit board.

[0084] Figure 2 A top view of a circuit board assembly provided in an embodiment of the present application. Figure 2 As shown, the MOSFET package structure 10 includes a carrier chip 100 and a MOSFET chip 210. The MOSFET chip 210 is mainly used as a switch. The carrier chip 100 is used to provide a charging current to the MOSFET chip 210 when driving the MOSFET chip 210 to turn on, so as to ensure that the MOSFET chip 210 can turn on quickly and maintain a stable voltage during the conduction period of the MOSFET chip 210, so as to ensure that the MOSFET chip 210 can be turned on reliably. Exemplarily, the carrier chip 100 can be a silicon chip, and the MOSFET chip 210 is packaged on the silicon chip to form the MOSFET package structure 10; the MOSFET package structure 10 is installed on the circuit board 20 to form the circuit board assembly 1.

[0085] At present, wide bandgap semiconductor devices represented by GaN are called third-generation semiconductor devices. GaN materials have the advantages of large bandgap width, high electron mobility and strong breakdown electric field. They can be used in high temperature, high voltage and high frequency working environments and have broad application prospects. Among them, GaN MOSFET has been widely used in the field of small and medium power adapters (such as mobile phone chargers). Compared with traditional Si MOSFET, GaN MOSFET has lower on-resistance (on-resistance between source and drain), fast switching speed, can reduce the area of ​​peripheral devices (such as inductors and capacitors), and reduce the volume of MOSFET packaging structure 10; and GaN MOSFET can effectively reduce switching losses and improve power efficiency.

[0086] When packaging the MOSFET chip 210, that is, when forming the MOSFET packaging structure 10, unlike the traditional Si MOSFET which can be directly integrated on the carrier chip 100 because the base material is the same as the collective material of the silicon chip, the GaN MOSFET is currently usually packaged as a discrete device and driven by a separate driver, that is, the GaN MOSFET and the driver are separately packaged on a circuit board and then the two are electrically connected.

[0087] In order to facilitate the packaging of GaN MOSFET, a co-sealing solution of GaN MOSFET and driver has been proposed. Figure 3 Schematic diagram of the packaging structure of GaN MOSFET in the related art, refer to Figure 3 As shown, at present, the GaN MOSFET 12 and the silicon chip 11 are usually bonded to the lead frame 14 through the packaging glue 13, and the lead frame 14 is soldered to the circuit board 16 through the solder 15. There is a certain distance between the GaN MOSFET 12 and the silicon chip 11, and the GaN MOSFET 12 and the silicon chip 11 are connected to the lead frame 14 through the connecting wire 17 (welding wire, lead wire), and a large number of connecting wires 17 are also connected between the GaN MOSFET 12 and the silicon chip 11 to achieve electrical connection between each other. The lead frame 14 is usually also covered with a plastic sealing layer 18, and the plastic sealing layer 18 wraps the GaN MOSFET 12, the silicon chip 11, and the connecting wires 17 connected between the GaN MOSFET 12, the silicon chip 11 and the lead frame 14 inside it to protect the packaging structure of the GaN MOSFET 12.

[0088] However, the connection wires 17 between the GaN MOSFET 12, the silicon chip 11 and the lead frame 14 will introduce a large amount of parasitic inductance, which will cause problems such as switching losses and affect the driving frequency of the packaging structure. In addition, the packaging method of the connection wires 17 plus the lead frame 14 makes the packaging structure larger in size, which is not conducive to the miniaturization of the packaging structure.

[0089] Among them, combined Figure 3 As shown, the overall thickness of the packaging structure is the thickness of the lead frame 14 plus the plastic layer 18, the surface of the GaN MOSFET 12 and the silicon chip 11 on the side facing away from the circuit board 16 is the electrode surface of the two (the side for drawing out current), the connecting wire 17 is connected to the surface of the two on the side facing away from the circuit board 16, the arc height of the connecting wire 17 (the distance between the curved top of the connecting wire 17 and the lead frame 14) is greater than the thickness of the GaN MOSFET 12 itself and the silicon chip 11 itself, because the plastic layer 18 needs to completely cover the GaN MOSFET 12, the silicon chip 11 and the connecting wire 17, and in order to make the plastic layer 18 have sufficient protection effect, the thickness of the plastic layer 18 should ensure that it covers at least 100μm above the curved top of the connecting wire 17. Therefore, the way in which the GaN MOSFET 12 and the silicon chip 11 are installed side by side on the lead frame 14 causes the package structure to occupy a larger plane area, and due to the arc height limitation of the connecting wire 17, the thickness of the plastic layer 18 is thicker, resulting in a larger overall thickness of the package structure, and therefore a larger volume of the package structure.

[0090] In addition, for GaN MOSFET12 with large current carrying capacity requirements, the packaging structure needs to have good heat dissipation performance. In the packaging solution of connecting wire 17 plus lead frame 14, the heat generated by GaN MOSFET12 is mainly transferred to the lead frame 14 at the bottom thereof, and is dissipated by transferring it to circuit board 16 through lead frame 14 and solder 15. However, the rest of GaN MOSFET12 is wrapped by plastic layer 18. Plastic layer 18 is limited by material and thickness, and has poor heat dissipation performance. The heat of GaN MOSFET12 cannot be dissipated to the outside world in a timely and effective manner through plastic layer 18.

[0091] In view of this, in the circuit board assembly 1 of the present embodiment, a conductive member is attached to one side of the MOSFET chip 210, and the conductive member and the MOSFET chip 210 together constitute a MOSFET assembly, and the surface of the side of the MOSFET chip 210 exposed outside the conductive member is attached to the mounting surface of the carrier chip 100, so as to form a MOSFET package structure 10. The MOSFET package structure 10 has a small volume, which is conducive to the miniaturization of the package structure; and, by attaching the MOSFET chip 210 to the carrier chip 100, the signal interconnection with low parasitic inductance can be realized between the MOSFET chip 210 and the carrier chip 100, and between the MOSFET chip 210, the carrier chip 100 and the circuit board 20, without causing problems such as switching loss, and it is easy to realize high-frequency driving, with small thermal resistance and good heat dissipation performance, which can improve the performance of the MOSFET package structure 10.

[0092] The circuit board assembly 1 of this embodiment is described in detail below.

[0093] Figure 4 for Figure 2 Schematic diagram of the cross section at AA. Figure 4 As shown, one side surface of the carrier chip 100 is a mounting surface 101, and a plurality of first pads 102 are distributed on the mounting surface 101. The MOSFET chip 210 is mounted on the mounting surface 101 of the carrier chip 100 to form a MOSFET package structure 10, and the MOSFET chip 210 is connected to the corresponding first pads 102 on the mounting surface 101 of the carrier chip 100, so as to achieve a fixed connection and electrical connection between the MOSFET chip 210 and the carrier chip 100.

[0094] When the MOSFET package structure 10 is mounted on the circuit board 20, the mounting surface 101 of the carrier chip 100 is opposite to the circuit board 20, and the MOSFET package structure 10 is mounted face to face on the circuit board 20 to form a circuit board assembly 1. Among them, a plurality of second pads 23 are distributed on the board surface of the circuit board 20, and the MOSFET chip 210 mounted on the mounting surface 101 of the carrier chip 100 is opposite to the circuit board 20. The MOSFET chip 210 and the corresponding second pads 23 on the circuit board 20 are connected through the conductive material 30 to achieve electrical connection between the MOSFET chip 210 and the circuit board 20; as for other areas of the mounting surface 101 of the carrier chip 100, the first pad 102 on the carrier chip 100 and the second pad 23 on the circuit board 20 are opposite, and the conductive material 30 is arranged between the first pad 102 and the second pad 23, and the first pad 102 of the carrier chip 100 and the second pad 23 of the circuit board 20 are connected through the conductive material 30 to achieve fixed connection and electrical connection between the carrier chip 100 and the circuit board 20.

[0095] Exemplarily, the conductive material 30 between the MOSFET chip 210 and the second pad 23 and the conductive material 30 between the first pad 102 and the second pad 23 may be Sn or SnAg.

[0096] During operation, the control signal is transmitted to the carrier chip 100 through the circuit board 20, and the carrier chip 100 drives the MOSFET chip 210 to turn on, provides charging current to the MOSFET chip 210, and keeps the voltage of the MOSFET chip 210 stable during the conduction period. When the MOSFET chip 210 is turned on, the main large current signal is transmitted from the circuit board 20 to the MOSFET chip 210. In addition, the drive signal is transmitted between the MOSFET chip 210 and the carrier chip 100, and between the MOSFET chip 210 and the circuit board 20.

[0097] Exemplarily, the MOSFET chip 210 can be the aforementioned GaN MOSFET, or the MOSFET chip 210 can also be other chips that need to be sealed with the carrier chip 100; the carrier chip 100 can be the aforementioned silicon chip, or the carrier chip 100 can also be other chips that can provide a driving signal for the MOSFET chip 210, and this embodiment does not impose any specific restrictions on this.

[0098] In addition, refer to Figure 4 As shown, it should be noted that the carrier chip 100 includes a chip body 110 and a wiring structure arranged on the surface of the chip body 110. Taking the carrier chip 100 as a silicon chip as an example, the material constituting the chip body 110 may be single crystal silicon, and a conductive structure (not shown in the figure) is provided in the chip body 110. Exemplarily, the conductive structure may be a transistor, a diode or other components arranged in the chip body 110, or the conductive structure may be an interconnection structure such as a conductive column or a conductive line arranged in the chip body 110, and the conductive structure is exposed on the surface of the chip body 110.

[0099] The wiring structure includes a dielectric layer 120 disposed on the surface of the chip body 110 and a wiring layer 130 disposed in the dielectric layer 120. The dielectric layer 120 can protect the wiring layer 130, and the wiring layer 130 is used to connect with the conductive structure in the chip body 110. The dielectric layer 120 has an opening 1221 on the side away from the chip body 110. A partial area of ​​the conductive wire 131 is exposed in the opening 1221 of the dielectric layer 120. The exposed area of ​​the conductive wire 131 is used to connect with the MOSFET chip 210 and the circuit board 20. Among them, the first solder pad 102 is the exposed area of ​​the conductive wire 131; or, the first solder pad 102 is a solder pad added on the exposed area of ​​the conductive wire 131, and the area of ​​the added solder pad can be larger than the area of ​​the exposed area of ​​the conductive wire 131, so as to increase the connection strength between the carrier chip 100 and the MOSFET chip 210 and the circuit board 20 through the first solder pad 102, and enhance the electrical connection stability between the carrier chip 100 and the MOSFET chip 210 and the circuit board 20.

[0100] Figure 5 for Figure 4 Schematic diagram of the cross-section of the MOSFET package structure. Figure 5 As shown, the insulating dielectric layer 120 disposed on the chip body 110 has two layers, and the dielectric layer 120 includes a first dielectric layer 121 and a second dielectric layer 122 sequentially stacked on the chip body 110. The wiring layer 130 is disposed on the first dielectric layer 121, and a via (not shown in the figure) is disposed in the first dielectric layer 121, and each conductive wire 131 in the wiring layer 130 passes through the via to connect with the conductive structure in the chip body 110. The second dielectric layer 122 covers the wiring layer 130, protects the conductive wire 131 in the wiring layer 130, and insulates and isolates the conductive wire 131 from the outside. The second dielectric layer 122 is provided with an opening 1221, and a local area of ​​the conductive wire 131 is exposed in the opening 1221, so as to be connected with the conductive material 30, so as to realize the connection between the carrier chip 100 and the MOSFET chip 210 and the circuit board 20.

[0101] Similar to the carrier chip 100, the circuit board 20 may also include a substrate 21 and a wiring layer (not shown in the figure) arranged on the substrate 21. The wiring layer is a plurality of conductive lines (not shown in the figure) formed on the substrate 21. The wiring layer is usually also covered with an insulating protective layer 22. The protective layer 22 has an opening, and a local area of ​​the conductive line is exposed in the opening on the protective layer 22. The second solder pad 23 is the exposed area of ​​the conductive line, or the second solder pad 23 is a solder pad added on the exposed area of ​​the conductive line, which will not be repeated here.

[0102] Figure 6 This is a plan view of the MOSFET package structure provided in the embodiment of the present application. Figure 6As shown, the mounting surface 101 of the carrier chip 100 has a mounting area 101a, and the mounting area 101a is used to mount the MOSFET chip 210. In this embodiment, the two opposite surfaces of the MOSFET chip 210 in the thickness direction are defined as a first surface 210a and a second surface 210b, respectively. The first surface 210a of the MOSFET chip 210 is mounted in the mounting area 101a, and the corresponding area of ​​the first surface 210a of the MOSFET chip 210 is connected to the first pad 102 in the mounting area 101a. The second surface 210b of the MOSFET chip 210 is used to be electrically connected to the circuit board 20.

[0103] Among them, the first solder pad 102 in the mounting area 101a can be electrically connected to the first solder pad 102 outside the mounting area 101a through the conductive wire 131, and the first solder pad 102 outside the mounting area 101a is connected to the corresponding second solder pad 23 on the circuit board 20. In this way, the circuit board 20 transmits the control signal to the corresponding first solder pad 102 outside the mounting area 101a on the carrier chip 100 through the second solder pad 23, and the carrier chip 100 receives the control signal. The control signal is transmitted to the corresponding first solder pad 102 in the mounting area 101a through the first solder pad 102 outside the mounting area 101a via the conductive wire 131 to drive the MOSFET chip 210 to turn on.

[0104] Combination Figure 5 and Figure 6 As shown, when the MOSFET chip 210 is interconnected with the circuit board 20, in order to allow a larger current to pass between the MOSFET chip 210 and the circuit board 20, in this embodiment, the second surface 210b of the MOSFET chip 210 is also mounted with a conductive member 220, and the conductive member 220 faces the circuit board 20 and is connected to the circuit board 20. Exemplarily, the conductive member 220 can be made of a metal material with high conductivity, such as copper, aluminum, titanium, gold, and silver. In this way, the current carrying capacity of the MOSFET chip 210 can be improved through the conductive member 220, so that the MOSFET chip 210 can achieve a high current carrying effect.

[0105] When the MOSFET chip 210 is working, there is a large current area, and the current flowing through the large current area is large. In this regard, the conductive member 220 is usually arranged corresponding to the large current area to improve the current carrying capacity of the large current area of ​​the MOSFET chip 210 and realize high-frequency driving of the MOSFET chip 210. As for other areas of the MOSFET chip 210 for transmitting driving signals, since the current flowing through is very small, other areas of the second surface 210b of the MOSFET chip 210 can be directly connected to the circuit board 20 through the conductive material 30.

[0106] Combination Figure 4 and Figure 6 As shown, compared with the second surface 210b of the MOSFET chip 210 being directly connected to the circuit board 20 through the conductive material 30 such as Sn or SnAg, by mounting the conductive member 220 as mentioned above on the second surface 210b of the MOSFET chip 210, the conductivity of the conductive member 220 is much higher than that of the conductive material 30 such as Sn or SnAg. Taking Cu as an example, the material constituting the conductive member 220 is 7.4 times that of SnAg. Therefore, the conductive member 220 has a high current carrying capacity, and the contact area between the conductive member 220 and the circuit board 20 is large, so that the high current carrying effect of the MOSFET chip 210 can be achieved.

[0107] In addition, compared with the conductive material 30 such as Sn or SnAg, the thermal conductivity of the conductive member 220 is high. Taking Cu as an example, the thermal conductivity of Cu is 7 times that of SnAg. Therefore, the conductive member 220 not only has a high current carrying capacity, but also can conduct the heat generated by the MOSFET chip 210 in a timely and efficient manner. In this embodiment, the high current area of ​​the MOSFET chip 210 and the circuit board 20 are interconnected by the conductive member 220. Compared with interconnecting the high current area of ​​the MOSFET chip 210 and the circuit board 20 through a connecting wire or a conductive material 30 such as Sn, SnAg, etc., the resistance of the interconnection can be reduced, the heat generation of the MOSFET chip 210 is less, and the conductive member 220 has a strong thermal conductivity, so the heat dissipation performance of the MOSFET chip 210 can be effectively improved.

[0108] Combination Figure 4 and Figure 6 As shown, in this embodiment, the first surface 210a of the MOSFET chip 210 is mounted in the mounting area 101a of the carrier chip 100, and the control signal interconnection between the MOSFET chip 210 and the carrier chip 100 is realized through the first pad 102 on the carrier chip 100. In addition, the MOSFET assembly 200 is formed by mounting the conductive member 220 on the second surface 210b of the MOSFET chip 210. When the MOSFET package structure 10 is assembled on the circuit board 20, the large current area of ​​the MOSFET chip 210 is interconnected with the circuit board 20 through the conductive member 220, and the other areas of the MOSFET chip 210 and the circuit board 20 and the carrier chip 100 and the circuit board 20 are interconnected through the conductive material 30. The interconnection distance between the MOSFET chip 210, the carrier chip 100 and the circuit board 20 is short, the parasitic inductance is small, and it is easy to realize high-frequency driving.

[0109] Furthermore, since the MOSFET chip 210 is mounted on the carrier chip 100 in a face-to-face manner, when the MOSFET package structure 10 is interconnected with the circuit board 20, the MOSFET component 200 does not occupy additional space, and the space occupied by the MOSFET package structure 10 is equivalent to the space occupied by the carrier chip 100 itself. The volume of the MOSFET package structure 10 is small, which is beneficial to the MOSFET package structure 10, so that the MOSFET package structure 10 can be applied in ultra-thin electronic devices. Specifically, when the carrier chip 100 is interconnected with the circuit board 20, the first pad 102 of the carrier chip 100 and the second pad 23 of the circuit board 20 can be connected through the solder ball 30a, and the thickness space of the MOSFET component 200 can be smaller than the thickness space occupied by the solder ball 30a after packaging. There is a gap between the conductive member 220 mounted on the second surface 210b of the MOSFET chip 210 and the circuit board 20, and the conductive member 220 can be connected to the circuit board 20 through a thin layer of conductive material 30, and the MOSFET component 200 does not affect the normal packaging space of the carrier chip 100.

[0110] Exemplarily, the initial diameter of the solder ball 30a connected between the first solder pad 102 of the carrier chip 100 and the second solder pad 23 of the circuit board 20 can be 300μm. After welding, the height of the solder ball 30a is reduced to 200μm. The thickness of the MOSFET chip 210 is, for example, 60μm, and the thickness of the conductive member 220 is, for example, 100μm. There can also be, for example, a 10μm connection space between the conductive member 220 and the second surface 210b of the MOSFET chip 210. In this way, there is also a 30μm wide gap between the conductive member 220 and the circuit board 20, and the conductive material 30 can be set in the gap to achieve electrical connection between the MOSFET chip 210 and the circuit board 20.

[0111] In addition, while mounting the MOSFET package structure 10 on the circuit board 20, ensuring that the interconnection distance between the MOSFET package structure 10 and the circuit board 20 is short and the parasitic inductance is small, the conductive member 220 realizes the characteristics of high current carrying capacity and low thermal resistance when the MOSFET chip 210 is interconnected with the circuit board 20, which can improve the current carrying capacity of the MOSFET chip 210 and ensure the heat dissipation performance of the MOSFET chip 210, thereby improving the working performance of the MOSFET chip 210.

[0112] Figure 7 A circuit diagram of a MOSFET package structure 10 provided in an embodiment of the present application. Figure 7As shown, for the MOSFET chip 210 used in the power supply field, the carrier chip 100 usually drives a half-bridge circuit. At this time, the MOSFET chip 210 usually includes two transistors in a half-bridge arrangement. For example, the MOSFET chip 210 includes a first transistor 210c and a second transistor 210d with a common source. The drain of the first transistor 210c is connected to the external power supply as an input terminal 210e, the drain of the second transistor 210d is a ground terminal 210g, and the common source terminal of the first transistor 210c and the second transistor 210d is connected to the output load as an output terminal 210f.

[0113] During operation, when the external control signal is high, the carrier chip 100 controls the first transistor 210c to turn on and the second transistor 210d to turn off, and the current of the external power supply enters the first transistor 210c from the drain of the first transistor 210c, and is transmitted to the output load through the first transistor 210c; when the external control signal is low, the carrier chip 100 controls the second transistor 210d to turn on and the first transistor 210c to turn off, and the grounded second transistor 210d draws charge from the output load to achieve grounding, and can withstand high voltage.

[0114] That is, the MOSFET chip 210 includes an input terminal 210e, an output terminal 210f and a ground terminal 210g, and the input terminal 210e, the output terminal 210f and the ground terminal 210g of the MOSFET chip 210 are all connected to the outside through the circuit board 20. These three parts are the high current areas when the MOSFET chip 210 and the circuit board 20 are interconnected. Figure 6 As shown, corresponding to the input terminal 210e, output terminal 210f and ground terminal 210g of the MOSFET chip 210, the MOSFET chip 210 is respectively provided with an input pad (not shown in the figure), an output pad (not shown in the figure) and a ground pad (not shown in the figure), and the input pad, output pad and ground pad of the MOSFET chip 210 are respectively used for electrical connection with the circuit board 20.

[0115] In this regard, there may be three conductive members 220 mounted on the second surface 210b of the MOSFET chip 210, and the three conductive members 220 are electrically connected to the input pad, the output pad and the ground pad, respectively. The first conductive member 220 is connected between the input pad and the corresponding second pad 23 on the circuit board 20, the second conductive member 220 is connected between the output pad and the corresponding second pad 23 on the circuit board 20, and the third conductive member 220 is connected between the ground pad and the corresponding second pad 23 on the circuit board 20. The three conductive members 220 are arranged at intervals to achieve electrical isolation between the input pad, the output pad and the ground pad, and the high current carrying capacity of the input terminal 210e, the output terminal 210f and the ground terminal 210g of the MOSFET chip 210 is achieved through the three conductive members 220.

[0116] Figure 8a for Figure 6 A schematic cross-section diagram at BB in the middle; Figure 8b for Figure 6 A cross-sectional diagram at CC in the middle. Figure 8a or Figure 8b As shown, a plurality of conductive pads 213 are provided on the MOSFET chip 210, and the conductive pads 213 are used to be electrically connected to the first pads 102 on the carrier chip 100, so as to transmit driving signals between the carrier chip 100 and the MOSFET chip 210. In order to facilitate the electrical connection between the conductive pads 213 on the MOSFET chip 210 and the first pads 102 on the carrier chip 100, the conductive pads 213 are usually distributed on the first surface 210a of the MOSFET chip 210, and the conductive pads 213 correspond to the first pads 102 on the carrier chip 100 one by one, and the conductive pads 213 of the MOSFET chip 210 and the first pads 102 of the carrier chip 100 are connected through the conductive material 30.

[0117] In this way, for the MOSFET chip 210 mounted face to face on the mounting surface 101 of the carrier chip 100, the conductive pad 213 set on the first surface 210a of the MOSFET chip 210 is directly opposite to the first solder pad 102 of the carrier chip 100, and the interconnection distance of the driving signal between the MOSFET chip 210 and the carrier chip 100 is short, the parasitic inductance is small, and high-frequency driving is easy to achieve.

[0118] As for the arrangement of the input pad 211, the output pad 212 and the ground pad on the MOSFET chip 210, as an implementation, the input pad 211, the output pad 212 and the ground pad on the MOSFET chip 210 can all be located on the side where the first surface 210a is located. In this way, the input pad 211, the output pad 212 and the ground pad are arranged on the same side of the first surface 210a as the conductive pad 213 used to transmit the drive signal, which is equivalent to the active surface of the MOSFET chip 210 being its first surface 210a, so that the drive signal can be transmitted to the active surface of the MOSFET chip 210 through the conductive pad 213.

[0119] At this time, the transmission of large current between the MOSFET chip 210 and the circuit board 20 needs to pass through the first surface 210a of the MOSFET chip 210. Since the first surface 210a of the MOSFET chip 210 is attached to the mounting surface 101 of the carrier chip 100, the mounting surface 101 of the carrier chip 100 should be provided with first pads 102 corresponding to the input pad 211, the output pad 212 and the ground pad on the first surface 210a of the MOSFET chip 210. In this embodiment, the first pads 102 corresponding to the input pad 211, the output pad 212 and the ground pad on the carrier chip 100 are defined as input terminal pads 102a, output terminal pads 102b and ground terminal pads, respectively. The input terminal pad 102a and the input pad 211, the output terminal pad 102b and the output pad 212, and the ground terminal pad and the ground pad are all connected by conductive material 30.

[0120] Since the large current needs to pass through the conductive member 220 and the first pad 102 on the carrier chip 100 when transmitting between the MOSFET chip 210 and the circuit board 20, the conductive member 220 needs to be connected to the first pad 102 on the carrier chip 100. Figure 8a or Figure 8b As shown, the conductive member 220 can be set in the form of a conductive frame 220a, the conductive frame 220a is arranged around the periphery of the MOSFET chip 210, and the two ends of the conductive frame 220a are connected to the first pad 102 on the carrier chip 100 through the conductive material 30. In this way, when the current is transmitted between the MOSFET chip 210 and the circuit board 20, the current can be transmitted between the conductive frame 220a, the first pad 102 and the corresponding parts of the carrier chip 100 that are connected in sequence.

[0121] Among them, the conductive frame 220a may include a main board portion 221 and a side panel portion 222, the main board portion 221 corresponds to covering the second surface 210b of the MOSFET chip 210, the side panel portion 222 is connected to the opposite sides of the main board portion 221, the side panel portion 222 extends along the side wall surface of the MOSFET chip 210, one end of the side panel portion 222 is connected to the side of the main board portion 221, and the other end of the side panel portion 222 extends to be connected to the first solder pad 102 on the carrier chip 100. In this way, the conductive frame 220a forms a structure surrounding the second surface 210b and the side wall surface of the MOSFET chip 210, the main board portion 221 of the conductive frame 220a is used to connect with the second surface 210b of the MOSFET chip 210, and the side plate portion 222 of the conductive frame 220a is used to connect with the first solder pad 102 on the carrier chip 100. The input pad 211, the output pad 212 and the ground pad of the first surface 210a of the MOSFET chip 210 are connected to the corresponding conductive frame 220a through the corresponding first solder pad 102, thereby realizing the transmission of large current between the circuit board 20 and the MOSFET chip 210.

[0122] The conductive frame 220a is an independent structural member, and the MOSFET chip 210 can be mounted on the conductive frame 220a. For details, refer to Figure 8a or Figure 8b As shown, a glue layer 230 may be provided between the conductive frame 220a and the MOSFET chip 210, and the MOSFET chip 210 is connected to the conductive frame 220a through the glue layer 230. The glue layer 230 may only cover the second surface 210b of the MOSFET chip 210, or the glue layer 230 may also extend to cover the side wall surface of the MOSFET chip 210 to ensure that the MOSFET chip 210 is firmly connected to the conductive frame 220a. Exemplarily, the glue layer 230 may be formed of silver paste, sintered silver, CuSn or AuSn, etc.

[0123] When assembling the MOSFET component 200, a layer of glue 230 can be first coated on the inner wall surface of the conductive frame 220a, and then the MOSFET chip 210 is placed in the conductive frame 220a. The surface of the MOSFET chip 210 is connected and fixed to the glue layer 230 to mount the MOSFET chip 210 on the conductive frame 220a.

[0124] Exemplarily, the conductive frame 220a can be a copper frame or a copper alloy frame. As mentioned above, compared with the conductive material 30 connected between the first pad 102 of the carrier chip 100 and the second pad 23 of the circuit board 20, the electrical conductivity and thermal conductivity of copper and its alloys are much higher. Using a copper frame as the conductive frame 220a can not only achieve a high current-carrying capacity of the conductive member 220, but also efficiently conduct the heat generated by the MOSFET chip 210, thereby improving the performance of the MOSFET packaging structure 10.

[0125] As for the transmission of large current between the circuit board 20 and the carrier chip 100, Figure 8a The cross-sectional view of the region where the input pad 211 of the MOSFET chip 210 is located is shown as an example, as shown by the dotted arrow in the figure, combined with Figure 4 , the current on the circuit board 20 flows into the input pad 211 of the MOSFET chip 210 through the conductive frame 220a, wherein the current flows from the circuit board 20 through the main board portion 221 and the side board portion 222 of the conductive frame 220a in sequence, enters the input terminal pad 102a on the carrier chip 100, and then flows from the input terminal pad 102a to the input pad 211 of the MOSFET chip 210, so that a large current enters the MOSFET chip 210 from the circuit board 20. Figure 8b The cross-sectional view of the region where the output pad 212 of the MOSFET chip 210 is located is shown as an example, as shown by the dotted arrow in the figure, combined with Figure 4 The current on the MOSFET chip 210 flows from the output pad 212 through the conductive frame 220a into the circuit board 20, wherein the current flows from the output pad 212 of the MOSFET chip 210 to the output terminal pad 102b on the carrier chip 100, and then enters the conductive frame 220a from the output terminal pad 102b, and sequentially flows through the side plate portion 222 and the main board portion 221 of the conductive frame 220a, and flows out to the circuit board 20, thereby realizing that a large current flows from the output pad 212 of the MOSFET chip 210 to the circuit board 20.

[0126] Figure 9a for Figure 6 Another cross-sectional schematic diagram at the middle BB; Figure 9b for Figure 6 Another cross-sectional diagram at CC in the middle. Figure 9a or Figure 9bAs shown, as another embodiment, the input pad 211, the output pad 212 and the ground pad on the MOSFET chip 210 can all be located on the side where the second surface 210b is located, which is equivalent to the active surface of the MOSFET chip 210 being its second surface 210b, and the active surface and the conductive pad 213 used to transmit the drive signal are arranged on the opposite side. At this time, in order to enable the drive signal to be transmitted to the active surface, a through hole 210h can be arranged in the MOSFET chip 210, and the through hole 210h extends from the first surface 210a of the MOSFET chip 210 to the second surface 210b, and the two ends of the through hole 210h extend to the conductive pad 213 arranged on the first surface 210a and the electrode (for example, the gate, not shown in the figure) of the transistor (for example, the first transistor 210c or the second transistor 210d mentioned above) arranged on the side close to the second surface 210b, and the conductive material is filled in the through hole 210h to electrically connect the conductive pad 213 and the electrode through the conductive material, so that the drive signal of the carrier chip 100 can be transmitted to the electrode to turn on the transistor of the MOSFET chip 210.

[0127] In the case where the input pad 211, the output pad 212 and the ground pad are all arranged on the second surface 210b of the MOSFET chip 210, the three conductive members 220 mounted on the second surface 210b of the MOSFET chip 210 can respectively cover the input pad 211, the output pad 212 and the ground pad to achieve connection between the input pad 211, the output pad 212 and the ground pad and the corresponding conductive members 220.

[0128] Since the input pad 211, the output pad 212 and the ground pad are directly connected to the corresponding conductive member 220, it is not necessary to connect the input pad 211, the output pad 212 and the ground pad to each conductive member 220 by providing a corresponding first pad 102 on the mounting surface 101 of the carrier chip 100. Therefore, the conductive member 220 does not need to be designed as a frame structure that needs to extend to connect to the first pad 102 on the carrier chip 100. Figure 9a or Figure 9b As shown, at this time, the conductive member 220 can be a conductive layer 220b covering the second surface 210b of the MOSFET chip 210, and the conductive layer 220b is a metal layer. For example, the conductive layer 220b can be a copper layer or an aluminum layer to ensure that the conductive layer 220b has high electrical conductivity and thermal conductivity. The conductive layer 220b can not only realize the high current carrying capacity of the conductive member 220, but also can efficiently conduct the heat generated by the MOSFET chip 210, thereby improving the performance of the MOSFET packaging structure 10.

[0129] The conductive layer 220b can be directly deposited on the second surface 210b of the MOSFET chip 210 by chemical vapor deposition (CVD) or physical vapor deposition (PVD) and other processes, so no connection medium is required between the conductive layer 220b and the MOSFET chip 210. Alternatively, the conductive layer 220b can also be set as an independent conductive plate, such as a copper plate or an aluminum plate, and the conductive plate can be attached to the second surface 210b of the MOSFET chip 210 by the aforementioned adhesive layer 230, which is not limited in this embodiment.

[0130] In addition, since the input pad 211, the output pad 212 and the ground pad are directly connected to the corresponding conductive member 220, Figure 9a As shown, Figure 9a The cross-sectional view of the region where the input pad 211 of the MOSFET chip 210 is located is shown as an example, as shown by the dotted arrow in the figure, combined with Figure 4 , the current on the circuit board 20 flows directly into the input pad 211 through the conductive layer 220b, so that a large current enters the MOSFET chip 210 from the circuit board 20. Figure 9b As shown, Figure 9b The cross-sectional view of the region where the output pad 212 of the MOSFET chip 210 is located is shown as an example, as shown by the dotted arrow in the figure, combined with Figure 4 , the current is directly transmitted from the output pad 212 of the MOSFET chip 210 to the conductive layer 220 b, and then flows out to the circuit board 20 through the conductive layer 220 b, so that a large current flows out from the output pad 212 of the MOSFET chip 210 to the circuit board 20.

[0131] In some other embodiments, the input pad 211, the output pad 212 and the ground pad on the MOSFET chip 210 can also be arranged on different sides. In this case, the three conductive members 220 mounted on the MOSFET chip 210 can also have different structural forms, so as to facilitate connection with the corresponding input pad 211, the output pad 212 and the ground pad located at different positions. For example, the input pad 211 and the output pad 212 are arranged on the first surface 210a of the MOSFET chip 210, and the ground pad is arranged on the second surface 210b of the MOSFET chip 210. In this regard, the two conductive members 220 respectively connected to the input pad 211 and the output pad 212 can be set as a conductive frame 220a, and the conductive member 220 connected to the ground pad can be set as a conductive layer 220b, which will not be repeated.

[0132] This embodiment also provides a method for manufacturing a MOSFET package structure (hereinafter referred to as the manufacturing method), which is used to manufacture the above-mentioned MOSFET package structure 10. The MOSFET package structure 10 can be manufactured by wafer level chip packaging (Wafer Level Chip Scale Packaging, referred to as WLCSP), that is, the MOSFET component 200 assembled by the MOSFET chip 210 and the conductive member 220 can be packaged on a wafer having a plurality of carrier chips 100 arrayed thereon, and then the wafer is cut to form a single MOSFET package structure 10.

[0133] Fig.10 This is a flowchart of the steps of the method for manufacturing the MOSFET packaging structure provided in the embodiment of the present application. Fig.10 As shown, specifically, the production method comprises the following steps:

[0134] S100. Provide a plurality of MOSFET components.

[0135] Combination Figure 5 and Figure 6 As shown, first, a plurality of MOSFET components 200 to be packaged on a wafer are provided. As mentioned above, the MOSFET component 200 includes a MOSFET chip 210 and three conductive members 220. The conductive member 220 is mounted on the MOSFET chip 210. The three conductive members 220 are all attached to the second surface 210b of the MOSFET chip 210 and are spaced apart.

[0136] Among them, combined Figures 8a to 9b As shown, the MOSFET chip 210 has an input pad 211, an output pad 212 and a ground pad. The input pad 211, the output pad 212 and the ground pad can be located on the side where the first surface 210a of the MOSFET chip 210 is located, or can be located on the side where the second surface 210b of the MOSFET chip 210 is located. The three can be arranged on the same side or on different sides. For the positions where the input pad 211, the output pad 212 and the ground pad are located, the corresponding conductive member 220 can be set as a conductive frame 220a or a conductive layer 220b, which will not be repeated here.

[0137] Combination Figure 8a and Figure 8bAs shown, as an implementation method, in the case where the input pad 211, the output pad 212 and the ground pad are all located on the side where the first surface 210a of the MOSFET chip 210 is located, a conductive frame 220a can be provided as a conductive member 220, and the MOSFET chip 210 can be mounted on the conductive frame 220a. At this time, an integrated structure having multiple conductive frames 220a can be formed first, and after multiple MOSFET chips 210 are mounted one by one on each conductive frame 220a, the integrated structure can be cut to form a single MOSFET component 200. In this way, multiple MOSFET components 200 can be formed at the same time, and the MOSFET components 200 can be mass-produced, thereby improving the production efficiency of the MOSFET components 200.

[0138] Fig.11 A schematic diagram of manufacturing a MOSFET component provided in an embodiment of the present application. Fig.11 As shown, the conductive frame 220a is used as the conductive member 220 to simultaneously form a plurality of MOSFET components 200, specifically:

[0139] Reference Fig.11 As shown in (a), a conductive plate 2201 is first provided, referring to Fig.11 As shown in (b), the conductive plate 2201 is then processed to form a plurality of interconnected conductive frames 220a. The figure shows that the conductive plate 2201 is processed into a plurality of interconnected conductive frames 220a by an etching process, specifically, a mask plate 2202 is covered on the conductive plate 2201, the mask plate 2202 has a mask pattern, the conductive plate 2201 is etched according to the mask pattern, and the mask pattern is transferred to the conductive plate 2201 to form a plurality of interconnected conductive frames 220a. In practical applications, the conductive plate 2201 can also be processed into a plurality of interconnected conductive frames 220a by other processes, for example, the conductive plate 2201 can be stamped into a plurality of interconnected conductive frames 220a by a stamping process.

[0140] Reference Fig.11As shown in (c), after forming a plurality of interconnected conductive frames 220a, a layer of glue layer 230 can be coated on the inner wall surface of each conductive frame 220a. As mentioned above, the conductive frame 220a includes a main board portion 221 and a side plate portion 222, one end of the side plate portion 222 is connected to the side of the main board portion 221, and the other end of the side plate portion 222 extends toward one side of the main board portion 221. The inner wall surface of the conductive frame 220a is a side surface of the main board portion 221 facing the side plate portion 222 and a wall surface of the side plate portion 222 connected to the side surface of the main board portion 221. Then, each MOSFET chip 210 is placed in each conductive frame 220a, that is, the MOSFET chip 210 is placed in the area surrounded by the main board portion 221 and the side plate portion 222 of the conductive frame 220a, and the MOSFET chip 210 and the conductive frame 220a are pressed together, so that each MOSFET chip 210 is firmly attached to each conductive frame 220a.

[0141] Reference Fig.11 As shown in (d), after each MOSFET chip 210 is mounted on each conductive frame 220a connected to each other, the conductive plate 2201 is cut, specifically, the connection parts between each conductive frame 220a are cut to form a plurality of independent MOSFET components 200.

[0142] It is understood that after the conductive plate 2201 forms a plurality of interconnected conductive frames 220a, the conductive frames 220a corresponding to each MOSFET chip 210 are three conductive frames 220a arranged at intervals, and the three conductive frames 220a are connected together. When the conductive plate 2201 is cut, in addition to separating the conductive frames 220a corresponding to different MOSFET chips 210 from each other, the three conductive frames 220a of each MOSFET chip 210 are also separated from each other.

[0143] Combination Figure 9a and Figure 9b As shown, as another embodiment, in the case where the input pad 211, the output pad 212 and the ground pad are all located on the side where the second surface 210b of the MOSFET chip 210 is located, a conductive layer 220b can be deposited on the second surface 210b of the MOSFET chip 210 as the conductive member 220. In this case, the conductive layer 220b can be deposited on the second surface 210b of each MOSFET chip 210 first, and then each MOSFET chip 210 is mounted on each carrier chip 100 of the wafer; or, all MOSFET chips 210 can be mounted on the wafer first, and then the conductive layer 220b can be deposited on the second surface 210b of each MOSFET chip 210.

[0144] In the following, the subsequent manufacturing process of the MOSFET package structure 10 is described by taking the conductive member 220 as the conductive frame 220 a.

[0145] S200, providing a wafer, wherein the wafer includes a plurality of chip bodies arranged in an array.

[0146] After forming a plurality of MOSFET components 200, a wafer is provided as the chip body 110 of the carrier chip 100. The wafer can be divided into a plurality of regions in an array, and each region corresponds to a chip body 110 of the carrier chip 100. The chip body 110 has a conductive structure disposed therein.

[0147] S300 , forming a dielectric layer and a wiring layer on one surface of the wafer.

[0148] Afterwards, a dielectric layer 120 and a wiring layer 130 are formed on one side surface of the wafer to provide a fixing foundation for the MOSFET chip 210 and realize the connection between the MOSFET chip 210 and the conductive structure in the chip body 110. The wafer is used as the chip body 110 of the carrier chip 100, and together with the dielectric layer 120 and the wiring layer 130, the carrier chip 100 is formed. After the dielectric layer 120 and the wiring layer 130 are formed on the wafer, the wafer is cut to form each independent carrier chip 100.

[0149] In this embodiment, after the dielectric layer 120 and the wiring layer 130 are formed on the wafer, the MOSFET component 200 can be packaged on the wafer first, and then the wafer is cut to form multiple single MOSFET package structures 10. In this way, wafer-level chip packaging is realized. Different from the traditional chip packaging method of cutting first and then packaging, the area after packaging is at least increased by 20% of the bare die (single carrier chip 100). Since the wafer-level chip packaging completes packaging and testing on the whole wafer, and then cuts to form a single MOSFET package structure 10, the area after packaging is the same as that of the bare die, and the miniaturization of the MOSFET package structure 10 can be achieved.

[0150] Among them, the formed dielectric layer 120 covers the surface of the wafer, the wiring layer 130 is located in the dielectric layer 120, the wiring layer 130 has a plurality of conductive wires 131, the side of the conductive wires 131 facing the wafer is electrically connected to the wafer, and the surface of the side of the conductive wires 131 facing away from the wafer has an exposed area, and the exposed area is exposed outside the dielectric layer 120. The exposed area is used to form the aforementioned first solder pad 102, so as to realize the connection between the carrier chip 100 and the MOSFET chip 210 and the circuit board 20 through the first solder pad 102.

[0151] Fig.12 A schematic diagram of forming a dielectric layer and a wiring layer on a wafer provided in an embodiment of the present application. Fig.12 As shown, a dielectric layer 120 and a wiring layer 130 are formed on the surface of the wafer, specifically including:

[0152] Reference Fig.12 As shown in (a), an insulating first dielectric layer 121 is first formed on the surface of the wafer, and a via 1211 is provided in the first dielectric layer 121. The via 1211 penetrates the thickness direction of the first dielectric layer 121 to expose a local area of ​​the surface of the wafer outside the first dielectric layer 121. Exemplarily, a first dielectric layer 121 can be first deposited on the surface of the wafer, and then the via 1211 is etched in the first dielectric layer 121. The first dielectric layer 121 is, for example, a silicon oxide layer or a silicon nitride layer.

[0153] Reference Fig.12 As shown in (b), after forming the first dielectric layer 121 on the surface of the wafer, a wiring layer 130 is laid on the first dielectric layer 121. The conductive wires 131 in the wiring layer 130 are spaced apart and electrically isolated from each other. The portion of the conductive wire 131 corresponding to the via hole 1211 extends into the via hole 1211, passes through the via hole 1211 and contacts the surface of the wafer to achieve electrical connection between the conductive wire 131 and the wafer. Exemplarily, a whole metal layer can be deposited on the surface of the first dielectric layer 121 first, and then the metal layer is etched to form a plurality of conductive wires 131 isolated from each other.

[0154] Reference Fig.12 As shown in (c), after forming the wiring layer 130, an insulating second dielectric layer 122 is formed on the wafer, and the second dielectric layer 122 is formed on the first dielectric layer 121, and the second dielectric layer 122 covers the wiring layer 130 to protect the wiring layer 130. In addition, the second dielectric layer 122 has an opening 1221, and a local area of ​​the conductive line 131 in the wiring layer 130 is exposed in the opening 1221, and the exposed area of ​​the conductive line 131 is used to form the first pad 102. Exemplarily, a second dielectric layer 122 can be first deposited on the first dielectric layer 121, and the second dielectric layer 122 covers the wiring layer 130. After that, the second dielectric layer 122 is etched to form an opening 1221 in the second dielectric layer 122, and the second dielectric layer 122 is, for example, a silicon oxide layer or a silicon nitride layer.

[0155] S400, mounting a MOSFET component on a wafer, and connecting a first surface of the MOSFET chip to a first pad via a conductive material.

[0156] Fig.13 This is a schematic diagram of forming a MOSFET packaging structure provided by an embodiment of the present application. Fig.13As shown in (a), after laying the dielectric layer 120 and the wiring layer 130 on the wafer, the assembled MOSFET component 200 is packaged on the wafer, and the conductive material 30 can be firstly provided on the first pad 102 in the mounting area 101a of each carrier chip 100 of the wafer, and then the MOSFET component 200 is mounted on the first pad 102 in the mounting area 101a. The first surface 210a of the MOSFET chip 210 faces the carrier chip 100 and is attached to the first pad 102 in the mounting area 101a of the carrier chip 100.

[0157] Specifically, each conductive pad 213 on the first surface 210a of the MOSFET chip 210 is connected to the corresponding first pads 102 through the conductive material 30. When the input pad 211, the output pad 212 and the ground pad of the MOSFET chip 210 are all arranged on the side where the first surface 210a is located, the mounting area 101a of the carrier chip 100 is provided with an input terminal pad 102a, an output terminal pad 102b and a ground terminal pad corresponding to the input pad 211, the output pad 212 and the ground pad, respectively. Each conductive frame 220a mounted on the MOSFET chip 210 is connected to the corresponding input terminal pad 102a, the output terminal pad 102b and the ground terminal pad, respectively, through the conductive material 30.

[0158] Reference Fig.13 As shown in (b), in order to realize the connection between the MOSFET package structure 10 and the circuit board 20, after the MOSFET component 200 is mounted on the wafer and before the wafer is cut, a conductive material 30 can be set on the first pad 102 of each carrier chip 100 on the wafer. For example, a solder ball 30a can be printed on the first pad 102 as the conductive material 30. In this way, after the wafer is cut, the MOSFET package structure 10 can be directly mounted on the circuit board 20, and the MOSFET package structure 10 and the circuit board 20 are connected through the conductive material 30.

[0159] Alternatively, in other embodiments, the conductive material 30 may also be pre-set on the circuit board 20 , for example, solder balls 30 a may be pre-printed on each second solder pad 23 of the circuit board 20 , and after wafer cutting, the formed MOSFET package structure 10 may be mounted on the circuit board 20 .

[0160] S500, cutting the wafer to form a single MOSFET packaging structure.

[0161] After the MOSFET component 200 is mounted on the wafer, the wafer is cut and the corresponding carrier chips 100 on the wafer are separated. After separation, each carrier chip 100 and the MOSFET component 200 mounted thereon form a single MOSFET package structure 10. In this way, the volume of the MOSFET package structure 10 is reduced through the wafer-level chip packaging method, which is conducive to the miniaturization of the MOSFET package structure 10, and the packaging process steps are simplified, the packaging cost is reduced, and the packaging efficiency is improved.

[0162] In the description of the embodiments of the present application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, or it can be an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the embodiments of the present application can be understood according to specific circumstances.

[0163] The terms "first", "second", "third", "fourth", etc. (if any) in the description and claims of the embodiments of the present application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

Claims

1. A MOSFET packaging structure, characterized in that: It includes a carrier chip, a MOSFET chip and three conductive parts, wherein the carrier chip is used to drive the MOSFET chip to conduct and provide a charging current for the MOSFET chip; One side surface of the carrier chip is a mounting surface, a plurality of first pads are distributed on the mounting surface, the mounting surface has a mounting area, a plurality of first pads are arranged in the mounting area, the MOSFET chip has a first surface and a second surface opposite to each other, the first surface is mounted in the mounting area and connected to the first pads in the mounting area, the three conductive members are all mounted on the second surface and are arranged at intervals, and the conductive members are configured to face the circuit board and be connected to the circuit board; Wherein, the MOSFET chip comprises an input pad, an output pad and a ground pad, and the three conductive members are electrically connected to the input pad, the output pad and the ground pad respectively.

2. The MOSFET packaging structure according to claim 1, characterized in that: The input pad, the output pad and the ground pad are all located on the side where the first surface is located, the first pad in the mounting area includes an input terminal pad, an output terminal pad and a ground terminal pad, the input pad is connected to the input terminal pad accordingly, the output pad is connected to the output terminal pad accordingly, and the ground pad is connected to the ground terminal pad accordingly.

3. The MOSFET packaging structure according to claim 2, characterized in that: The conductive member is a conductive frame, and the conductive frame includes a main board portion and a side board portion, wherein the main board portion covers the second surface, one end of the side board portion is connected to the side edge of the main board portion, and the other end of the side board portion extends toward the carrier chip; The side plates of the three conductive frames are respectively connected to the input pad, the output pad and the ground pad.

4. The MOSFET packaging structure according to claim 3, characterized in that: An adhesive layer is arranged between the conductive frame and the MOSFET chip.

5. The MOSFET packaging structure according to claim 3 or 4, characterized in that: The conductive frame includes a copper frame or a copper alloy frame.

6. The MOSFET packaging structure according to claim 1, characterized in that: The input pad, the output pad and the ground pad are all located on the side where the second surface is located, and the three conductive members cover the input pad, the output pad and the ground pad respectively.

7. The MOSFET packaging structure according to claim 6, characterized in that: The conductive element is a conductive layer covering the second surface.

8. The MOSFET packaging structure according to claim 7, characterized in that: The conductive layer includes a copper layer or an aluminum layer.

9. The MOSFET packaging structure according to any one of claims 1-4, 6-8, characterized in that: A plurality of conductive pads are distributed on the first surface, and the conductive pads are connected to the first pads in the mounting area in a one-to-one correspondence.

10. The MOSFET packaging structure according to any one of claims 1-4, 6-8, characterized in that: The MOSFET chip is a GaN MOSFET.

11. The MOSFET packaging structure according to any one of claims 1-4 and 6-8, characterized in that: The carrier chip comprises a chip body, a dielectric layer and a wiring layer; The dielectric layer covers the chip body, the wiring layer is arranged in the dielectric layer, and the side of the wiring layer facing the chip body is connected to the conductive structure in the chip body, and the surface of the wiring layer facing away from the chip body has an exposed area exposed outside the dielectric layer, and the first pad corresponds to the exposed area.

12. The MOSFET packaging structure according to claim 11, characterized in that: The dielectric layer comprises a first dielectric layer and a second dielectric layer sequentially stacked on the chip body, and the wiring layer is arranged between the first dielectric layer and the second dielectric layer; The first dielectric layer is provided with a via hole, and the wiring layer is connected to the conductive structure through the via hole; the second dielectric layer has an opening, and the exposed area is exposed in the opening.

13. A method for manufacturing a MOSFET packaging structure, characterized in that: The MOSFET packaging structure according to any one of claims 1 to 12 comprises: A plurality of MOSFET components are provided; the MOSFET components include a MOSFET chip and three conductive members, the MOSFET chip has a first surface and a second surface opposite to each other, and the three conductive members are mounted on the second surface and arranged at intervals; wherein the MOSFET chip includes an input pad, an output pad and a ground pad, and the three conductive members are electrically connected to the input pad, the output pad and the ground pad respectively; Providing a wafer, wherein the wafer includes a plurality of chip bodies arranged in an array; A dielectric layer and a wiring layer are formed on one side surface of the wafer; the dielectric layer covers the wafer, the wiring layer is arranged in the dielectric layer, and the side of the wiring layer facing the wafer is connected to the conductive structure in the chip body, and the side surface of the wiring layer facing away from the wafer has an exposed area exposed outside the dielectric layer, and the exposed area is correspondingly formed with a first pad; Mounting the MOSFET component on the wafer, wherein the first surface of the MOSFET chip is connected to the first pad via a conductive material; The wafer is cut to form a single MOSFET package structure.

14. The method for manufacturing a MOSFET package structure according to claim 13, characterized in that: The input pad, the output pad and the ground pad are all located on the side where the first surface is located, and providing the MOSFET component includes: A conductive frame is provided as a conductive member; the conductive frame comprises a main board portion and a side board portion, one end of the side board portion is connected to a side edge of the main board portion, and the other end of the side board portion extends toward one side of the main board portion; The MOSFET chip is connected to the conductive frame, and the MOSFET chip is located in the area surrounded by the main board part and the side board part.

15. The method for manufacturing a MOSFET package structure according to claim 14, characterized in that: The invention provides a plurality of MOSFET components, including: Providing a conductive plate; Processing the conductive plate to form a plurality of conductive frames connected to each other; Connecting each of the MOSFET chips to each of the conductive frames accordingly; The conductive plate is cut to form a plurality of MOSFET components.

16. The method for manufacturing a MOSFET package structure according to claim 15, characterized in that: The processing of the conductive plate comprises: The conductive plate is formed into a plurality of conductive frames connected to each other by adopting a photolithography process or a stamping process.

17. The method for manufacturing a MOSFET package structure according to claim 13, characterized in that: The input pad, the output pad and the ground pad are all located on the side where the second surface is located, and providing the MOSFET component includes: Providing the MOSFET chip; A conductive layer is formed on the second surface of the MOSFET chip, the conductive layer serving as a conductive member, and the three conductive layers respectively cover the input pad, the output pad and the ground pad.

18. The method for manufacturing a MOSFET package structure according to any one of claims 13 to 17, characterized in that: The step of forming a dielectric layer and a wiring layer on a surface of one side of the wafer comprises: forming a first dielectric layer having via holes on a surface of one side of the wafer; Laying a wiring layer on the first dielectric layer, wherein the wiring layer passes through the via hole and is connected to the conductive structure; A second dielectric layer having an opening is formed on the first dielectric layer, wherein the second dielectric layer covers the wiring layer, and the exposed area is exposed in the opening.

19. A circuit board assembly, characterized in that: It comprises a circuit board and the MOSFET packaging structure according to any one of claims 1 to 12, wherein a plurality of second pads are distributed on the circuit board, and the MOSFET packaging structure is connected to the second pads via a conductive material.

20. An electronic device, characterized in that: The invention comprises a housing and the circuit board assembly according to claim 19, wherein the circuit board assembly is arranged in the housing.

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