A high-reliability FPGA based on memristor to implement check rollback

Abstract

The present application discloses a high-reliability FPGA for implementing check rollback based on a memristor, and relates to the field of FPGA technology. The non-volatile sequential element inside the high-reliability FPGA has a built-in memristor based on a variable resistance value. The memristor is used as a functional element on the one hand, and is used to store information on the other hand. The check rollback controller controls each non-volatile sequential element to update and store the working state when there is no fault using the resistance state of the built-in memristor, and restores to the most recent working state when a fault occurs using the resistance state of the built-in memristor, driving the high-reliability FPGA to restore to the most recent fault-free operating state, thereby realizing the functions of non-volatile state preservation and state recovery, improving reliability and stability, and this approach is compatible with existing CMOS processes, can improve the scale and speed of FPGA, and can be well applied in large data volume processing scenarios.

Description

Technical Field

[0001] The present application relates to the field of FPGA technology, and in particular to a high-reliability FPGA based on a memristor to implement check rollback. Background Art

[0002] FPGA (Field Programmable Gate Array) is a hardware programmable logic device that is widely used in systems in various fields. With the continuous advancement of technology, modern society has higher and higher requirements for the reliability of various systems, especially in fields such as aerospace, medical equipment, energy, transportation, and financial systems that require high stability. However, for the current mainstream SRAM-based FPGA, information will be lost when the system fails, affecting the reliability and stability of the system. Summary of the invention

[0003] In view of the above problems and technical requirements, this application proposes a high-reliability FPGA based on a memristor to implement check rollback. The technical solution of this application is as follows:

[0004] A high-reliability FPGA for implementing check rollback based on a memristor, wherein the high-reliability FPGA includes at least one non-volatile sequential element formed by a memristor with a variable resistance value, and also includes a check rollback controller; during the operation of the high-reliability FPGA:

[0005] When the current operating state of the high-reliability FPGA is fault-free, the check rollback controller controls each non-volatile sequential element to update and store the current working state of the non-volatile sequential element using the resistance state of the built-in memristor;

[0006] When a fault occurs in the current operating state of the high-reliability FPGA, the check rollback controller controls each non-volatile sequential element to recover to the most recent working state of the non-volatile sequential element by using the resistance state of the built-in memristor, thereby driving the high-reliability FPGA to recover to the most recent fault-free operating state.

[0007] Its further technical solution is that during the operation of the high-reliability FPGA, when it is determined that the current operating state of the high-reliability FPGA is fault-free, the check rollback controller controls each non-volatile timing element according to a predetermined check frequency to use the resistance state of the built-in memristor to update the current working state of the non-volatile timing element.

[0008] A further technical solution is that the inspection frequency used by the check rollback controller is dynamically variable during the operation of the high-reliability FPGA, and the inspection frequency is related to at least one of the operating state, operating environment and reliability requirements of the high-reliability FPGA.

[0009] The further technical solution is that during the operation of the high-reliability FPGA:

[0010] Temporarily increase the inspection frequency within a predetermined period after determining that the operating state of the high-reliability FPGA has a fault, and restore the inspection frequency after determining that the operating state of the high-reliability FPGA has been fault-free for a predetermined period of time;

[0011] and / or, when it is determined that the operating environment of the high reliability FPGA has become severe, increasing the inspection frequency;

[0012] And / or, when it is determined that the reliability requirement of the high-reliability FPGA becomes higher, the inspection frequency is increased.

[0013] The further technical solution is that during the operation of the high-reliability FPGA:

[0014] Suspend the user function executed by the high-reliability FPGA, and perform a fault test on the current running state of the high-reliability FPGA. After the fault test is completed, resume the execution of the user function, and check whether the rollback controller determines whether there is a fault in the current running state of the high-reliability FPGA according to the fault test result.

[0015] While the high-reliability FPGA is executing user functions, a fault test is performed on the current running state of the high-reliability FPGA in parallel, and a rollback controller is checked to determine whether there is a fault in the current running state of the high-reliability FPGA based on the fault test result.

[0016] A further technical solution thereof is to check that the rollback controller is connected through a control line network and controls the resistance state of the memristor built into each non-volatile sequential element;

[0017] When each non-volatile sequential element in the control line network shares the same control line with the check rollback controller, the check rollback controller simultaneously reads the resistance state of the memristor built into each non-volatile sequential element, and the check rollback controller simultaneously configures the resistance state of the memristor built into each non-volatile sequential element;

[0018] When there are at least two non-volatile timing elements in the control line network and the control lines between the check rollback controller are independent of each other, the control line network forms a hierarchical structure, and the check rollback controller reads the resistance state of the memristor built into each non-volatile timing element in sequence according to the hierarchical order, and the check rollback controller configures the resistance state of the memristor built into each non-volatile timing element in sequence according to the hierarchical order.

[0019] A further technical solution is that the total inspection time and the total rollback time of the check rollback controller are both related to the structure of the control line network, and the total inspection time and the total rollback time are adjustable;

[0020] The total time consumption of the check is the time consumption of checking the rollback controller to control all non-volatile sequential elements to complete the update and storage of the current working state;

[0021] The total rollback time is the time taken by the rollback controller to control all non-volatile sequential elements to complete the recovery to the most recent working state.

[0022] Its further technical solution is to check that the rollback controller and the control line network are both implemented using the programmable resources built into the high-reliability FPGA; and in the design process of the high-reliability FPGA, the circuit structure of the control line network formed using the programmable resources matches the circuit design requirements.

[0023] Its further technical solution is that the circuit design requirements include at least one of the wiring area of ​​the control line network, the total inspection time of the rollback controller, the total rollback time of the rollback controller, the maximum instantaneous current of the rollback controller reading the resistance state of the built-in memristor of each non-volatile timing element, and the maximum instantaneous current of the rollback controller configuring the resistance state of the built-in memristor of each non-volatile timing element.

[0024] A further technical solution is that the non-volatile sequential elements included in the high-reliability FPGA include a non-volatile DFF, a non-volatile BRAM and a sequential element providing configuration bits, the sequential element providing configuration bits includes a non-volatile distributed random access memory and a non-volatile shift register, and the non-volatile BRAM, the non-volatile distributed random access memory and the non-volatile shift register are respectively constructed based on the non-volatile DFF;

[0025] For the non-volatile DFF, check that the rollback controller controls the data save signal SET of the non-volatile DFF to be in a valid level state, and apply a programming voltage PHV at the end of the memristor to control the non-volatile DFF to store the current working state of the output end of the non-volatile DFF using the resistance state of the built-in memristor; check that the rollback controller controls the data recovery signal RES of the non-volatile DFF to be in a valid level state and the set signal is in an invalid level state, so as to restore the resistance state of the built-in memristor of the non-volatile DFF to the most recent operating state of the non-volatile DFF.

[0026] The beneficial technical effects of this application are:

[0027] The present application discloses a high-reliability FPGA based on memristors to implement check rollback. The high-reliability FPGA optimizes the hardware circuit structure and software workflow, upgrades the timing element to a non-volatile timing element based on a memristor with a variable resistance value, and adds a check rollback controller inside the FPGA to control each non-volatile timing element. The built-in memristor of the non-volatile timing element is used as a functional element on the one hand, and is used to store information on the other hand. The working state of each non-volatile timing element is directly stored in the built-in memristor, stored as the resistance state of the memristor, so that the functions of non-volatile state preservation and state recovery can be realized, and this approach is compatible with existing CMOS processes, can improve the scale and speed of FPGA, ensure the reliability and operation stability of the high-reliability FPGA, and can be well applied in large data processing scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is a structural diagram of the non-volatile DFF in the high-reliability FPGA of the present application.

[0029] Figure 2 It is a flowchart of a method for checking the execution of a rollback controller in one embodiment of the present application.

[0030] Figure 3 The circuit structure of checking the control line network between the rollback controller and two non-volatile DFFs in one example. DETAILED DESCRIPTION

[0031] The specific implementation of the present application is further described below in conjunction with the accompanying drawings.

[0032] The present application discloses a high-reliability FPGA that implements check rollback based on a memristor. The high-reliability FPGA has a check rollback mechanism. The check rollback mechanism can record a specific working state during the operation of the high-reliability FPGA. Then, when a failure occurs during the operation of a transaction, the previously made changes or transactions can be undone or rolled back, and the operation can be restored to the previously recorded working state to continue, so that rapid recovery can be achieved in the event of a failure, thereby achieving high-reliability operation.

[0033] Currently, commonly used FPGAs are implemented using volatile SRAM (Static Random-Access Memory). SRAM-type FPGAs can record the working status in the SRAM, but when the FPGA fails, the information stored in the SRAM will be lost. Therefore, SRAM-type FPGAs cannot actually implement check rollback. When a failure occurs, they can only be restored to the original working state when the power is just turned on and restarted. As a result, the recovery time of SRAM-type FPGAs after a failure is very long, affecting the operating stability and reliability.

[0034] Some FPGAs are currently implemented using Flash technology. Flash-based FPGAs can record the working status in Flash. The information stored in Flash will not be lost when the FPGA fails. Therefore, Flash-based FPGAs can be restored to the most recently saved working status and continue to run, without having to restore to the original working status when it was just powered on like SRAM-based FPGAs. Therefore, in theory, Flash-based FPGAs can implement check rollback. However, FPGAs based on Flash technology are difficult to be compatible with the most advanced CMOS processes available, which limits the scale and speed of Flash-based FPGAs. The speed of accessing and reading information in Flash is too slow, and the memory space depends on the size of Flash memory, and the storage space is limited. This makes it difficult for Flash-based FPGAs to meet the requirements of large data processing capabilities, and it is also difficult to apply to the current large-scale FPGA scenarios.

[0035] From the above introduction, it can be seen that the two existing mainstream FPGAs cannot implement check rollback well, which is an important reason affecting the operational reliability. Therefore, the high-reliability FPGA of the present application improves reliability by optimizing the check rollback mechanism. In order to achieve this goal, a combination of software and hardware is required. Therefore, compared with traditional FPGAs, the high-reliability FPGA of the present application has made improvements to the hardware structure and software methods.

[0036] Compared with traditional FPGAs, the improvements of the internal circuit structure of the high-reliability FPGA in this application mainly include the following two parts:

[0037] (1) The hardware structure of the timing elements in traditional FPGAs has been improved and optimized.

[0038] Sequential elements are elements used to store information inside FPGA. The operating state of FPGA is determined by the value of sequential elements inside FPGA. Therefore, by saving the value of sequential elements inside FPGA, the working state of FPGA can be recorded. Sequential elements inside FPGA include DFF (D-type flip-flop), BRAM (Block RAM, block random access memory) and sequential elements that provide configuration bits. Sequential elements that provide configuration bits include distributed random access memory (Distributed Random Access Memory, DRAM) and shift registers.

[0039] In order to avoid the volatility disadvantage of SRAM-type FPGAs and to overcome the disadvantage that Flash-type FPGAs are difficult to be compatible with CMOS processes, this application adopts an approach that is different from SRAM-type FPGAs and Flash-type FPGAs: the circuit structure of at least one timing element in a traditional FPGA is improved and upgraded, and replaced with a corresponding non-volatile timing element formed by a variable resistance memristor. In order to completely preserve the operating state of the high-reliability FPGA, in actual application, all timing elements inside the high-reliability FPGA are non-volatile timing elements formed by a variable resistance memristor, so that the values ​​of all timing elements inside the high-reliability FPGA can be preserved.

[0040] Therefore, all the sequential elements inside the high-reliability FPGA are non-volatile sequential elements, and the non-volatile sequential elements include non-volatile DFF, non-volatile BRAM and non-volatile sequential elements providing configuration bits. The non-volatile sequential elements providing configuration bits include non-volatile distributed random access memory and non-volatile shift register.

[0041] BRAM is implemented through a combination of registers and latches, and the non-volatile sequential elements that provide configuration bits are also implemented through registers, latches, and devices with RAM functions. Therefore, it can be considered that non-volatile BRAM, non-volatile distributed random access memory, and non-volatile shift registers are constructed based on non-volatile DFFs. Therefore, after the non-volatile DFF is formed based on the variable resistance memristor, the non-volatile BRAM and the non-volatile sequential element that provides configuration bits can be further constructed according to the standard circuit structure.

[0042] The structure of the nonvolatile DFF in this application is as follows Figure 1As shown, the non-volatile DFF (Re_DFF) includes a data input port DATA, a data output terminal Q, a clock port CK, a set signal terminal SEB, a shaping signal terminal FOM, a data storage signal terminal SET, a data recovery signal terminal RES, and a variable resistance reset signal terminal RET. The specific structure and working principle of the non-volatile DFF can refer to the relevant contents of the non-volatile DFF for FPGA based on variable resistance resistors previously applied by the applicant, and this embodiment will not be repeated.

[0043] (2) A check rollback controller is added inside the high-reliability FPGA. The check rollback controller is used to control the check rollback process.

[0044] Based on the above improvements to the hardware circuit structure, the high-reliability FPGA of the present application also improves the working process compared to the traditional FPGA. During the operation of the high-reliability FPGA of the present application:

[0045] When the current operating state of the high-reliability FPGA is fault-free, the check rollback controller controls each non-volatile timing element to update and store the current fault-free working state of the non-volatile timing element using the resistance state of the built-in memristor, thereby using the resistance state of the built-in memristor of each non-volatile timing element to store the current fault-free operating state of the high-reliability FPGA.

[0046] When there is a fault in the current operating state of the high-reliability FPGA, the check rollback controller controls each non-volatile timing element to use the resistance state of the built-in memristor to restore to the most recent working state of the non-volatile timing element, thereby driving the high-reliability FPGA to recover to the most recent stored fault-free operating state.

[0047] In one embodiment, there are two main methods for detecting whether there is a fault in the current running state of the high-reliability FPGA during operation: (1) suspending the user function executed by the high-reliability FPGA, and performing a fault test on the current running state of the high-reliability FPGA. After completing the fault test, the user function is resumed, and the rollback controller is checked to determine whether there is a fault in the current running state of the high-reliability FPGA based on the fault test result. (2) while the high-reliability FPGA is executing the user function, the current running state of the high-reliability FPGA is fault tested in parallel, and the rollback controller is checked to determine whether there is a fault in the current running state of the high-reliability FPGA based on the fault test result. Regardless of which method is used, the fault test on the current running state of the high-reliability FPGA can be completed by checking the rollback controller or other components inside the high-reliability FPGA or a higher-level system.

[0048] That is, in the high-reliability FPGA of the present application, the built-in memristor of the non-volatile sequential element is used as a functional element on the one hand, and is used to store information on the other hand. The working state of each non-volatile sequential element is directly stored in the built-in memristor, and is stored as the resistance state of the memristor. The resistance state is controlled by the control voltage of the memristor, that is, the configuration information and working state of the non-volatile sequential element can be converted with the control voltage of its built-in memristor to realize the functions of state preservation and state recovery. Since the resistance state of the built-in memristor of the non-volatile sequential element is non-volatile, information loss is avoided, and the shortcomings of SRAM-type FPGA are overcome. In addition, this approach is compatible with existing CMOS processes, and can also improve the scale and speed of FPGA, overcome the shortcomings of Flash-type FPGA, so that the high-reliability FPGA will not lose information after an error or an emergency failure occurs, and can quickly recover to the state before the failure occurs, realizing the high reliability and high stability of the FPGA system. In addition, the check rollback controller may also have a built-in register, which is used to dynamically maintain system status information. The system status information indicates the information of the most recent fault-free operating status currently stored, so that in the process of updating the storage and restoring the operating status, it can be clearly determined to which system state the storage and restoration are to be performed.

[0049] When implementing the above functions, the check rollback controller stores and restores the working state of the non-volatile sequential elements by controlling the control voltage of the built-in memristor of each non-volatile sequential element. The control process of the check rollback controller on the control voltage of the built-in memristor of the non-volatile DFF is as follows:

[0050] During the inspection phase, the inspection rollback controller controls the data saving signal SET of the non-volatile DFF to be in a valid level state, and applies a programming voltage PHV to the end of the memristor to control the non-volatile DFF to use the resistance state of the built-in memristor to store the current working state of the output end of the non-volatile DFF, thereby updating the current working state of the non-volatile DFF.

[0051] In the rollback phase, the rollback controller controls the data recovery signal RES of the nonvolatile DFF to be configured in a valid level state and the set signal is in an invalid level state, and the resistance state of the memristor built into the nonvolatile DFF is restored to the most recent operating state of the nonvolatile DFF.

[0052] The more detailed control process of the non-volatile DFF in this embodiment will not be described in detail. In addition, since other non-volatile sequential elements are constructed based on the non-volatile DFF, the same method is used to control the non-volatile DFF that constructs other non-volatile sequential elements, so that the memristor of other non-volatile sequential elements can be controlled, and this embodiment will not be described one by one.

[0053] On the basis of using non-volatile sequential elements to realize the above functions, since the operation state of the high-reliability FPGA is restored to the most recent fault-free operation state stored when a fault occurs, when the most recent fault-free operation state stored is an operation state long ago, after a fault occurs, it is necessary to roll back to the operation state long ago to continue to operate, which will affect the recovery time after the fault occurs and reduce reliability. Therefore, in one embodiment, during the operation of the high-reliability FPGA, when it is determined that the current operation state of the high-reliability FPGA is fault-free, the check rollback controller controls each non-volatile sequential element to update and store the current working state of the non-volatile sequential element using the resistance state of the built-in memristor according to a predetermined check frequency, that is, regularly storing the fault-free operation state, then by reasonably configuring the check frequency, it can be ensured that the difference between the operation state rolled back after the FPGA fails and the operation state when the fault occurs will not be too large, so that the recovery time after the fault occurs can be controlled within a reasonable range.

[0054] Increasing the inspection frequency can shorten the recovery time after a fault occurs, but the increase in inspection frequency will also bring other problems: when the method of suspending user functions to perform fault tests on the current operating state of the high-reliability FPGA is adopted, a higher inspection frequency means that the user function needs to be suspended more frequently and fault tests need to be performed, which will affect the execution time of the user function of the high-reliability FPGA and reduce the execution speed and performance of the chip. When the method of performing fault tests on the current operating state of the high-reliability FPGA in parallel with the execution of user functions is adopted, since the fault test will introduce additional power consumption and computing power requirements, the higher inspection frequency also brings greater power consumption burden and computing burden. Therefore, no matter which fault testing method is adopted, a higher inspection frequency will bring corresponding negative effects. Therefore, when determining the inspection frequency, it is necessary to comprehensively consider the positive impact of the inspection frequency on shortening the recovery time and the negative impact it brings, and select the appropriate inspection frequency.

[0055] Based on this consideration, one approach is to set a suitable check frequency based on pre-debugging and experience so that the overall effect is ideal enough. Or another approach is to dynamically change the check frequency used by the check rollback controller during the operation of the high-reliability FPGA. Please refer to Figure 2The flowchart shown in the figure is shown in the figure, and the inspection frequency is related to at least one of the operating state, operating environment and reliability requirements of the high-reliability FPGA. In one embodiment, the inspection frequency is temporarily increased within a predetermined period after it is determined that the operating state of the high-reliability FPGA has a fault, and the inspection frequency is restored after it is determined that the operating state of the high-reliability FPGA has been fault-free for a predetermined period of time; and / or, when it is determined that the operating environment of the high-reliability FPGA has become worse, the inspection frequency is increased; and / or, when it is determined that the reliability requirements of the high-reliability FPGA have become higher, the inspection frequency is increased. That is, when the operating state, operating environment and reliability requirements of the high-reliability FPGA indicate that the probability of a fault has increased or indicate that the reliability requirements have increased, the inspection frequency is increased to give priority to ensuring the operating reliability, otherwise a lower inspection frequency is maintained to reduce the negative impact of the inspection mechanism.

[0056] In addition, as mentioned above, whether the storage or recovery of the working state is achieved based on the voltage control of the memristor by the check rollback controller, so the check rollback controller needs to connect and control the resistance state of the memristor built into each non-volatile sequential element through the control line network. When the control line network structure is different, the control method of the check rollback controller for all non-volatile sequential elements is also different:

[0057] When each non-volatile sequential element in the control line network shares the same control line with the check rollback controller, the check rollback controller simultaneously reads the resistance state of the memristor built into each non-volatile sequential element, and the check rollback controller simultaneously configures the resistance state of the memristor built into each non-volatile sequential element. Figure 3 In the embodiment, the two non-volatile DFFs share the same control line with the check rollback controller, that is, the same ports of the two non-volatile DFFs are connected and connected to the same port of the check rollback controller, then the check rollback controller can simultaneously control the data saving signal SET of the two non-volatile DFFs to be in a valid level state, and simultaneously apply the programming voltage PHV to the ends of the memristors of the two non-volatile DFFs, thereby controlling the two non-volatile DFFs to simultaneously use the resistance state of the built-in memristors to store the current working state of the output end of the non-volatile DFF. The check rollback controller can also simultaneously control the data recovery signal RES of the two non-volatile DFFs to be in a valid level state and the set signal to be in a non-valid level state, so as to simultaneously restore the resistance state of the built-in memristors of the two non-volatile DFFs to their most recent operating state.

[0058] When there are at least two control lines between the non-volatile sequential elements and the check rollback controller in the control line network and the control lines are independent of each other, the control line network forms a hierarchical structure, and the check rollback controller sequentially reads the resistance state of the memristor built into each non-volatile sequential element according to the hierarchical order formed by the hierarchical structure, and the check rollback controller also sequentially configures the resistance state of the memristor built into each non-volatile sequential element according to the same hierarchical order. Figure 3 The structure of the check rollback controller can be connected to two non-volatile DFFs respectively, and then control the working process of the two non-volatile DFFs in sequence. According to the number and position of non-volatile sequential elements, the hierarchical structure formed by the control line network can be diverse and can be designed according to actual needs. After determining the control line network, the hierarchical order of implementation can be determined accordingly.

[0059] When the structure of the control line network is different, the read configuration process of the check and rollback controller for all non-volatile sequential elements will be different. This difference causes the total check time and the total rollback time to be different. The total check time and the total rollback time of the check and rollback controller are both related to the structure of the control line network. Among them, the total check time is the time it takes for the check and rollback controller to control all non-volatile sequential elements to complete the update and storage of the current working state. The total rollback time is the time it takes for the check and rollback controller to control all non-volatile sequential elements to complete the recovery to the most recent working state.

[0060] In one embodiment, the check rollback controller and the control line network included in the high-reliability FPGA are all implemented using the built-in programmable resources of the high-reliability FPGA. Thanks to this feature, the function of the check rollback controller and the structure of the control line network can be adjusted through configuration information. This adjustment configuration can be implemented by the same configuration chain of the FPGA or by an independent configuration chain or by pin input control. Based on the configurable characteristics, the function of the check rollback controller and the structure of the control line network can be adjusted, and accordingly the total check time and the total rollback time can be adjusted, so the total check time and the total rollback time can be adjusted to appropriate values.

[0061] In order to store the working status of each non-volatile sequential element as quickly as possible, it is generally hoped that the total inspection time can be as short as possible, and in order to restore the working status of each non-volatile sequential element as quickly as possible, it is generally hoped that the total rollback time can be as short as possible. When the control line network is designed so that all non-volatile sequential elements and the check and rollback controller share the same control line, the check and rollback controller can control each non-volatile sequential element at the same time, so that the total inspection time and the total rollback time can be minimized. However, the structure of the control line network is not only related to the total inspection time and the total rollback time, but also affects other performances, such as affecting the wiring area of ​​the control line network, affecting the instantaneous current of the control line network, etc. When the control line network is designed so that all non-volatile sequential elements and the check and rollback controller share the same control line, it will bring other negative effects, such as affecting the wiring area, such as causing excessive instantaneous current, so the structure of the control line network cannot be designed blindly in pursuit of shorter total inspection time and total rollback time.

[0062] As described above, thanks to the fact that both the check rollback controller and the control line network are implemented based on the programmable resources built into the high-reliability FPGA, the programmable resources can be configured according to actual needs to form a suitable control line network structure to achieve better overall performance. In the design process of the high-reliability FPGA, the circuit structure of the control line network formed by the programmable resources matches the circuit design requirements. The circuit design requirements here include at least one of the wiring area of ​​the control line network, the total check time of the check rollback controller, the total rollback time of the check rollback controller, the maximum instantaneous current of the resistance state of the built-in memristor of each non-volatile sequential element read by the check rollback controller, and the maximum instantaneous current of the resistance state of the built-in memristor of each non-volatile sequential element configured by the check rollback controller.

[0063] The above are only preferred embodiments of the present application, and the present application is not limited to the above embodiments. It is understood that other improvements and changes directly derived or associated by those skilled in the art without departing from the spirit and concept of the present application should be considered to be included in the protection scope of the present application.

Claims

1. A high reliability FPGA based on memristor to implement check rollback, characterized in that: The high-reliability FPGA includes at least one non-volatile sequential element formed by a variable resistance memristor, and the high-reliability FPGA also includes a check rollback controller; during the operation of the high-reliability FPGA: When the current operating state of the high-reliability FPGA is fault-free, the check rollback controller controls each non-volatile sequential element to update and store the current working state of the non-volatile sequential element using the resistance state of the built-in memristor; When a fault occurs in the current operating state of the high-reliability FPGA, the check rollback controller controls each non-volatile sequential element to recover to the most recent working state of the non-volatile sequential element by using the resistance state of the built-in memristor, and drives the high-reliability FPGA to recover to the most recent fault-free operating state; The check rollback controller is connected to and controls the resistance state of the built-in memristor of each non-volatile timing element through a control line network; when each non-volatile timing element in the control line network shares the same control line with the check rollback controller, the check rollback controller simultaneously reads the resistance state of the built-in memristor of each non-volatile timing element, and the check rollback controller simultaneously configures the resistance state of the built-in memristor of each non-volatile timing element; when there are at least two non-volatile timing elements in the control line network and the control lines between the check rollback controller are independent of each other, the control line network forms a hierarchical structure, and the check rollback controller reads the resistance state of the built-in memristor of each non-volatile timing element in sequence according to the hierarchical order, and the check rollback controller sequentially configures the resistance state of the built-in memristor of each non-volatile timing element in sequence according to the hierarchical order.

2. The high reliability FPGA according to claim 1, characterized in that: During the operation of the high-reliability FPGA, when it is determined that the current operating state of the high-reliability FPGA is fault-free, the check rollback controller controls each non-volatile timing element according to a predetermined check frequency to update and store the current working state of the non-volatile timing element using the resistance state of the built-in memristor.

3. The high reliability FPGA according to claim 2, characterized in that: The inspection frequency used by the inspection rollback controller is dynamically variable during the operation of the high-reliability FPGA, and the inspection frequency is related to at least one of the operating state, operating environment and reliability requirements of the high-reliability FPGA.

4. The high reliability FPGA according to claim 3, characterized in that: During the operation of the high reliability FPGA: Temporarily increase the inspection frequency within a predetermined period after determining that the operation state of the high-reliability FPGA has a fault, and restore the inspection frequency after determining that the operation state of the high-reliability FPGA has been fault-free for a predetermined period of time; and / or, when it is determined that the operating environment of the high-reliability FPGA has become severe, increasing the inspection frequency; And / or, when it is determined that the reliability requirement of the high-reliability FPGA becomes higher, the inspection frequency is increased.

5. The high reliability FPGA according to claim 1, characterized in that: During the operation of the high reliability FPGA: Suspending the user function executed by the high-reliability FPGA, and performing a fault test on the current running state of the high-reliability FPGA, and resuming the execution of the user function after completing the fault test, the check rollback controller determining whether there is a fault in the current running state of the high-reliability FPGA according to the fault test result; While the high-reliability FPGA is executing user functions, a fault test is performed on the current running state of the high-reliability FPGA in parallel, and the check rollback controller determines whether there is a fault in the current running state of the high-reliability FPGA based on the fault test result.

6. The high reliability FPGA according to claim 1, characterized in that: The total inspection time and the total rollback time of the inspection and rollback controller are both related to the structure of the control line network, and the total inspection time and the total rollback time are adjustable; The total inspection time is the time taken for the inspection rollback controller to control all non-volatile sequential elements to complete updating and storing the current working state; The total rollback time is the time taken for the check rollback controller to control all non-volatile sequential elements to complete recovery to the most recent working state.

7. The high reliability FPGA according to claim 1, characterized in that: The check rollback controller and the control line network are both implemented using programmable resources built into the high-reliability FPGA; and in the design process of the high-reliability FPGA, the circuit structure of the control line network formed using programmable resources matches the circuit design requirements.

8. The high reliability FPGA according to claim 1, characterized in that: The circuit design requirements include at least one of the wiring area of ​​the control line network, the total inspection time of the check rollback controller, the total rollback time of the check rollback controller, the maximum instantaneous current of the resistance state of the built-in memristor of each non-volatile timing element read by the check rollback controller, and the maximum instantaneous current of the resistance state of the built-in memristor of each non-volatile timing element configured by the check rollback controller.

9. The high reliability FPGA according to claim 1, characterized in that: The nonvolatile sequential elements included in the high-reliability FPGA include a nonvolatile DFF, a nonvolatile BRAM, and a sequential element providing a configuration bit, the sequential element providing the configuration bit includes a nonvolatile distributed random access memory and a nonvolatile shift register, and the nonvolatile BRAM, the nonvolatile distributed random access memory, and the nonvolatile shift register are respectively constructed based on the nonvolatile DFF; For the non-volatile DFF, the check and rollback controller controls the data save signal SET of the non-volatile DFF to be in a valid level state, and applies a programming voltage PHV at the end of the memristor to control the non-volatile DFF to store the current working state of the output end of the non-volatile DFF using the resistance state of the built-in memristor; the check and rollback controller controls the data recovery signal RES of the non-volatile DFF to be in a valid level state and the set signal to be in a non-valid level state, so as to restore the resistance state of the built-in memristor of the non-volatile DFF to the most recent operating state of the non-volatile DFF.

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