Solar cell and preparation method thereof, photovoltaic module

Abstract

The present application relates to a solar cell and a method for preparing the same, and a photovoltaic module. The solar cell comprises: a semiconductor substrate, comprising a first surface and a second surface arranged opposite to each other; a plurality of passivation regions and a plurality of passivation contact regions are arranged on the semiconductor substrate, and the plurality of passivation regions and the plurality of passivation contact regions are arranged alternately along a first direction; the first direction is perpendicular to the thickness direction of the semiconductor substrate; a plurality of passivation contact structures are arranged on the second surface, and are correspondingly distributed in each of the passivation contact regions; wherein the passivation contact structure comprises a conductive passivation layer; a dielectric layer, the dielectric layer at least covers the second surface located in the passivation region; and a plurality of first electrodes, and at least one of the first electrodes is arranged on the side of each of the passivation contact structures away from the semiconductor substrate. The present application can reduce the absorption of long-wavelength light by the passivation contact structure, increase the current, and improve the efficiency of the battery.

Description

Technical Field

[0001] The present application relates to the technical field of solar photovoltaic cells, and in particular to a solar cell and a preparation method thereof, and a photovoltaic module. Background Art

[0002] With the continuous development of solar cell technology, people have higher and higher requirements for the photoelectric conversion efficiency of cells. However, the improvement of industrial cell efficiency is still facing many challenges. Among them, the contact recombination between metal and silicon contact area and the Auger recombination and deep energy level recombination caused by diffusion in the silicon matrix are the main factors restricting the improvement of cell efficiency. TOPCon (Tunnel Oxide Passivated Contact) cells reduce the recombination of surface carriers by setting a passivation contact structure on the back of the silicon substrate. How to further improve the efficiency of TOPCon cells has become the research focus of technicians in this field. Summary of the invention

[0003] Based on this, it is necessary to provide a solar cell and a preparation method thereof, and a photovoltaic module to address the above problems.

[0004] In a first aspect, an embodiment of the present application provides a solar cell, comprising:

[0005] A semiconductor substrate, comprising a first surface and a second surface arranged opposite to each other; a plurality of passivation regions and a plurality of passivation contact regions are arranged on the semiconductor substrate, and the plurality of passivation regions and the plurality of passivation contact regions are arranged alternately along a first direction; the first direction is perpendicular to a thickness direction of the semiconductor substrate;

[0006] A plurality of passivation contact structures are provided on the second surface and are distributed correspondingly in each of the passivation contact regions; wherein the passivation contact structure comprises a conductive passivation layer;

[0007] a dielectric layer, the dielectric layer at least covering the second surface located in the passivation region; and

[0008] A plurality of first electrodes are provided, and at least one first electrode is disposed on a side of each of the passivation contact structures away from the semiconductor substrate.

[0009] In one embodiment, there is a first distance between the second surface located in the passivation region and the first surface, and there is a second distance between the second surface located in the passivation contact region and the first surface;

[0010] The second distance is greater than the first distance.

[0011] In one embodiment, the difference between the second distance and the first distance is greater than 1 μm.

[0012] In one embodiment, the solar cell further includes a plurality of first diffusion layers disposed in the semiconductor substrate, the plurality of first diffusion layers are correspondingly distributed in the plurality of passivation contact regions, and each of the first diffusion layers is in contact with the second surface.

[0013] In one embodiment, the difference between the second distance and the first distance is greater than or equal to a dimension of the first diffusion layer along a thickness direction of the semiconductor substrate.

[0014] In one embodiment, the second surface is a backlight surface.

[0015] In one of the embodiments, the roughness of the second surface located in the passivation region is smaller than the roughness of the second surface located in the passivation contact region.

[0016] In one embodiment, a plurality of pits are provided on the second surface; the pit located in the passivation area and having the deepest depth is defined as the first pit, and the pit located in the passivation contact area and having the deepest depth is defined as the second pit;

[0017] The depth of the first pit is smaller than the depth of the second pit.

[0018] In one embodiment, the inner diameter of the first recess is greater than the inner diameter of the second recess.

[0019] In one embodiment, there is a first distance between the second surface located in the passivation region and the first surface, and there is a second distance between the second surface located in the passivation contact region and the first surface;

[0020] The second distance is greater than the first distance.

[0021] In one embodiment, from the second surface to the first surface, the size of the passivation contact structure along the first direction gradually decreases.

[0022] In one of the embodiments, the passivation contact structure further includes a tunneling layer, and the tunneling layer is disposed between the conductive passivation layer and the semiconductor substrate;

[0023] From the second surface to the first surface, the size of the conductive passivation layer along the first direction gradually decreases.

[0024] In one embodiment, each of the passivation contact structures is provided with a first electrode; a surface of the conductive passivation layer close to the tunneling layer is a first surface, and a surface of the conductive passivation layer away from the tunneling layer is a second surface;

[0025] The size of the first surface along the first direction, the size of the second surface along the first direction, and the size of the first electrode along the first direction satisfy the following relationship:

[0026]

[0027] Wherein, W1 is the size of the first surface along the first direction, W2 is the size of the second surface along the first direction, and W3 is the size of the first electrode along the first direction.

[0028] In one of the embodiments, the dielectric layer also covers a surface of the passivation contact structure close to the passivation region.

[0029] In one embodiment, the second surface of the semiconductor substrate includes a first sub-surface, a second sub-surface and a connection surface; the first sub-surface is located in the passivation region, the second sub-surface is located in the passivation contact region, and the connection surface connects the adjacent first sub-surface and the second sub-surface;

[0030] The dielectric layer also covers the connecting surface.

[0031] In one embodiment, the second sub-surface includes a sub-contact surface and two non-contact surfaces, and the two non-contact surfaces are arranged on both sides of the sub-contact surface along the first direction; the passivation contact structure contacts the sub-contact surface;

[0032] The dielectric layer also covers the non-contact surface.

[0033] In one embodiment, the dielectric layer includes one or more of aluminum oxide, silicon nitride, and silicon oxynitride.

[0034] In one of the embodiments, the conductive passivation layer includes a doped polysilicon layer, and the doped polysilicon layer is doped with an N-type doping element or a P-type doping element.

[0035] In one of the embodiments, the doped polysilicon layer is further doped with one or more of carbon, nitrogen and oxygen.

[0036] In one of the embodiments, the conductive passivation layer further includes a silicon carbide layer, and the silicon carbide layer is disposed on a side of the doped polysilicon layer away from the semiconductor substrate.

[0037] In a second aspect, an embodiment of the present application provides a method for preparing a solar cell, comprising:

[0038] A semiconductor substrate is provided, the semiconductor substrate comprising a first surface and a second surface arranged opposite to each other; a plurality of passivation regions and a plurality of passivation contact regions are arranged on the semiconductor substrate, the plurality of passivation regions and the plurality of passivation contact regions are arranged alternately along a first direction; the first direction is perpendicular to a thickness direction of the semiconductor substrate;

[0039] forming a plurality of passivation contact structures on the second surface; wherein the plurality of passivation contact structures are correspondingly distributed in each of the passivation contact regions; and the passivation contact structure comprises a conductive passivation layer;

[0040] forming a dielectric layer on the semiconductor substrate; the dielectric layer at least covers the second surface located in the passivation region;

[0041] A plurality of first electrodes are formed on the plurality of passivation contact structures; at least one first electrode is disposed on a side of each of the passivation contact structures away from the semiconductor substrate.

[0042] In one embodiment, the forming of a plurality of passivation contact structures on the second surface and the forming of a plurality of first diffusion layers in the semiconductor substrate include:

[0043] forming a stacked tunneling material layer and a conductive passivation material layer on the second surface;

[0044] forming a patterned mask layer on the conductive passivation material layer;

[0045] The tunneling material layer and the conductive passivation material layer located in the passivation region are removed to form the passivation contact structure.

[0046] In one of the embodiments, after forming the stacked tunneling material layer and the conductive passivation material layer on the second surface, before forming the patterned mask layer on the conductive passivation material layer, the method includes: heat treating the conductive passivation material layer and forming an initial diffusion layer; or, after forming the patterned mask layer on the conductive passivation material layer, before removing the tunneling material layer and the conductive passivation material layer located in the passivation area to form the passivation contact structure, the method includes: heat treating the conductive passivation material layer and forming an initial diffusion layer;

[0047] After removing the tunneling material layer and the conductive passivation material layer located in the passivation region to form the passivation contact structure, the method further includes removing the initial diffusion layer located in the passivation region to form the first diffusion layer.

[0048] In a third aspect, an embodiment of the present application provides a photovoltaic assembly, comprising the solar cell in the first aspect.

[0049] The solar cell and its preparation method, and photovoltaic module provided by the embodiment of the present application are provided with alternately arranged passivation regions and passivation contact regions on the semiconductor substrate, and the multiple passivation contact structures provided on the second surface are distributed correspondingly in each of the passivation contact regions. In this way, it is equivalent to providing multiple spaced passivation contact structures on the second surface, which can reduce the coverage area of ​​the conductive passivation layer on the second surface compared to the traditional TOPCon cell, thereby helping to reduce the absorption of long-wavelength light by the conductive passivation layer, increase the current, and improve the cell efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] In order to more clearly illustrate the technical solutions in the embodiments or exemplary embodiments of the present application, the drawings required for use in the description of the embodiments or exemplary embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0051] Figure 1 A schematic diagram of a partial cross-sectional structure of a solar cell provided in one embodiment of the present application.

[0052] Figure 2 for Figure 1 A partial schematic diagram of a semiconductor substrate of a solar cell is shown.

[0053] Figure 3 for Figure 2 Enlarged view of part A.

[0054] Figure 4 for Figure 2 Magnified view of part B.

[0055] Figure 5 for Figure 1 A schematic structural diagram of a semiconductor substrate and a passivation contact structure of a solar cell is shown.

[0056] Figure 6 A schematic diagram of a process for preparing a solar cell provided in one embodiment of the present application.

[0057] Figure 7 for Figure 6 A schematic diagram of a process flow of S20 in the preparation method shown.

[0058] Figure 8 for Figure 6 Another schematic diagram of the process of S20 in the preparation method shown.

[0059] Fig. 9 for Figure 6 A schematic diagram of the partial cross-sectional structure of a semiconductor substrate after texturing during the preparation method shown.

[0060] Fig.10 for Figure 6 A schematic diagram of the partial cross-sectional structure of a semiconductor substrate after polishing during the preparation method shown.

[0061] Fig.11 for Figure 6 A schematic diagram of the partial cross-sectional structure of a tunneling material layer, a conductive passivation material layer and an oxide layer after they are formed during the preparation method shown.

[0062] Fig.12 for Figure 6 A schematic diagram of the partial cross-sectional structure of a semi-finished structure of a solar cell after heat treatment during the preparation method shown.

[0063] Fig.13 for Figure 6 A schematic diagram of the partial cross-sectional structure of a patterned mask layer after formation during the preparation method shown.

[0064] Fig.14 for Figure 6 A schematic diagram of the local cross-sectional structure of a passivation contact structure after formation during the preparation method shown.

[0065] Fig.15 for Figure 6 A schematic diagram of the local cross-sectional structure of the dielectric layer after formation during the preparation method shown.

[0066] Reference numerals:

[0067] 1. Solar cell; 11. Semiconductor substrate; 11a. Passivation region; 11b. Passivation contact region; 111. First surface; 112. Second surface; 1121. First sub-surface; 1122. Second sub-surface; 11221. Sub-contact surface; 11222. Non-contact surface; 1123. Connecting surface; 12. Passivation contact structure; 121. Tunneling layer; 122. Conductive passivation layer; 13. Dielectric layer; 14. First electrode; 15. First diffusion layer; 16. Pits; 16a. First pits; 16b. Second pits; 21. Tunneling material layer; 22. Conductive passivation material layer; 231. Oxide layer; 232. Patterned mask layer; 24. Initial diffusion layer. DETAILED DESCRIPTION

[0068] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are described in detail below in conjunction with the accompanying drawings. In the following description, many specific details are set forth to facilitate a full understanding of the present application. However, the present application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without violating the connotation of the present application, so the present application is not limited by the specific embodiments disclosed below.

[0069] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0070] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, doping type or part discussed below can be represented as a second element, component, region, layer or part.

[0071] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0072] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0073] Embodiments of the application are described herein with reference to cross-sectional views that are schematic diagrams of ideal embodiments (and intermediate structures) of the application, so that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, embodiments of the application should not be limited to the specific shapes of the zones shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Therefore, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the application.

[0074] As described in the background technology, the traditional TOPCon cell has a passivation contact structure on the back of the silicon substrate to reduce the recombination of surface carriers. However, the doped polysilicon layer in the passivation contact structure easily absorbs long-wavelength light and produces parasitic absorption, thereby reducing the current and affecting the cell efficiency.

[0075] Related technology 1 reduces the absorption of long-wavelength light by the doped polysilicon layer by thinning the doped polysilicon layer. However, when making the metal electrode, the metal paste is easy to burn through the passivation contact structure, affecting the passivation effect.

[0076] Related technology 2 selectively sets the thickness of the doped polysilicon layer, so that the thickness of the doped polysilicon layer in the metal electrode area is thicker and the thickness of the doped polysilicon layer in the non-metal electrode area is thinner. However, on the one hand, this structure still has a relatively serious parasitic absorption phenomenon; on the other hand, the preparation process of this structure is relatively complicated and is not suitable for large-scale mass production.

[0077] In view of at least one of the above problems, the embodiments of the present application provide a solar cell and a method for preparing the same, and a photovoltaic module, by providing alternately arranged passivation regions and passivation contact regions on a semiconductor substrate, and making the multiple passivation contact structures provided on the second surface correspondingly distributed in each of the passivation contact regions. In this way, it is equivalent to providing multiple spaced passivation contact structures on the second surface. Compared with the traditional TOPCon battery, the coverage area of ​​the passivation contact structure on the second surface can be reduced, which is beneficial to reduce the absorption of long-wavelength light by the passivation contact structure, increase the current, and improve the battery efficiency. In addition, compared with the related art one, the solar cell provided by the present application will not affect the passivation effect; compared with the related art two, the solar cell provided by the present application is less difficult to prepare and more manufacturable.

[0078] First, refer to Figure 1 As shown, the embodiment of the present application provides a solar cell 1, which may be a TOPCon cell. Specifically, the solar cell 1 includes a semiconductor substrate 11, a plurality of passivation contact structures 12, a dielectric layer 13, and a plurality of first electrodes 14.

[0079] The material of the semiconductor substrate 11 may be silicon. The semiconductor substrate 11 includes a first surface 111 and a second surface 112 arranged opposite to each other. Specifically, one of the first surface 111 and the second surface 112 may be a light-facing surface, and the other may be a backlight surface. A plurality of passivation regions 11a and a plurality of passivation contact regions 11b are provided on the semiconductor substrate 11, and the plurality of passivation regions 11a and the plurality of passivation contact regions 11b are alternately arranged along a first direction X. The first direction X is perpendicular to the thickness direction of the semiconductor substrate 11. The plurality of passivation contact structures 12 are provided on the second surface 112 and are correspondingly distributed in each passivation contact region 11b, and the passivation contact structure 12 includes a conductive passivation layer 122. At least one first electrode 14 is provided on a side of each passivation contact structure 12 away from the semiconductor substrate 11. The dielectric layer 13 at least covers the second surface 112 located in the passivation region 11a.

[0080] It should be noted that the passivation regions 11a and the passivation contact regions 11b are alternately arranged, that is, two passivation regions 11a form a group, two passivation contact regions 11b form a group, and a group of passivation regions 11a and a group of passivation contact regions 11b are alternately arranged in sequence. The passivation regions 11a and the passivation contact regions 11b are alternately arranged, that is, one passivation region 11a and one passivation contact region 11b are alternately arranged in sequence, that is, one passivation contact region 11b is provided between any two adjacent passivation regions 11a, and one passivation region 11a is provided between any two adjacent passivation contact regions 11b.

[0081] It should also be noted that the plurality of passivation contact structures 12 may correspond to each passivation contact region 11b one by one, or two, three or more passivation contact structures 12 may correspond to one passivation contact region 11b. Each passivation contact structure 12 may be provided with one, two or more first electrodes 14. Figure 1 Only one passivation contact region 11b is shown, so Figure 1 Only one first diffusion layer 15 is shown.

[0082] The embodiment of the present application provides a solar cell 1, which is equivalent to providing a passivation contact structure 12 arranged at intervals on the second surface 112. Compared with the traditional TOPCon cell, the passivation contact structure 12 is not provided on the second surface 112 located in the passivation area 11a, so that the coverage area of ​​the passivation contact structure 12 (such as the conductive passivation layer 122) on the second surface 112 can be reduced, which is beneficial to reduce the absorption of long-wavelength light by the passivation contact structure 12 (such as the conductive passivation layer 122), thereby increasing the absorption of current and improving the cell efficiency.

[0083] In addition, compared to the first related art, the solar cell 1 provided in the embodiment of the present application does not reduce the thickness of the passivation contact structure 12 when manufacturing the metal electrode, so the metal paste is not easy to burn through the passivation contact structure 12, thereby not affecting the passivation effect. Compared to the second related art, the solar cell 1 provided in the embodiment of the present application needs to completely remove the material of the passivation contact structure 12 in the passivation area 11a during the preparation process, so that the manufacturing process window is relatively large, the difficulty of preparation is reduced, and mass production is higher.

[0084] In one embodiment, the solar cell 1 further includes a plurality of first diffusion layers 15 disposed in the semiconductor substrate 11 . The plurality of first diffusion layers 15 are distributed correspondingly in the plurality of passivation contact regions 11 b , and each of the first diffusion layers 15 is in contact with the second surface 112 .

[0085] In the embodiment of the present application, the passivation region 11a in the semiconductor substrate 11 and the region adjacent to the second surface 112 are not provided with a diffusion layer, which is beneficial to reducing recombination. The passivation contact region 11b in the semiconductor substrate 11 and the region adjacent to the second surface 112 are provided with a first diffusion layer 15, which is beneficial to improving the carrier collection efficiency.

[0086] In one embodiment, the first surface 111 is a light-facing surface, and the second surface 112 is a backlight surface. In this way, it is equivalent to setting the passivation contact structure 12 arranged at intervals on the backlight surface. Compared with the traditional TOPCon battery, the passivation contact structure 12 is not set on the second surface 112 located in the passivation area 11a, so that the coverage area of ​​the passivation contact structure 12 (such as the conductive passivation layer 122) on the second surface 112 can be reduced, which is conducive to reducing the absorption of long-wavelength light by the passivation contact structure 12 (such as the conductive passivation layer 122), increasing the absorption of current, and improving the battery efficiency.

[0087] In one embodiment, there is a first distance between the second surface 112 located in the passivation area 11a and the first surface 111, and there is a second distance between the second surface 112 located in the passivation contact area 11b and the first surface 111. The second distance is greater than the first distance. It can also be understood that: the depth of the second surface 112 located in the passivation area 11a is greater than the depth of the second surface 112 located in the passivation contact area 11b.

[0088] The above arrangement, on the one hand, is conducive to forming the passivation contact structures 12 arranged at intervals on the second surface 112; on the other hand, it is conducive to removing the diffusion layer of the passivation area 11a, which is conducive to reducing recombination; on the other hand, during the manufacturing process, pits 16 will be formed on the second surface 112 of the semiconductor substrate 11. By making the depth of the second surface 112 located in the passivation area 11a greater than the depth of the second surface 112 located in the passivation contact area 11b, it is equivalent to corroding the second surface 112 located in the passivation area 11a deeper, which is conducive to forming pits 16 with a larger inner diameter and a shallower depth, and further conducive to making the roughness of the second surface 112 located in the passivation area 11a smaller and the reflective effect better.

[0089] In one embodiment, the difference between the second distance and the first distance is greater than 1 μm. In this way, on the one hand, the diffusion layer of the passivation area 11a can be removed, which is beneficial to reducing recombination; on the other hand, during the manufacturing process, the second surface 112 located in the passivation area 11a can be etched deeper, which is beneficial to forming a pit 16 with a larger inner diameter and a shallower depth, thereby making the second surface 112 located in the passivation area 11a less rough and having a better reflective effect.

[0090] In one embodiment, referring to Figure 1 As shown, the difference between the second distance and the first distance is greater than or equal to the dimension of the first diffusion layer 15 along the thickness direction of the semiconductor substrate 11. It can be understood that the difference between the second distance and the first distance is equal to the depth of the second surface 112 located in the passivation region 11a, and the dimension of the first diffusion layer 15 along the thickness direction of the semiconductor substrate 11 is the thickness of the first diffusion layer 15.

[0091] By making the depth of the second surface 112 located in the passivation area 11a not less than the thickness of the first diffusion layer 15, on the one hand, it can ensure that the first diffusion layer 15 in the passivation area 11a is completely removed, which is beneficial to reducing recombination; on the other hand, it is beneficial to make the roughness of the second surface 112 located in the passivation area 11a smaller, thereby achieving better reflective effect and better passivation effect.

[0092] In one embodiment, the second surface 112 located in the passivation region 11 a may have a non-pyramid microstructure morphology, and the second surface 112 located in the passivation contact region 11 b may have a pyramid microstructure morphology.

[0093] In one embodiment, the roughness of the second surface 112 located in the passivation region 11a is smaller than the roughness of the second surface 112 located in the passivation contact region 11b. Here, the roughness may be surface roughness.

[0094] In this way, the smoothness of the second surface 112 located in the passivation area 11a can be increased, thereby increasing the mirror reflection effect. When a fixed angle of light is incident, since the second surface 112 located in the passivation area 11a has a greater smoothness, the second surface 112 located in the passivation area 11a has a better reflection effect, and can reflect more long-wave light back into the semiconductor substrate 11, which is beneficial to increase the absorption of current, thereby improving the battery efficiency.

[0095] In the embodiment of the present application, the reflectivity of the second surface 112 located in the passivation area 11a is greater than the reflectivity of the second surface 112 located in the passivation contact area 11b. On the one hand, this is because the roughness of the second surface 112 located in the passivation area 11a is less than the roughness of the second surface 112 located in the passivation contact area 11b; on the other hand, this is because the second surface 112 located in the passivation area 11a is not covered by the passivation contact structure 12, so that the absorption of long-wavelength light is smaller.

[0096] In one embodiment, referring to Figure 2 , Figure 3 and Figure 4 As shown, a plurality of pits 16 are provided on the second surface 112. Among them, a plurality of pits 16 are provided on the second surface 112 located in the passivation area 11a, and a plurality of pits 16 are also provided on the second surface 112 located in the passivation contact area 11b. It should be noted that Figure 2 FIG. 1 is a schematic diagram of the second surface 112 of the semiconductor substrate 11 under a microscopic view.

[0097] The pit 16 located in the passivation region 11a and having the deepest depth is defined as the first pit 16a, and the pit 16 located in the passivation contact region 11b and having the deepest depth is defined as the second pit 16b. The depth of the first pit 16a is less than the depth of the second pit 16b. Here, the dimension of the first pit 16a along the thickness direction of the semiconductor substrate 11 is the depth of the first pit 16a, and the dimension of the second pit 16b along the thickness direction of the semiconductor substrate 11 is the depth of the second pit 16b. Figure 3 As shown, the size of the first pit 16a along the thickness direction of the semiconductor substrate 11 is H1, and the size of the second pit 16b along the thickness direction of the semiconductor substrate 11 is H2.

[0098] It should be noted that pits will be formed on the initial surface of the semiconductor substrate 11 after polishing. Since the diffusion layer of the passivation area 11a needs to be removed, the second surface 112 located in the passivation area 11a needs to be further polished to remove the diffusion layer in this area. During the polishing process, the depth of the pits 16 located on the second surface 112 of the passivation area 11a is reduced. In this way, the depth of most of the pits 16 located on the second surface 112 of the passivation area 11a is reduced. Furthermore, the depth of the pits 16 is related to the roughness. On the same surface, the smaller the depth difference between the deepest pit 16 and the shallowest pit 16, the smaller the roughness. Therefore, the above-mentioned setting is conducive to making the roughness of the second surface 112 located in the passivation area 11a smaller than the roughness of the second surface 112 located in the passivation contact area 11b.

[0099] In one embodiment, the roughness of the second surface 112 of the passivation region 11a can be defined by the depths of all the pits 16 on the second surface 112 of the passivation region 11a. Further, the standard deviation of the depths of all the pits 16 on the second surface 112 of the passivation region 11a is the roughness of the second surface 112 of the passivation region 11a.

[0100] The roughness of the second surface 112 of the passivation contact region 11b can be defined by the depths of all the pits 16 on the second surface 112 of the passivation contact region 11b. Further, the standard deviation of the depths of all the pits 16 on the second surface 112 of the passivation contact region 11b is the roughness of the second surface 112 of the passivation contact region 11b.

[0101] Furthermore, the standard deviation of the depths of all the pits 16 located on the second surface 112 of the passivation region 11 a is smaller than the standard deviation of the depths of all the pits 16 located on the second surface 112 of the passivation contact region 11 b .

[0102] It should be noted that when calculating the standard deviation, the standard deviation of the depths of all the pits 16 within a unit area may be calculated.

[0103] In one embodiment, the inner diameter of the first recess 16a is greater than the inner diameter of the second recess 16b. Figure 3 As shown, the inner diameter of the first recess 16a is D1. Figure 4 As shown, the inner diameter of the second dimple 16b is D2. It should be noted that if the dimple 16 is a circular dimple 16, the inner diameter of the dimple 16 is the diameter of the circular dimple 16. If the dimple 16 is a square dimple 16, the inner diameter of the dimple 16 may be the side length of the square dimple 16. If the dimple 16 is a rectangular dimple 16, the inner diameter of the dimple 16 may be the maximum side length of the rectangular dimple 16. If the dimple 16 is an irregularly shaped dimple 16, the inner diameter of the dimple 16 may be the maximum inner diameter of the irregular shape.

[0104] It can be understood that the inner diameter of the pit 16 is inversely proportional to the depth of the pit 16. In the process of polishing and removing the diffusion layer of the passivation area 11a, the depth of the pit 16 located on the second surface 112 of the passivation area 11a is reduced and the inner diameter is increased. In this way, the inner diameter of the first pit 16a is larger than the inner diameter of the second pit 16b.

[0105] In one embodiment, the inner diameter of each pit 16 located on the second surface 112 of the passivation region 11a is greater than the inner diameter of the pit 16 (second pit 16b) located in the passivation contact region 11b and having the largest inner diameter. In this way, the depth of each pit 16 located on the second surface 112 of the passivation region 11a is smaller and smaller than the depth of the pit 16 (second pit 16b) located in the passivation contact region 11b and having the deepest depth. This is conducive to making the roughness of the second surface 112 located in the passivation region 11a smaller than the roughness of the second surface 112 located in the passivation contact region 11b.

[0106] In another embodiment, the inner diameters of a portion of the pits 16 located on the second surface 112 of the passivation region 11a are all larger than the inner diameter of the pit 16 (the second pit 16b) located in the passivation contact region 11b and having the largest inner diameter. In this way, the depths of a portion of the pits 16 located on the second surface 112 of the passivation region 11a are all smaller than the depth of the pit 16 (the second pit 16b) located in the passivation contact region 11b and having the deepest depth.

[0107] In one embodiment, the inner diameter of the first pit 16a is between 8 μm and 40 μm. For example, the inner diameter of the first pit 16a may be 8 μm, 15 μm, 23 μm, 30 μm, 35 μm, 40 μm, or between any two of the above values.

[0108] In one embodiment, the inner diameter of the second pit 16b is between 5 μm and 20 μm. For example, the inner diameter of the second pit 16b can be 5 μm, 10 μm, 15 μm, 20 μm, or between any two of the above values.

[0109] In one embodiment, the depth of the first pit 16a is between 50 nm and 800 nm. For example, the depth of the first pit 16a can be 50 nm, 200 nm, 400 nm, 600 nm, 800 nm, or between any two of the above values.

[0110] In one embodiment, the depth of the second pit 16b is between 200 nm and 1000 nm. For example, the depth of the second pit 16b can be 200 nm, 400 nm, 500 nm, 700 nm, 850 nm, 1000 nm, or between any two of the above values.

[0111] By making the size (such as depth and inner diameter) of the first pit 16a and the size (such as depth and inner diameter) of the second pit 16b within the above-mentioned range, it is beneficial to form pits 16 of different sizes on the second surface 112 located in the passivation area 11a and the second surface 112 located in the passivation contact area 11b, respectively, which is beneficial to make the roughness of the second surface 112 located in the passivation area 11a smaller than the roughness of the second surface 112 located in the passivation contact area 11b.

[0112] In one embodiment, referring to Figure 1 As shown, the size of the passivation contact structure 12 along the first direction X gradually decreases from the second surface 112 to the first surface 111. That is, the width of the passivation contact structure 12 gradually decreases from the second surface 112 to the first surface 111. Under the same length, the surface area of ​​the passivation contact structure 12 on the side away from the semiconductor substrate 11 is larger, and the surface area of ​​the passivation contact structure 12 on the side close to the semiconductor substrate 11 is smaller. In this way, on the one hand, when making the first electrode 14, it is convenient to align and the difficulty of making the first electrode 14 can be reduced; on the other hand, the contact area between the passivation contact structure 12 and the second surface 112 can be reduced, thereby reducing the absorption of the passivation contact structure 12 to long-wavelength light.

[0113] In one embodiment, the passivation contact structure 12 further includes a tunneling layer 121, and the tunneling layer 121 is disposed between the conductive passivation layer 122 and the semiconductor substrate 11. From the second surface 112 to the first surface 111, the size of the conductive passivation layer 122 along the first direction X gradually decreases, that is, the width of the conductive passivation layer 122 gradually decreases. It can be understood that the material of the tunneling layer 121 can be silicon oxide, the material of the conductive passivation layer 122 can be polycrystalline silicon, microcrystalline silicon, silicon carbide, and the conductive passivation layer 122 is doped with N-type or P-type doping elements.

[0114] The inventor has found through research that the conductive passivation layer 122 (such as polysilicon) easily absorbs long-wavelength light. The above configuration makes the surface area of ​​the conductive passivation layer 122 close to the semiconductor substrate 11 smaller, which is conducive to reducing the absorption of long-wavelength light by the conductive passivation layer 122, and makes the surface area of ​​the conductive passivation layer 122 away from the semiconductor substrate 11 larger, which is convenient for alignment when manufacturing the first electrode 14, and can reduce the difficulty of manufacturing the first electrode 14.

[0115] In one embodiment, a first electrode 14 is provided on each passivation contact structure 12. A surface of the conductive passivation layer 122 close to the tunneling layer 121 is a first surface, and a surface of the conductive passivation layer 122 away from the tunneling layer 121 is a second surface. The size of the first surface along the first direction X, the size of the second surface along the first direction X, and the size of the first electrode 14 along the first direction X satisfy the following relationship.

[0116]

[0117] Wherein, W1 is the size of the first surface along the first direction X, W2 is the size of the second surface along the first direction X, and W3 is the size of the first electrode 14 along the first direction X.

[0118] The above arrangement, on the one hand, makes the surface area of ​​the conductive passivation layer 122 close to the semiconductor substrate 11 smaller, which is beneficial to reducing the absorption of long-wavelength light by the conductive passivation layer 122; on the other hand, it makes the surface area of ​​the conductive passivation layer 122 away from the semiconductor substrate 11 larger, which facilitates alignment when making the first electrode 14 and can reduce the difficulty of making the first electrode 14.

[0119] In one embodiment, the thickness of the tunneling layer 121 is between 0.5 nm and 2 nm. For example, the thickness of the tunneling layer 121 may be 0.5 nm, 1 nm, 1.5 nm or 2 nm.

[0120] In one embodiment, the solar cell 1 further includes a dielectric layer 13 , and the dielectric layer 13 at least covers the second surface 112 located in the passivation region 11 a and a surface of the passivation contact structure 12 away from the semiconductor substrate 11 .

[0121] In the embodiment of the present application, the dielectric layer 13 is in direct contact with the second surface 112 located in the passivation region 11a, and the second surface 112 located in the passivation region 11a has a smaller roughness (better flatness), which can make the passivation effect of the dielectric layer 13 better. In addition, the dielectric layer 13 covers the side surface of the passivation contact structure 12 away from the semiconductor substrate 11, which can also make the passivation contact structure 12 have a better passivation effect.

[0122] In one embodiment, the thickness of the dielectric layer 13 is less than 30 nm. For example, the thickness of the dielectric layer 13 may be 25 nm, 20 nm, 10 nm, etc.

[0123] In one embodiment, the dielectric layer 13 also covers the surface of the passivation contact structure 12 close to the passivation region 11a, that is, the dielectric layer 13 also covers the side surface of the passivation contact structure 12. In this way, the passivation contact structure 12 can have a better passivation effect.

[0124] In one embodiment, in combination Figure 5 As shown, the second surface 112 of the semiconductor substrate 11 includes a first sub-surface 1121, a second sub-surface 1122 and a connection surface 1123. The first sub-surface 1121 is located in the passivation region 11a, the second sub-surface 1122 is located in the passivation contact region 11b, and the connection surface 1123 connects the adjacent first sub-surface 1121 and the second sub-surface 1122. The dielectric layer 13 also covers the connection surface 1123. Figure 5 As shown, the second sub-surface 1122 and the connecting surface 1123 together form a step. In this way, it can be ensured that the side surface of the step has a good passivation effect.

[0125] In one embodiment, the second sub-surface 1122 includes a sub-contact surface 11221 and two non-contact surfaces 11222, and the two non-contact surfaces 11222 are arranged on both sides of the sub-contact surface 11221 along the first direction X. The passivation contact structure 12 contacts the sub-contact surface 11221. The dielectric layer 13 also covers the non-contact surface 11222. In this way, the non-contact surface 11222 of the second sub-surface 1122 can also have a good passivation effect.

[0126] In one embodiment, referring to Figure 1 As shown, a "mating groove" is formed between the passivation contact structure 12 and the non-contact surface 11222, and the dielectric layer 13 is embedded in the embedding groove. In this way, the connection strength between the dielectric layer 13 and the semiconductor substrate 11 can be made higher, and the structural stability of the solar cell 1 is improved.

[0127] In one embodiment, the dielectric layer 13 includes one or more of aluminum oxide, silicon nitride, silicon oxynitride, and silicon oxide.

[0128] In one example, the dielectric layer 13 includes an aluminum oxide layer, and the aluminum oxide layer covers at least the second surface 112 located in the passivation region 11a. Thus, compared with the conductive passivation layer 122 (such as doped polysilicon) covering the second surface 112 of the passivation region 11a in the related art, the aluminum oxide layer can have a better passivation effect in the passivation region 11a, and the passivation effect is equivalent to the passivation effect of doped polysilicon.

[0129] In another example, the dielectric layer 13 includes a silicon nitride layer, and the silicon nitride layer at least covers the second surface 112 located in the passivation region 11a. In this way, the silicon nitride layer can have a better passivation effect in the passivation region 11a, thereby improving the performance of the solar cell 1.

[0130] It is understandable that the dielectric layer 13 may be a stack of at least two layers of an aluminum oxide layer, a silicon nitride layer, and a silicon oxynitride layer. The specific structure of the dielectric layer 13 is not limited in the embodiment of the present application.

[0131] In one embodiment, the conductive passivation layer 122 includes a doped polysilicon layer, and the doped polysilicon layer is doped with N-type doping elements or P-type doping elements. In this way, the passivation contact structure 12 can have better conductive properties.

[0132] In one embodiment, the doped polysilicon layer is also doped with one or more of carbon, nitrogen, and oxygen, so as to increase the band gap of the film layer and further reduce light absorption, thereby improving the efficiency of the solar cell 1.

[0133] It is understood that the conductive passivation layer 122 may only include a doped polysilicon layer.

[0134] In one embodiment, the conductive passivation layer 122 may further include a doped microcrystalline silicon layer, wherein the doped microcrystalline silicon layer is doped with an N-type doping element or a P-type doping element.

[0135] In one embodiment, the conductive passivation layer 122 further includes a silicon carbide layer, which is disposed on a side of the doped polysilicon layer away from the semiconductor substrate 11. It is understood that the silicon carbide layer may also be doped with N-type doping elements or P-type doping elements.

[0136] By providing a silicon carbide layer, on the one hand, light absorption can be reduced, which is beneficial to improving the efficiency of the solar cell 1; on the other hand, in the process of making the first electrode 14, it can resist metal ablation, which is beneficial to reducing metal recombination. It should be noted that the first electrode 14 is in contact with at least one of the silicon carbide layer and the doped polysilicon layer.

[0137] In one embodiment, the material of the tunneling layer 121 includes at least one of silicon oxide, silicon nitride, intrinsic amorphous silicon, intrinsic polysilicon, aluminum oxide, aluminum nitride, phosphorus nitride, and titanium nitride.

[0138] In one embodiment, the material of the conductive passivation layer 122 includes at least one of polycrystalline silicon, microcrystalline silicon and silicon carbide. Furthermore, the conductive passivation layer 122 is doped with N-type doping elements or P-type doping elements.

[0139] In one embodiment, the solar cell 1 further comprises an emitter, a second electrode and a passivation layer. The emitter and the passivation layer are sequentially stacked on the first surface 111 of the semiconductor substrate 11, and the second electrode penetrates the passivation layer and is electrically connected to the emitter.

[0140] In one embodiment, the first electrode 14 includes at least one of silver and aluminum. In one example, the first electrode 14 includes silver and aluminum. Further, the first electrode can be made of silver-aluminum paste.

[0141] In one embodiment, the second electrode includes at least one of silver and aluminum. In one example, the second electrode includes silver and aluminum, and further, the second electrode can be made of silver-aluminum paste.

[0142] It should be noted that the applicant has tested the traditional TOPCon cell and the solar cell provided in the embodiment of the present application respectively, and the test results are shown in the following table:

[0143] Solar cell performance comparison table

[0144]

[0145] According to the above table, the solar cell provided by the embodiment of the present application can increase the short-circuit current by 0.19 mA / cm 2 , battery efficiency increased by 0.13%.

[0146] Second, refer to Figure 6-Figure 8 The production process, combined with Figure 9-Figure 15 The present application embodiment provides a method for preparing a solar cell, which can be used to prepare the solar cell 1 in the first aspect. The preparation method specifically includes the following steps:

[0147] S10: Provide a semiconductor substrate 11. The semiconductor substrate 11 includes a first surface 111 and a second surface 112 that are arranged opposite to each other. The semiconductor substrate 11 is provided with a plurality of passivation regions 11a and a plurality of passivation contact regions 11b, which are alternately arranged along a first direction X. The first direction X is perpendicular to the thickness direction of the semiconductor substrate 11. The semiconductor substrate 11 may be an N-type silicon substrate. It is understood that in this step, if Fig. 9 As shown, the semiconductor substrate 11 may be textured first, and after the texture is completed, as shown in FIG. Fig.10 As shown, an alkaline solution may be used to polish the second surface 112 of the semiconductor substrate 11. After polishing, pits 16 are formed on the second surface 112 of the semiconductor substrate 11.

[0148] S20: forming a plurality of passivation contact structures 12 on the second surface 112. The plurality of passivation contact structures 12 are correspondingly distributed in each passivation contact region 11b. The passivation contact structure 12 includes a conductive passivation layer 122.

[0149] S30: forming a dielectric layer 13 on the semiconductor substrate 11. The dielectric layer 13 at least covers the second surface 112 located in the passivation area 11a. The material of the dielectric layer 13 may include one or more of silicon oxide, aluminum oxide, silicon oxynitride, and silicon nitride. Exemplarily, the dielectric layer 13 may be manufactured by ALD (Atomic Layer Deposition), so that the dielectric layer 13 may be embedded in the "embedded groove" between the passivation contact structure 12 and the non-contact surface 11222 described above.

[0150] S40 : forming a plurality of first electrodes 14 on the plurality of passivation contact structures 12 . At least one first electrode 14 is disposed on a side of each passivation contact structure 12 away from the semiconductor substrate 11 .

[0151] The method for preparing a solar cell provided in an embodiment of the present application is equivalent to providing a passivation contact structure 12 arranged at intervals on the second surface 112. Compared with a traditional TOPCon cell, a passivation contact structure 12 is not provided on the second surface 112 located in the passivation area 11a, thereby reducing the coverage area of ​​the passivation contact structure 12 on the second surface 112, which is beneficial to reducing the absorption of long-wavelength light by the passivation contact structure 12, increasing the absorption of current, and improving the cell efficiency.

[0152] In addition, compared to the first related art, the solar cell 1 provided in the embodiment of the present application does not reduce the thickness of the passivation contact structure 12 when manufacturing the metal electrode, so the metal paste is not easy to burn through the passivation contact structure 12, thereby not affecting the passivation effect. Compared to the second related art, the solar cell 1 provided in the embodiment of the present application needs to completely remove the material of the passivation contact structure 12 in the passivation area 11a during the preparation process, so that the manufacturing process window is relatively large, the difficulty of preparation is reduced, and mass production is higher.

[0153] In one embodiment, referring to Figure 7 As shown, S20: forming a plurality of passivation contact structures 12 on the second surface 112, specifically comprising the following steps:

[0154] S21: A stacked tunneling material layer 21 and a conductive passivation material layer 22 are formed on the second surface 112. Exemplarily, the material of the tunneling material layer 21 may be a dielectric material, such as silicon oxide, aluminum oxide, silicon nitride, silicon oxynitride, magnesium fluoride, amorphous silicon, polycrystalline silicon, silicon carbide or titanium oxide. The material of the conductive passivation material layer 22 may be amorphous silicon, polycrystalline silicon, microcrystalline silicon, silicon carbide or the like. It is understandable that the tunneling material layer 21 and the conductive passivation material layer 22 may be prepared by processes such as ALD (Atomic Layer Deposition), PECVD (Plasma Enhanced Chemical Vapor Deposition), PEALD (Plasma Enhanced Atomic Layer Deposition), and LPCVD (Low Pressure Chemical Vapor Deposition). The structure after the tunneling material layer 21 and the conductive passivation material layer 22 are formed is as follows: Fig.11 shown.

[0155] S23: forming a patterned mask layer 232 on the conductive passivation material layer 22. The structure after the patterned mask layer 232 is formed is as follows: Fig.13 The material of the patterned mask layer 232 may be silicon oxide. Specifically, the oxide layer 231 on the surface of the conductive passivation material layer 22 may be processed by laser or etching process to form the patterned mask layer 232. It should be noted that the oxide layer 231 may be formed simultaneously in the process of S21.

[0156] S24: removing the tunneling material layer 21 and the conductive passivation material layer 22 located in the passivation region 11a to form a passivation contact structure 12. The structure of the passivation contact structure 12 after formation is as follows: Fig.14 As shown. Exemplarily, the above film layer can be removed by a wet etching process.

[0157] It should be noted that after removing the tunneling material layer 21 and the conductive passivation material layer 22 located in the passivation area 11a, the semiconductor substrate 11 located in the passivation area 11a can be polished with an alkaline solution, so that the depth of the second surface 112 of the passivation area 11a is deeper than the depth of the second surface 112 of the passivation contact area 11b. During the polishing process, the inner diameters of most of the pits 16, or even all of the pits 16, in the passivation area 11a can be enlarged, and the depths of the pits 16 can be reduced, which is conducive to reducing the roughness of the second surface 112 of the passivation area 11a.

[0158] In one embodiment, referring to Figure 7As shown, S21: after forming the stacked tunneling material layer 21 and the conductive passivation material layer 22 on the second surface 112, S23: before forming the patterned mask layer 232 on the conductive passivation material layer 22, the following steps are also included:

[0159] S22: Heat-treating the conductive passivation material layer 22 to form an initial diffusion layer 24. Fig.12 As shown, after the heat treatment, an initial diffusion layer 24 is formed in the semiconductor substrate 11.

[0160] It should be noted that the conductive passivation material layer 22 formed in the step S21 may contain doping elements or may not contain doping elements. When the conductive passivation material layer 22 contains doping elements, the heat treatment in the step S22 may activate the doping elements and further crystallize the conductive passivation material layer 22. Fig.11 As shown, when the conductive passivation material layer 22 formed in the S21 process contains doping elements, an oxide layer 231 will be formed on the surface of the conductive passivation material layer 22 simultaneously after the S21 process is completed.

[0161] When the conductive passivation material layer 22 does not contain doping elements, a doping source may be introduced during the heat treatment process of S22 to diffuse the doping elements into the conductive passivation material layer 22 and further crystallize the conductive passivation material layer 22 .

[0162] In one embodiment, if Figure 7 As shown, S24: after removing the tunneling material layer 21 and the conductive passivation material layer 22 located in the passivation region 11a to form the passivation contact structure 12, the following steps are also included:

[0163] S25: removing the initial diffusion layer 24 in the passivation region 11a to form the first diffusion layer 15. Specifically, the semiconductor substrate 11 may be polished with an alkaline solution to remove the initial diffusion layer 24 in the passivation region 11a. It is understood that the initial diffusion layer 24 in the passivation region 11a may not be removed.

[0164] In one embodiment, if Figure 8 As shown, S20: forming a plurality of passivation contact structures 12 on the second surface 112, specifically comprising the following steps:

[0165] S201: Form a stacked tunneling material layer 21 and a conductive passivation material layer 22 on the second surface 112. Exemplarily, the material of the tunneling material layer 21 can be a dielectric material, such as silicon oxide, aluminum oxide, silicon nitride, silicon oxynitride, magnesium fluoride, amorphous silicon, polycrystalline silicon, silicon carbide or titanium oxide. The conductive passivation material layer 22 can be an amorphous silicon layer. It is understandable that the tunneling material layer 21 and the conductive passivation material layer 22 can be prepared by processes such as ALD (Atomic Layer Deposition), PECVD (Plasma Enhanced Chemical Vapor Deposition), PEALD (Plasma Enhanced Atomic Layer Deposition), and LPCVD (Low Pressure Chemical Vapor Deposition). Fig.11 As shown, in this step, an oxide layer 231 may also be formed simultaneously. The oxide layer 231 is formed on the surface of the conductive passivation material layer 22 .

[0166] S202: forming a patterned mask layer 232 on the conductive passivation material layer 22. The structure after the patterned mask layer 232 is formed is as follows: Fig.13 Specifically, the oxide layer 231 on the surface of the conductive passivation material layer 22 may be processed by laser or etching process to form a patterned mask layer 232 .

[0167] S203: heat-treating the conductive passivation material layer 22 to form an initial diffusion layer 24. It should be noted that in this step, a thin oxide film is formed on the surface of the conductive passivation material layer 22 located in the passivation region 11a.

[0168] It should be noted that the conductive passivation material layer 22 formed in the step S201 may contain doping elements or may not contain doping elements. When the conductive passivation material layer 22 contains doping elements, the heat treatment in the step S202 may activate the doping elements and further crystallize the conductive passivation material layer 22. When the conductive passivation material layer 22 does not contain doping elements, a doping source may be introduced during the heat treatment process of S203 to diffuse the doping elements into the conductive passivation material layer 22 and further crystallize the conductive passivation material layer 22.

[0169] S204: removing the tunneling material layer 21 and the conductive passivation material layer 22 located in the passivation region 11a to form a passivation contact structure 12. The structure of the passivation contact structure 12 after formation is as follows: Fig.14As shown. Exemplarily, the above film layer can be removed by a wet etching process. It should be noted that, since there is a thin oxide film on the surface of the conductive passivation material layer 22 of the passivation area 11a, during the wet etching process, the oxide film helps to control the wet etching rate, thereby improving the accuracy of the wet etching process.

[0170] S205: removing the initial diffusion layer 24 in the passivation region 11a to form the first diffusion layer 15. Specifically, the semiconductor substrate 11 may be polished with an alkaline solution to remove the initial diffusion layer 24 in the passivation region 11a. It is understood that the initial diffusion layer 24 in the passivation region 11a may not be removed.

[0171] In a third aspect, an embodiment of the present application provides a photovoltaic assembly, comprising the solar cell in the first aspect.

[0172] For example, the photovoltaic module includes a plurality of solar cells, which can be connected in series by welding ribbons, so that the electricity generated by the individual solar cells can be collected for subsequent transmission. Of course, the solar cells can be arranged at intervals or stacked in a shingled form.

[0173] Furthermore, the photovoltaic module also includes an encapsulation layer and a cover plate, wherein the encapsulation layer is used to cover the surface of the battery string, and the cover plate is used to cover the surface of the encapsulation layer away from the battery string. The solar cells are electrically connected in the form of a whole piece or multiple pieces to form a plurality of battery strings, and the plurality of battery strings are electrically connected in series and / or in parallel. Specifically, in some embodiments, the plurality of battery strings can be electrically connected by a conductive tape. The encapsulation layer covers the surface of the solar cell. Exemplarily, the encapsulation layer can be an organic encapsulation film such as an ethylene-vinyl acetate copolymer film, a polyethylene octene co-elastic film, or a polyethylene terephthalate film. The cover plate can be a cover plate with a light-transmitting function such as a glass cover plate, a plastic cover plate, etc.

[0174] It should be understood that in the embodiments of the present application, at least part of the steps in the drawings may include multiple steps or multiple stages, and these steps or stages are not necessarily performed at the same time, but may be performed at different times. The execution order of these steps or stages is not necessarily sequential, but may be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0175] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0176] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A solar cell, characterized in that: include: A semiconductor substrate comprising a first surface and a second surface arranged opposite to each other; The second surface is a backlit surface; A plurality of passivation regions and a plurality of passivation contact regions are provided on the semiconductor substrate, and the plurality of passivation regions and the plurality of passivation contact regions are alternately arranged along a first direction; the first direction is perpendicular to a thickness direction of the semiconductor substrate; There is a first distance between the second surface located in the passivation area and the first surface, and there is a second distance between the second surface located in the passivation contact area and the first surface; the second distance is greater than the first distance; The roughness of the second surface located in the passivation region is less than the roughness of the second surface located in the passivation contact region; A plurality of passivation contact structures are provided on the second surface and are distributed correspondingly in each of the passivation contact regions; wherein the passivation contact structure comprises a conductive passivation layer; a dielectric layer, the dielectric layer at least covering the second surface located in the passivation region; and A plurality of first electrodes, at least one of the first electrodes being disposed on a side of each of the passivation contact structures away from the semiconductor substrate; The solar cell also includes a plurality of first diffusion layers disposed in the semiconductor substrate, the plurality of first diffusion layers being distributed correspondingly in the plurality of passivation contact regions, each of the first diffusion layers being in contact with the second surface; and a difference between the second distance and the first distance being greater than or equal to a dimension of the first diffusion layer along a thickness direction of the semiconductor substrate.

2. The solar cell according to claim 1, characterized in that The difference between the second distance and the first distance is greater than 1 μm.

3. The solar cell according to claim 1, characterized in that A plurality of pits are provided on the second surface; the pit located in the passivation area and having the deepest depth is defined as a first pit, and the pit located in the passivation contact area and having the deepest depth is defined as a second pit; The depth of the first pit is smaller than the depth of the second pit.

4. The solar cell according to claim 3, characterized in that: An inner diameter of the first recess is greater than an inner diameter of the second recess.

5. The solar cell according to claim 1, characterized in that: From the second surface to the first surface, the size of the passivation contact structure along the first direction gradually decreases.

6. The solar cell according to claim 5, characterized in that: The passivation contact structure further comprises a tunneling layer, wherein the tunneling layer is disposed between the conductive passivation layer and the semiconductor substrate; From the second surface to the first surface, the size of the conductive passivation layer along the first direction gradually decreases.

7. The solar cell according to claim 6, characterized in that: Each of the passivation contact structures is provided with a first electrode; a surface of the conductive passivation layer close to the tunneling layer is a first surface, and a surface of the conductive passivation layer away from the tunneling layer is a second surface; The size of the first surface along the first direction, the size of the second surface along the first direction, and the size of the first electrode along the first direction satisfy the following relationship: Wherein, W1 is the size of the first surface along the first direction, W2 is the size of the second surface along the first direction, and W3 is the size of the first electrode along the first direction.

8. The solar cell according to claim 1, characterized in that The dielectric layer also covers a surface of the passivation contact structure that is away from the semiconductor substrate.

9. The solar cell according to claim 8, characterized in that The second surface of the semiconductor substrate includes a first sub-surface, a second sub-surface and a connection surface; the first sub-surface is located in the passivation region, the second sub-surface is located in the passivation contact region, and the connection surface connects the adjacent first sub-surface and the second sub-surface; The dielectric layer also covers the connecting surface.

10. The solar cell according to claim 9, characterized in that: The second sub-surface includes a sub-contact surface and two non-contact surfaces, wherein the two non-contact surfaces are arranged on both sides of the sub-contact surface along the first direction; the passivation contact structure contacts the sub-contact surface; The dielectric layer also covers the non-contact surface.

11. The solar cell according to claim 1, characterized in that: The dielectric layer includes one or more of aluminum oxide, silicon nitride, and silicon oxynitride.

12. The solar cell according to claim 1, characterized in that The conductive passivation layer includes a doped polysilicon layer, and the doped polysilicon layer is doped with an N-type doping element or a P-type doping element.

13. The solar cell according to claim 12, characterized in that: The doped polysilicon layer is also doped with one or more of carbon, nitrogen and oxygen.

14. The solar cell according to claim 12, characterized in that: The conductive passivation layer further includes a silicon carbide layer, and the silicon carbide layer is disposed on a side of the doped polysilicon layer away from the semiconductor substrate.

15. The solar cell according to claim 1, characterized in that The first electrode includes at least one of silver and aluminum.

16. A method for preparing a solar cell, characterized in that: include: Providing a semiconductor substrate; the semiconductor substrate comprises a first surface and a second surface arranged opposite to each other; the second surface is a backlight surface; A plurality of passivation regions and a plurality of passivation contact regions are provided on the semiconductor substrate, and the plurality of passivation regions and the plurality of passivation contact regions are alternately arranged along a first direction; the first direction is perpendicular to a thickness direction of the semiconductor substrate; forming a plurality of passivation contact structures on the second surface; wherein the plurality of passivation contact structures are correspondingly distributed in each of the passivation contact regions; and the passivation contact structure comprises a conductive passivation layer; forming a dielectric layer on the semiconductor substrate; the dielectric layer at least covers the second surface located in the passivation region; A plurality of first electrodes are formed on the plurality of passivation contact structures; at least one first electrode is disposed on a side of each of the passivation contact structures away from the semiconductor substrate; The forming of a plurality of passivation contact structures on the second surface comprises: forming a stacked tunneling material layer and a conductive passivation material layer on the second surface; forming a patterned mask layer on the conductive passivation material layer; removing the tunneling material layer and the conductive passivation material layer located in the passivation region to form the passivation contact structure; After forming the stacked tunneling material layer and the conductive passivation material layer on the second surface, and before forming the patterned mask layer on the conductive passivation material layer, the method includes: performing a heat treatment on the conductive passivation material layer to form an initial diffusion layer; or, after forming the patterned mask layer on the conductive passivation material layer, and before removing the tunneling material layer and the conductive passivation material layer located in the passivation area to form the passivation contact structure, the method includes: performing a heat treatment on the conductive passivation material layer to form an initial diffusion layer; After the tunneling material layer and the conductive passivation material layer located in the passivation region are removed to form the passivation contact structure, the method further comprises: removing the initial diffusion layer located in the passivation region to form a first diffusion layer; Among them, there is a first distance between the second surface located in the passivation area and the first surface, and there is a second distance between the second surface located in the passivation contact area and the first surface; the second distance is greater than the first distance; the roughness of the second surface located in the passivation area is less than the roughness of the second surface located in the passivation contact area; a plurality of the first diffusion layers are arranged in the semiconductor substrate, and the plurality of the first diffusion layers are correspondingly distributed in the plurality of passivation contact areas, and each of the first diffusion layers is connected to the second surface; the difference between the second distance and the first distance is greater than or equal to the size of the first diffusion layer along the thickness direction of the semiconductor substrate.

17. A photovoltaic module, characterized in that: Comprising the solar cell according to any one of claims 1 to 15.

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