Sense amplifier, control method of sense amplifier and memory

Abstract

The present application relates to a sensitive amplifier, a control method for the sensitive amplifier and a memory. The sensitive amplifier is provided with an adjustment circuit between an amplifying circuit and a comparing circuit, and the initial voltage signal output by the amplifying circuit is reduced by the adjustment circuit to obtain an adjusted target voltage signal. When the comparing circuit is in a comparing state, the input unit in the comparing circuit is controlled by the adjusted target voltage signal, so that the transistors in the input unit are in different states; since the transistors in the input unit of the comparing circuit are in different working states, the current difference between the transistors will be much greater than the current margin caused by the process adaptation of the transistors in the latch unit of the comparing circuit, and the distortion caused by the process mismatch of the latch unit transistor can be overcome. The present application does not make much change to the circuit, has a small area, is easy to implement, and the memory including the sensitive amplifier of the present application is reliable.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to a sensitive amplifier, a control method for the sensitive amplifier, and a memory. Background Art

[0002] The sense amplifier is an important module in analog CMOS integrated circuits and is closely related to the memory cell. The sense amplifier is mainly used to detect and judge the data content in the selected memory cell.

[0003] The traditional sensitive amplifier circuit consists of an amplifier and a comparator, where the amplifier is powered by an analog voltage and the comparator is powered by a digital voltage. Due to the limitation of the analog circuit power supply voltage range, the voltage output from the amplifier to the comparator is generally higher. If there is a process mismatch problem with the transistors in the comparator, the comparator will be distorted and the output comparison result will be inaccurate.

[0004] In order to solve the comparator distortion caused by the mismatch of the device process, the traditional method is to set a low-voltage power supply for the amplifier separately so that the voltage output by the amplifier can ensure that there is a large difference in the transistor current in the comparator. However, this method requires an additional low-voltage power supply, which wastes the layout area. The additional low-voltage power supply also increases the metal interconnection lines in the layout, increasing the complexity of the layout design. Summary of the invention

[0005] Based on this, it is necessary to provide a sense amplifier with a small circuit area and simple connection, a control method for the sense amplifier, and a memory.

[0006] In a first aspect, the present application provides a sensitive amplifier, comprising:

[0007] an amplifier circuit, used for outputting an initial voltage signal;

[0008] The adjustment circuit is connected to the amplifier circuit and is used to reduce the initial voltage signal output by the amplifier circuit to obtain an adjusted target voltage signal;

[0009] A comparison circuit is connected to the adjustment circuit. The comparison circuit includes an input unit and a latch unit. The comparison circuit is used to control the input unit according to a target voltage signal when in a comparison state, and output a comparison result through the latch unit; wherein the target voltage signal is used to make the transistors in the input unit be in different states.

[0010] In one embodiment, the adjustment circuit is specifically used to: divide the initial voltage signal to obtain a target voltage signal; or,

[0011] By adjusting the size parameters of the transistors in the adjustment circuit, the initial voltage signal is adjusted to obtain the target voltage signal;

[0012] Wherein, the initial voltage signal and the target voltage signal are both differential signals, and the adjustment circuit includes a first adjustment sub-circuit and a second adjustment sub-circuit.

[0013] In one embodiment, the target voltage signal includes a first target voltage signal and a second target voltage signal, the first adjustment subcircuit includes a first capacitor and a first switch tube group, and the first adjustment subcircuit is used to charge the first capacitor when the comparison circuit is in a latched state under the control of the first switch tube group, and output the first target voltage signal when the comparison circuit is in a comparison state;

[0014] The second adjustment subcircuit includes a second capacitor and a second switch tube group. The second adjustment subcircuit is used to charge the second capacitor when the comparison circuit is in a latched state under the control of the second switch tube group, and output a second target voltage signal when the comparison circuit is in a comparison state.

[0015] In one embodiment, the first adjustment subcircuit includes a first N-type transistor, a second N-type transistor and a third N-type transistor, the first N-type transistor is connected to the amplification circuit, the second N-type transistor and the third N-type transistor respectively, and the second N-type transistor is also connected to the comparison circuit;

[0016] The second adjustment subcircuit includes a fourth N-type transistor, a fifth N-type transistor and a sixth N-type transistor. The fourth N-type transistor is connected to the amplification circuit, the fifth N-type transistor and the sixth N-type transistor respectively, and the fifth N-type transistor is also connected to the comparison circuit.

[0017] In one embodiment, the first adjustment subcircuit includes a first P-type transistor and a seventh N-type transistor, and the first P-type transistor is connected to the amplification circuit, the seventh N-type transistor and the comparison circuit respectively;

[0018] The second adjustment sub-circuit includes a second P-type transistor and an eighth N-type transistor, and the second P-type transistor is connected to the amplification circuit, the eighth N-type transistor and the comparison circuit respectively.

[0019] In a second aspect, the present application provides a sense amplifier control method, which is applied to the sense amplifier provided in the first aspect above, wherein the sense amplifier includes an amplification circuit, an adjustment circuit, and a comparison circuit, wherein the comparison circuit includes an input unit and a latch unit, and the method includes the following steps:

[0020] The amplifier circuit outputs an initial voltage signal;

[0021] The adjustment circuit reduces the initial voltage signal output by the amplifier circuit to obtain an adjusted target voltage signal;

[0022] When the comparison circuit is in a comparison state, the input unit is controlled according to the target voltage signal, and the comparison result is output through the latch unit; wherein the target voltage signal is used to make the transistors in the input unit in different states.

[0023] In one embodiment, the target voltage signal includes a first target voltage signal and a second target voltage signal, and the adjustment circuit reduces the initial voltage signal output by the amplification circuit to obtain the adjusted target voltage signal, including:

[0024] Dividing the initial voltage signal to obtain a target voltage signal; or,

[0025] By adjusting the size parameters of the transistors in the adjustment circuit, the initial voltage signal is adjusted to obtain the target voltage signal;

[0026] Wherein, the initial voltage signal and the target voltage signal are both differential signals.

[0027] In one embodiment, the adjustment circuit includes a first adjustment subcircuit and a second adjustment subcircuit, the first adjustment subcircuit includes a first capacitor and a first switch tube group, the second adjustment subcircuit includes a second capacitor and a second switch tube group, and the initial voltage signal is divided to obtain a target voltage signal, including:

[0028] Under the control of the first switch tube group, when the comparison circuit is in a latched state, the first capacitor is charged, and when the comparison circuit is in a comparison state, a first target voltage signal is output;

[0029] Under the control of the second switch tube group, when the comparison circuit is in a latched state, the second capacitor is charged, and when the comparison circuit is in a comparison state, a second target voltage signal is output.

[0030] In one embodiment, adjusting the size parameters of transistors in the adjustment circuit to adjust the initial voltage signal to obtain the target voltage signal includes:

[0031] The width-to-length ratio of the transistor in the adjustment circuit is adjusted to change the gain of the adjustment circuit output to obtain a target voltage signal.

[0032] In a third aspect, the present application provides a memory, which includes the sensitive amplifier provided in the first aspect.

[0033] In the above-mentioned sensitive amplifier, control method of the sensitive amplifier and memory, the sensitive amplifier is provided with an adjustment circuit between the amplification circuit and the comparison circuit, and the initial voltage signal output by the amplification circuit is reduced by the adjustment circuit to obtain an adjusted target voltage signal. When the comparison circuit is in a comparison state, the input unit in the comparison circuit is controlled by the adjusted target voltage signal, so that the transistors in the input unit are in different states; since the transistors of the input unit of the comparison circuit are in different working states, the current difference between the transistors will be much larger than the current margin of the transistors in the latch unit of the comparison circuit due to process adaptation, and the distortion caused by the process mismatch of the latch unit transistor can be overcome. The present application does not make much change to the circuit, has a small area, is easy to implement, and the memory including the sensitive amplifier of the present application is reliable. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0035] Figure 1 is a schematic diagram of a sensitive amplifier module according to an embodiment;

[0036] Figure 2 is a circuit diagram of a sense amplifier according to an embodiment;

[0037] Figure 3 is a circuit diagram of a sense amplifier according to another embodiment;

[0038] Figure 4 is a circuit diagram of a sense amplifier according to another embodiment;

[0039] Figure 5 FIG. 4 is a flow chart of a control method of a sense amplifier according to an embodiment of the present invention.

[0040] Description of reference numerals:

[0041] 100. Amplification circuit; 200. Adjustment circuit; 300. Comparison circuit. DETAILED DESCRIPTION

[0042] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0043] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0044] It is understood that the terms "first", "second", etc. used in this application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish a first element from another element. For example, without departing from the scope of this application, a first resistor may be referred to as a second resistor, and similarly, a second resistor may be referred to as a first resistor. Both the first resistor and the second resistor are resistors, but they are not the same resistor.

[0045] It can be understood that the “connection” in the following embodiments should be understood as “electrical connection”, “communication connection”, etc. if the connected circuits, modules, units, etc. have electrical signals or data transmission between each other.

[0046] It can be understood that “at least one” means one or more, “plurality” means two or more, and “at least a portion of an element” means a part or all of an element.

[0047] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, the term "and / or" used in this specification includes any and all combinations of the relevant listed items.

[0048] The sense amplifier is an important module in analog CMOS integrated circuits, which is closely related to the memory unit and is mainly used to detect and judge the data content in the memory unit. The traditional sense amplifier includes an amplifier circuit 100 and a comparison circuit 300, wherein the amplifier circuit 100 is powered by an analog voltage chip and outputs a digital voltage to control the operation of the comparison unit 300. However, the voltage output by the amplifier circuit 100 is generally high. When controlling the comparison circuit 300, if there is a process mismatch problem in the transistors in the comparison circuit 300, the output signal of the comparison circuit 300 will be distorted and the reliability will be reduced.

[0049] In order to improve the reliability of the output signal of the sensitive amplifier, such as Figure 1As shown, a sensitive amplifier of an embodiment includes an amplifier circuit 100, an adjustment circuit 200 and a comparison circuit 300, wherein the amplifier circuit 100 is used to output an initial voltage signal; the adjustment circuit 200 is connected to the amplifier circuit 100, and is used to reduce the initial voltage signal output by the amplifier circuit 100 to obtain an adjusted target voltage signal; the comparison circuit 300 is connected to the adjustment circuit 200, and the comparison circuit 300 includes an input unit and a latch unit. The comparison circuit 300 is used to control the input unit according to the target voltage signal when in a comparison state, and output a comparison result through the latch unit; wherein the target voltage signal is used to make the transistors in the input unit be in different states.

[0050] by Figure 2 Taking the circuit diagram shown in FIG. 1 as an example, SA_SENSE represents the amplifier circuit 100, SA_COMP represents the comparison circuit 300, and the dotted box in the amplifier circuit 100 represents the adjustment circuit 200. Figure 2 As shown, the amplifier circuit 100 includes a first transistor pair, a second transistor pair, a third transistor pair and resistors R1 and R2. The first transistor pair includes PMOS transistors M15 and M16, the second transistor pair includes NMOS transistors M13 and M14, and the third transistor pair includes NMOS transistors M11 and M12. The gates of the transistors (M15 and M16) in the first transistor pair are connected to the read enable signal, the sources are connected to the power supply, and the drains are connected to one end of the resistors R1 and R2 respectively. The other ends of the resistors R1 and R2 are connected to the drains of the transistors (M13 and M14) in the second transistor pair. The gates of the transistors in the second transistor pair are connected to high-level signals, the sources are connected to the drains of the transistors (M11 and M12) in the third transistor pair, the gates of the transistors in the third transistor pair are connected to low-level signals, and the sources are connected to the power supply VSS. The second transistor pair and the second transistor pair are also connected to the reference power supply. The differential output signals INN and INP are drawn between the second transistor pair and the resistor, and the differential signals are input to the comparison circuit 300.

[0051] The power supply of the amplifier circuit 100 is VDD2, which is the power supply for the analog circuit, and its voltage range is approximately 2.3V to 4.8V. The initial voltage signals output by the amplifier circuit 100 are represented as INP and INN, where INP=VDD2-(I1-Icell)*R1, INN=VDD2-(I2- Iref) *R2, and the two voltages are based on VDD2 and range from approximately 1.3V to 4.8V.

[0052] The comparison circuit 300 includes an input unit, a latch unit and a reset switch unit. Figure 2For example, the input unit includes NMOS tubes M5 and M6, the latch unit includes NMOS tubes M1-M2 and PMOS tubes M3-M4, the reset switch unit includes PMOS tubes M7-M8, M10-M11, and the comparison circuit 300 also includes NMOS tube M9 as a tail current source, which is also used to reset the latch unit.

[0053] The comparison circuit 300 mainly includes a latch state and a comparison state, such as Figure 2 As shown, when the comparison circuit 300 is in the latched state, CLK_EN is at a low level, the transistors M1, M2, M3, M4, and M9 are turned off, the transistors M7, M8, M10, and M11 are turned on, and the Q1, Q2, Q3, and Q4 nodes are all at high levels; when the comparison circuit 300 is in the comparison state, CLK_EN changes from a low level to a high level, at this time, the transistors M7, M8, M10, and M11 are turned off, the transistors M5, M6, and M9 are turned on, and the states of the transistors M1, M2, M3, and M4 are determined by the transistors M5 and M6. The gates of transistors M5 and M6 receive differential signals INN and INP output by the amplifier circuit 100. Since the range of INN and INP is 1.3V to 4.8V, one of transistors M5 and M6 is in a saturation region and the other is in a near-saturation region, resulting in a small current difference between transistors M5 and M6. If the process of transistors M1 and M3 is mismatched, the current margin caused by the process mismatch of transistors M1 and M3 will be greater than the current difference between transistors M5 and M6, resulting in a distorted output result of the comparison circuit 300.

[0054] The present application provides a sensitive amplifier, in which the initial voltage signal output by the amplifier circuit 100 is adjusted to obtain a reduced target voltage signal, which can make the transistors M5 and M6 of the input unit of the comparison circuit 300 in different working states, such as one of the transistors is in the saturation region and the other is in the linear region, so that the current difference between the transistors M5 and M6 will be much larger than the current margin caused by the process adaptation of the transistors in the latch unit of the comparison circuit. At this time, the current difference between the input unit transistors is rapidly amplified by the positive feedback latch stage of the latch unit, and one end of the output is pulled down to a low level, while the other end remains at a high level unchanged. This embodiment overcomes the distortion caused by the process mismatch of the latch unit transistor. The sensitive amplifier of this embodiment does not make much change to the circuit, has a small area, is easy to implement, and has high reliability.

[0055] In a specific embodiment, the adjustment circuit 200 is specifically used to: divide the initial voltage signal to obtain a target voltage signal; or, adjust the initial voltage signal by adjusting the size parameters of the transistors in the adjustment circuit 200 to obtain the target voltage signal; wherein the initial voltage signal and the target voltage signal are both differential signals, and the adjustment circuit 200 includes a first adjustment sub-circuit and a second adjustment sub-circuit.

[0056] Among them, the initial voltage signal is divided, and a voltage dividing circuit can be set to make the voltage signal output to the comparison circuit 300 lower than the initial voltage signal. Alternatively, the initial voltage signal is reduced by adjusting the size parameters of the transistor. For example, the size parameter can be the width-to-length ratio of the transistor, and the width-to-length ratio of the transistor is related to the conduction characteristics and cut-off characteristics of the transistor. When the width-to-length ratio is small, the channel width is small, and the space for electrons to move in the channel is limited, so the current density is large and the conduction ability is strong; when the width-to-length ratio is large, the channel width is large, the space for electrons to move in the channel is relatively large, the current density is small, and the conduction ability of the transistor is weak. By adjusting the size parameters of the transistor in the adjustment circuit 200, the reduced target voltage signal can be obtained.

[0057] It should be noted that this embodiment has no limitation on the composition of the adjustment circuit 200 , as long as it can adjust and reduce the initial voltage signal output by the amplifier circuit 100 to obtain a target voltage signal to overcome the device mismatch in the comparison circuit 300 .

[0058] In an exemplary embodiment, Figure 2 As shown, the target voltage signal includes a first target voltage signal and a second target voltage signal, the first adjustment subcircuit includes a first capacitor and a first switch tube group, and the first adjustment subcircuit is used to charge the first capacitor under the control of the first switch tube group when the comparison circuit 300 is in a latched state, and output the first target voltage signal when the comparison circuit 300 is in a comparison state; the second adjustment subcircuit includes a second capacitor and a second switch tube group, and the second adjustment subcircuit is used to charge the second capacitor under the control of the second switch tube group when the comparison circuit 300 is in a latched state, and output the second target voltage signal when the comparison circuit 300 is in a comparison state.

[0059] like Figure 2 As shown, the first adjustment sub-circuit includes a first switch tube group composed of transistors M17-M20 and a first capacitor Cp1, wherein the first switch tube group includes NMOS tubes M17 and M20, and PMOS tubes M18 and M19; the second adjustment sub-circuit includes a second switch tube group composed of transistors M21-M24 and a second capacitor Cp2, wherein the second switch tube group includes NMOS tubes M21 and M24, and PMOS tubes M22 and M23.

[0060] exist Figure 2In the circuit, if the comparison circuit 300 is in the latched state, CLK_EN is at a low level, the comparison circuit 300 remains unchanged, the transistors M18, M19, M22, and M23 in the adjustment circuit 200 are turned on, and the transistors M17, M20, M21, and M24 are turned off, and the output voltage charges the capacitors Cp1 and Cp2; if the comparison circuit 300 is in the amplified state, CLK_EN changes from a low level to a high level, at which time the transistors M18, M19, M22, and M23 are turned off, and the transistors M 17. M20, M21, and M24 are turned on. Since the voltages across capacitors Cp1 and Cp2 cannot change suddenly, in the differential target voltage signals INN and INP output at this time, INP=[VDD2-(I1-Icell)*R1] / 2, INN=[VDD2-(I2-Iref)*R2] / 2, that is, the adjustment circuit 200 reduces the voltage range of the initial voltage signal output by the amplifier circuit 100, and the range of the target voltage signal after the reduction is 0.7V~2.4V.

[0061] In another exemplary embodiment, Figure 3 As shown, the first adjustment subcircuit includes a first N-type transistor, a second N-type transistor and a third N-type transistor, the first N-type transistor is respectively connected to the amplifier circuit 100, the second N-type transistor and the third N-type transistor, and the second N-type transistor is also connected to the comparison circuit 300; the second adjustment subcircuit includes a fourth N-type transistor, a fifth N-type transistor and a sixth N-type transistor, the fourth N-type transistor is respectively connected to the amplifier circuit 100, the fifth N-type transistor and the sixth N-type transistor, and the fifth N-type transistor is also connected to the comparison circuit 300.

[0062] like Figure 3 As shown, the first adjustment sub-circuit includes NMOS transistors M30-M32, the gate and drain of transistor M31 are connected to the amplifier circuit 100, the source of M31 is respectively connected to the drain of M30 and the drain of M32, the gate of M30 and the gate of M32 are both connected to CLK_EN, the source of M32 is connected to the power supply VSS, and the source of M30 outputs a first target voltage signal; the second adjustment sub-circuit includes NMOS transistors M27-M29, the gate and drain of transistor M27 are both connected to the amplifier circuit 100, the source of M27 is respectively connected to the drain of M29 and the drain of M28, the gate of M29 and the gate of M28 are both connected to CLK_EN, the source of M28 is connected to the power supply VSS, and the source of M29 outputs a second target voltage signal.

[0063] exist Figure 3In the circuit, when the comparison circuit 300 is in the latched state, CLK_EN is at a low level, the comparison circuit 300 remains unchanged, M31 and M27 in the adjustment circuit 200 are turned on, and M28, M29, M30, and M32 are turned off. At this time, the differential target voltage signals INN and INP have no output; when the comparison circuit 300 is in the amplified state, CLK_EN changes from a low level to a high level, at this time, transistors M27-M32 are all turned on, wherein transistors M27 and M32 work in the saturation region, and at this time, the gain of the first adjustment sub-circuit is It is expressed as:

[0064]

[0065] The gain of the second adjustment subcircuit It is expressed as:

[0066]

[0067] in, , , , denote the width-to-length ratios of transistors M28, M27, M32, and M31, respectively, represents the transconductance of transistor M27, represents the reverse transconductance of transistor M27, represents the transconductance of transistor M31, represents the reverse transconductance of transistor M31.

[0068] By selecting NMOS transistors of appropriate sizes in the adjustment circuit 200 , the voltages of the differential target voltage signals INN and INP can be reduced to an appropriate range, thereby avoiding output distortion caused by transistor process mismatch of the comparison circuit 300 .

[0069] In an exemplary embodiment, Figure 4 As shown, the first adjustment subcircuit includes a first P-type transistor and a seventh N-type transistor, and the first P-type transistor is respectively connected to the amplifier circuit 100, the seventh N-type transistor and the comparison circuit 300; the second adjustment subcircuit includes a second P-type transistor and an eighth N-type transistor, and the second P-type transistor is respectively connected to the amplifier circuit 100, the eighth N-type transistor and the comparison circuit 300.

[0070] like Figure 4As shown, the first adjustment sub-circuit includes a PMOS transistor M39 and an NMOS transistor M40, the source of the transistor M39 is connected to the amplifier circuit 100, the gate and drain of the transistor M39 are connected to the drain of the transistor M40, and outputs a first target voltage signal, the gate of the transistor M40 is connected to CLK_EN, and the source is connected to the power supply VSS; the second adjustment sub-circuit includes a PMOS transistor M37 and an NMOS transistor M38, the source of the transistor M37 is connected to the amplifier circuit 100, the gate and drain of the transistor M37 are connected to the drain of the transistor M38, and outputs a second target voltage signal, the gate of the transistor M38 is connected to CLK_EN, and the source is connected to the power supply VSS.

[0071] exist Figure 4 In the circuit, if the comparison circuit 300 is in the latched state, CLK_EN is at a low level, the comparison circuit 300 remains unchanged, and the transistors M37-M40 in the adjustment circuit 200 are all turned off. At this time, the differential target voltage signals INN and INP have no output; if the comparison circuit 300 is in the amplification state, CLK_EN changes from a low level to a high level, at this time, the transistors M37-M40 are all turned on, wherein the transistors M37 and M37 work in the saturation region, and at this time, the gain of the first adjustment sub-circuit It is expressed as:

[0072]

[0073] The gain of the second adjustment subcircuit It is expressed as:

[0074]

[0075] in, , , , denote the width-to-length ratios of transistors M38, M37, M40, and M39, respectively, represents the mobility of the NMOS transistor, Represents the mobility of the PMOS transistor.

[0076] By selecting NMOS transistors of appropriate sizes in the adjustment circuit 200 , the voltages of the differential target voltage signals INN and INP can be reduced to an appropriate range, thereby avoiding output distortion caused by transistor process mismatch of the comparison circuit 300 .

[0077] It is understandable that the adjustment circuit 200 may also be in other forms, not limited to the forms mentioned in the above embodiments, as long as it can achieve the function of adjusting the initial voltage signal.

[0078] In one embodiment, Figure 5A method for controlling a sensitive amplifier is disclosed. The method for controlling a sensitive amplifier is applied to the above-mentioned sensitive amplifier circuit. The sensitive amplifier includes an amplifying circuit 100, an adjusting circuit 200 and a comparing circuit 300. The comparing circuit 300 includes an input unit and a latch unit. The method includes the following steps 502 to 506. Among them:

[0079] Step 502: the amplifier circuit outputs an initial voltage signal.

[0080] Step 504: the adjustment circuit reduces the initial voltage signal output by the amplifier circuit to obtain an adjusted target voltage signal.

[0081] Step 506: When the comparison circuit is in the comparison state, the input unit is controlled according to the target voltage signal, and the comparison result is output through the latch unit; wherein the target voltage signal is used to make the transistors in the input unit in different states.

[0082] Combination Figure 1 In the sensitive amplifier shown, the adjustment circuit 200 adjusts the initial voltage signal output by the amplifier circuit 100 to obtain an adjusted target voltage signal.

[0083] When the comparison circuit 300 works in the comparison state, the transistors in the input unit are controlled according to the target voltage signal, so that the transistors in the input unit are in a non-passing state, for example, in the saturation region and the linear region respectively, and then the comparison result is output through the latch unit. At this time, since the current difference between the transistors in the input unit of the comparison circuit 300 is much larger than the current margin of the transistors in the latch unit of the comparison circuit 300 due to process adaptation, the distortion caused by the process mismatch of the latch unit transistor is overcome. This embodiment does not make much change to the circuit, has a small area, is easy to implement, and the memory including the sensitive amplifier of the present application has reliability.

[0084] In a specific embodiment, the target voltage signal includes a first target voltage signal and a second target voltage signal, and the adjustment circuit 200 reduces the initial voltage signal output by the amplifier circuit 100 to obtain an adjusted target voltage signal, including: dividing the initial voltage signal to obtain the target voltage signal; or, adjusting the size parameters of the transistors in the adjustment circuit 200 to adjust the initial voltage signal to obtain the target voltage signal; wherein the initial voltage signal and the target voltage signal are both differential signals.

[0085] Exemplarily, the initial voltage signal is adjusted to obtain the adjusted target voltage signal by dividing the initial voltage signal to reduce the initial voltage signal, such as charging the capacitor in the latch state of the comparison circuit 300 by controlling the switch tube to output the reduced target voltage signal in the comparison state. In addition, the adjustment circuit 200 of this embodiment can also adjust the size parameters of the transistor to change the gain of the adjustment circuit 200 to adjust the initial voltage signal and obtain the reduced target voltage signal.

[0086] The adjustment circuit 200 of this embodiment is combined with the working state of the comparison circuit 300 during operation, and is simple to control. It is relatively simple to improve the distortion caused by device mismatch and improve the reliability of the circuit.

[0087] In an exemplary embodiment, the adjustment circuit 200 includes a first adjustment sub-circuit and a second adjustment sub-circuit, the first adjustment sub-circuit includes a first capacitor and a first switch tube group, the second adjustment sub-circuit includes a second capacitor and a second switch tube group, and the initial voltage signal is divided to obtain a target voltage signal, including: under the control of the first switch tube group, when the comparison circuit 300 is in a latched state, the first capacitor is charged, and when the comparison circuit 300 is in a comparison state, the first target voltage signal is output; under the control of the second switch tube group, when the comparison circuit 300 is in a latched state, the second capacitor is charged, and when the comparison circuit 300 is in a comparison state, the second target voltage signal is output.

[0088] Exemplarily, the target voltage signal is a differential signal, and the first adjustment subcircuit and the second adjustment subcircuit are respectively connected to the differential signal. The structure and working principle of the first adjustment subcircuit and the second adjustment subcircuit are the same. Taking the first adjustment subcircuit as an example, a first switch tube group and a first capacitor are set in the first adjustment subcircuit. By controlling the first switch tube group, when the comparison circuit 300 is in a latched state, the first capacitor is charged. When the comparison circuit 300 is in an amplified state, since the voltage across the first capacitor cannot change suddenly, the initial voltage signal is adjusted, and the first target voltage signal after the reduction is output. The working principle of the second adjustment subcircuit is similar to that of the first adjustment subcircuit, which will not be repeated here.

[0089] In another exemplary embodiment, the initial voltage signal is adjusted by adjusting the size parameters of the transistors in the adjustment circuit 200 to obtain the target voltage signal, including: adjusting the width-to-length ratio of the transistors in the adjustment circuit 200 to change the gain output by the adjustment circuit 200 to obtain the target voltage signal.

[0090] Illustratively, in order to reduce the initial voltage signal, the present embodiment may also adjust the size parameters of the transistors in the adjustment circuit 200 to obtain a reduced target voltage signal, such as selecting a suitable width-to-length ratio of the transistors to reduce the output differential target voltage signal to a suitable range.

[0091] To ensure the feasibility of the scheme of the present application, a circuit simulation was performed on the sensitive amplifier of the present application. According to the simulation results, the output differential voltage signal range was reduced from the previous 1.3V-4.8V to 0.7V-2.3V, which matched the theoretical calculation results. In other words, the sensitive amplifier of this embodiment was verified to be feasible after simulation.

[0092] In one embodiment, a memory is also disclosed. The memory includes the sensitive amplifier disclosed in the above embodiment.

[0093] Including the sensitive amplifier disclosed in the above embodiment in the memory can effectively solve the problem of sensitive amplifier output distortion caused by the unavoidable mismatch caused by the process, and the circuit modification is small, the layout area is small, the technical implementation and manufacturing are simple, and the reliability is high.

[0094] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic description of the above terms does not necessarily refer to the same embodiment or example.

[0095] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0096] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A sensitive amplifier, It is characterized in that include: an amplifier circuit, used for outputting an initial voltage signal; an adjustment circuit, connected to the amplifying circuit, and used to reduce the initial voltage signal output by the amplifying circuit to obtain an adjusted target voltage signal; a comparison circuit connected to the adjustment circuit, the comparison circuit comprising an input unit and a latch unit, the comparison circuit being used to control the input unit according to the target voltage signal when in a comparison state, and output a comparison result through the latch unit; wherein the target voltage signal is used to make the transistors in the input unit be in different states; The adjustment circuit is specifically used to: divide the initial voltage signal to obtain the target voltage signal; or, adjust the initial voltage signal by adjusting the size parameters of the transistors in the adjustment circuit to obtain the target voltage signal; wherein the initial voltage signal and the target voltage signal are both differential signals, and the adjustment circuit includes a first adjustment sub-circuit and a second adjustment sub-circuit.

2. The sense amplifier according to claim 1, It is characterized in that The size parameter includes a width-to-length ratio of the transistor.

3. The sense amplifier according to claim 1, It is characterized in that The target voltage signal includes a first target voltage signal and a second target voltage signal, the first adjustment subcircuit includes a first capacitor and a first switch tube group, and the first adjustment subcircuit is used to charge the first capacitor when the comparison circuit is in a latched state under the control of the first switch tube group, and output the first target voltage signal when the comparison circuit is in a comparison state; The second adjustment subcircuit includes a second capacitor and a second switch tube group. The second adjustment subcircuit is used to charge the second capacitor when the comparison circuit is in a latched state and output the second target voltage signal when the comparison circuit is in a comparison state under the control of the second switch tube group.

4. The sense amplifier according to claim 3, It is characterized in that The first switch group includes N-type transistors M17 and M20, and P-type transistors M18 and M19; the second switch group includes N-type transistors M21 and M24, and P-type transistors M22 and M23; When the comparison circuit is in a latched state, transistors M18, M19, M22, and M23 are turned on, and transistors M17, M20, M21, and M24 are turned off, so that the first capacitor and the second capacitor are charged; When the comparison circuit is in the comparison state, transistors M18, M19, M22, and M23 are turned off, and transistors M17, M20, M21, and M24 are turned on. The adjustment circuit reduces the voltage range of the initial voltage signal output by the amplifier circuit to obtain the first target voltage signal and the second target voltage signal.

5. The sense amplifier according to claim 1, It is characterized in that The first adjustment subcircuit includes a first N-type transistor, a second N-type transistor and a third N-type transistor, the first N-type transistor is connected to the amplification circuit, the second N-type transistor and the third N-type transistor respectively, and the second N-type transistor is also connected to the comparison circuit; The second adjustment subcircuit includes a fourth N-type transistor, a fifth N-type transistor and a sixth N-type transistor, the fourth N-type transistor is connected to the amplification circuit, the fifth N-type transistor and the sixth N-type transistor respectively, and the fifth N-type transistor is also connected to the comparison circuit.

6. The sense amplifier according to claim 1, It is characterized in that The first adjustment subcircuit includes a first P-type transistor and a seventh N-type transistor, and the first P-type transistor is connected to the amplification circuit, the seventh N-type transistor and the comparison circuit respectively; The second adjustment sub-circuit includes a second P-type transistor and an eighth N-type transistor, and the second P-type transistor is connected to the amplifying circuit, the eighth N-type transistor and the comparing circuit respectively.

7. A sensitive amplifier control method, It is characterized in that Applied to the sense amplifier according to any one of claims 1 to 6, the sense amplifier comprises an amplification circuit, an adjustment circuit and a comparison circuit, the comparison circuit comprises an input unit and a latch unit, and the method comprises the following steps: The amplifying circuit outputs an initial voltage signal; The adjustment circuit reduces the initial voltage signal output by the amplifier circuit to obtain an adjusted target voltage signal; When the comparison circuit is in a comparison state, the input unit is controlled according to the target voltage signal, and a comparison result is output through the latch unit; wherein the target voltage signal is used to make the transistors in the input unit in different states; The adjusting circuit reduces the initial voltage signal output by the amplifying circuit to obtain an adjusted target voltage signal, including: The target voltage signal is obtained by dividing the initial voltage signal; or, the initial voltage signal is adjusted by adjusting the size parameters of the transistors in the adjustment circuit to obtain the target voltage signal; wherein the initial voltage signal and the target voltage signal are both differential signals.

8. The method according to claim 7, It is characterized in that The target voltage signal includes a first target voltage signal and a second target voltage signal, the adjustment circuit includes a first adjustment subcircuit and a second adjustment subcircuit, the first adjustment subcircuit includes a first capacitor and a first switch tube group, the second adjustment subcircuit includes a second capacitor and a second switch tube group, and the initial voltage signal is divided to obtain the target voltage signal, including: Under the control of the first switch tube group, when the comparison circuit is in a latched state, the first capacitor is charged, and when the comparison circuit is in a comparison state, the first target voltage signal is output; Under the control of the second switch tube group, when the comparison circuit is in a latched state, the second capacitor is charged, and when the comparison circuit is in a comparison state, the second target voltage signal is output.

9. The method according to claim 7, It is characterized in that The adjusting of the initial voltage signal by adjusting the size parameters of the transistors in the adjusting circuit to obtain the target voltage signal includes: The width-to-length ratio of transistors in the adjustment circuit is adjusted to change the gain output by the adjustment circuit to obtain the target voltage signal.

10. A memory, It is characterized in that Comprising the sensitive amplifier according to any one of claims 1-6.

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