A power supply system for security chip

Abstract

The present invention discloses a power supply system applied to a security chip, including a configurable frequency divider module, a bandgap reference module, a low-power reference module, a reference storage module, a low-power voltage regulator module and a high-power voltage regulator module; CLK is a low-frequency clock input signal, EN_HP is a sleep mode enable input signal, CLK and EN_HP input signals to the configurable frequency divider module; when EN_HP is at a high level, it is in normal mode, and when EN_HP is at a low level, it is in sleep mode; EN_LP is an enable input signal for a low-power voltage regulator module, which is enabled at a high level and is always at a high level; the outputs of the low-power voltage regulator module and the high-power voltage regulator module are short-circuited to provide a digital circuit power supply VDD. The present invention uses a configurable frequency divider to adjust the proportion of high-power modules such as a bandgap reference source being turned on, thereby reducing the overall power consumption of the security chip; and uses a capacitor to store the reference voltage when the bandgap reference source is turned on, thereby improving the output accuracy of the voltage regulator in sleep mode.

Description

Technical Field

[0001] The present invention belongs to the technical field of information security chips, and more specifically, relates to a power supply system applied to a security chip. Background Art

[0002] With the development of information technology, the application scope of security chips is becoming more and more extensive. Its main functions include secure storage, encryption, decryption and identity recognition of key data. The application scenarios of security chips include cash registers, identity recognition and identity authentication, etc. They are generally powered by batteries and are in sleep mode for a long time.

[0003] The working modes of security chips can generally be divided into normal mode and sleep mode. Sleep mode generally requires turning off digital logic such as MCU and storage units. Since the security chip is in sleep mode most of the time, reducing power consumption in sleep mode can extend battery life.

[0004] Existing technical solutions such as Figure 1 As shown, it includes a bandgap reference module, a low-power reference module and a regulator module. ENA and ENB are the enable signals of the bandgap reference module and the low-power reference module, respectively, which are enabled at a high level, and VDD is the output of the regulator module. In normal mode, the bandgap reference module is turned on, and the low-power reference module is turned off. The bandgap reference module provides a high-precision reference voltage Vref1 and a reference current Iref1 for the regulator module. In sleep mode, the bandgap reference module is turned off, and the low-power reference module is turned on. The low-power reference module provides a low-precision reference voltage Vref2 and a reference current Iref2 for the regulator module.

[0005] However, the above-mentioned traditional power supply system has the disadvantage of high power consumption; and the low-power reference module is generally composed entirely of MOS devices, and the output reference voltage and reference current have low accuracy; the zero-pole position of the regulator module will also change with the load, and the regulator compensation is relatively complicated. Summary of the invention

[0006] Based on this, the primary purpose of the present invention is to provide a power supply system for a security chip, which uses a configurable divider to adjust the proportion of the opening time of high-power modules such as a bandgap reference source to reduce the overall power consumption of the security chip.

[0007] Another object of the present invention is to provide a power supply system for a security chip, wherein the power supply system utilizes a capacitor to store a reference voltage when a bandgap reference source is turned on, thereby improving the output accuracy of a voltage regulator in a sleep mode.

[0008] To achieve the above object, the technical solution of the present invention is:

[0009] A power supply system for a security chip, comprising a configurable frequency divider module, a bandgap reference module, a low power reference module, a reference storage module, a low power regulator module and a high power regulator module;

[0010] The output of the configurable frequency divider module is connected to the bandgap reference module, the output of the bandgap reference module is connected to the reference storage module, and the output of the low-power reference module is also connected to the reference storage module, the output of the low-power reference module is also connected to the low-power regulator module and the high-power regulator module, and the output of the reference storage module is connected to the configurable frequency divider module, the low-power regulator module and the high-power regulator module;

[0011] CLK is the low-frequency clock input signal, EN_HP is the sleep mode enable input signal, CLK and EN_HP input signals to the configurable divider module, and EN_HP also inputs signals to the high-power regulator module; when EN_HP is high, it is in normal mode, and when EN_HP is low, it is in sleep mode; EN_LP is the low-power regulator module enable input signal, high level enables, and is always high; the outputs of the low-power regulator module and the high-power regulator module are short-circuited to provide the digital circuit power supply VDD.

[0012] The working modes of the power supply system of the present invention are divided into normal mode and sleep mode. In normal mode, all modules are turned on, and the outputs of the low-power regulator module and the high-power regulator module are short-circuited to provide the digital circuit power supply VDD. Since the normal output voltage of the low-power regulator module is 10% lower than the output voltage of the high-power regulator module, in normal mode, the low-power regulator module cannot work normally (i.e., the output power VDD cannot be stabilized), and the output power VDD is provided by the high-power regulator module in normal mode.

[0013] In sleep mode, the high-power regulator module is turned off, and the low-power regulator module provides 90% VDD of output power. By periodically turning on the bandgap reference module at fixed intervals, the storage capacitor in the reference storage module is replenished with charge regularly, and the reference storage module provides a high-precision reference source for the low-power regulator module, thereby solving the problem of high power consumption and low output power accuracy of the power system in the sleep mode of the security chip. The high-power regulator module only needs to consider the working conditions of higher load current in normal mode, and the low-power regulator module only needs to consider the working conditions of lower load current in sleep mode, so the regulator compensation is also relatively simple.

[0014] Therefore, the present invention can use a configurable frequency divider to adjust the proportion of the time when high-power consumption modules such as the bandgap reference source are turned on, thereby reducing the overall power consumption of the security chip; at the same time, it can use a capacitor to store the reference voltage when the bandgap reference source is turned on, thereby improving the output accuracy of the voltage regulator in the sleep mode.

[0015] Further, the configurable frequency divider module includes a configurable frequency divider circuit and a control circuit. The triggers DFF1~DFF5, inverters INV1~INV3, two-input NAND gates ND2_1~ND2_5 and four-input NAND gates ND4_1 constitute the configurable frequency divider circuit, wherein sp0, sp1, sp2, sp3 control the frequency division period. The trigger DFF6, inverters INV4~INV6, two-input NAND gates ND2_6 and two-input NOR gates NR2_1 constitute the control circuit. The triggers DFF1~DFF5 have a reset terminal RB. When RB is at a low level, the trigger output Q terminal is reset. When EN_HP is at a high level, the configurable frequency divider circuit is in a reset state. When the EN_HP signal jumps to a low level, the configurable frequency divider circuit starts to divide the CLK signal; when EN_DL flips to a high level, the trigger DFF6 is reset, BG_EN quickly flips to a low level, and EN_DL flips to a low level at the same time. The output of the configurable divider circuit (i.e., the output of INV3) is input to the CLK terminal of the trigger DFF6. After the frequency division cycle ends, BG_EN flips to a high level, and the cycle repeats.

[0016] Further, the configurable frequency divider circuit includes a trigger DFF, an inverter INV, a NAND gate ND, and a NOR gate NR, all of which have multiples; wherein the EN_HP signal and the CLK signal are input into DFF1, and DFF1 is connected to four triggers, namely DFF2, DFF3, DFF4, and DFF5, through ND2_1 and the inverter INV2, and these four triggers are connected to the control circuit DFF6, and DFF2, DFF3, DFF4, and DFF5 are respectively connected to ND2_2~ND2_5, and ND2_2~ND2_5 are connected to ND4_1, and are connected to DFF6 through INV3;

[0017] In the control circuit, INV4 is connected to ND2_6, ND2_6 is connected to INV5, INV5 is connected to DFF6, and at the same time, DFF6 is also connected to NR2_1, and NR2_1 is connected to INV6.

[0018] The EN_HP signal, CLK signal and feedback signal EN_DL are input to the configurable divider module, and the bandgap reference module enable signal BG_EN is output. When EN_HP is high, it is in normal mode, and BG_EN is always high; when EN_HP is low, it is in sleep mode, and when EN_DL flips to high, BG_EN quickly flips to low, and maintains low for several frequency division cycles, and then BG_EN flips to high, and repeats this cycle. Through sp0, sp1, sp2, and sp3, the frequency division period can be adjusted to 2, 4, 8, or 16 respectively. That is, when sp0 is high and sp1, sp2, and sp3 are low, the frequency division period is 2; when sp1 is high and sp0, sp2, and sp3 are low, the frequency division period is 4; when sp2 is high and sp0, sp1, and sp3 are low, the frequency division period is 8; when sp3 is high and sp0, sp1, and sp2 are low, the frequency division period is 16.

[0019] Furthermore, the high power consumption regulator module is a regulator without external capacitors, and the output of the high power consumption regulator module provides the digital circuit power supply VDD; in the high power consumption regulator module, VREF2 is a 1.0V reference voltage input, R2 / R1 is 1.1, so the high power consumption regulator module outputs a 1.1V voltage.

[0020] Furthermore, the low-power voltage regulator module is a voltage regulator without an external capacitor. The output of the low-power voltage regulator module provides the digital circuit power supply VDD. The low-power voltage regulator is connected in the form of a voltage follower. Vref_stored is a 1.0V storage reference voltage input. The output VDD follows the input voltage Vref_stored. The low-power voltage regulator module outputs a 1.0V voltage. The low-power voltage regulator module is always turned on, and the storage reference voltage Vref_stored is periodically replenished with charge in sleep mode without powering off.

[0021] When EN_HP is high, the high power regulator module is turned on. Since the output voltage of the high power regulator module is higher, the low power regulator module cannot work normally at this time, and the regulator output voltage is 1.1V; when EN_HP is low, the high power regulator module is turned off, and the regulator output voltage is 1.0V. A lower supply voltage in sleep mode is beneficial to reducing the overall power consumption of the chip.

[0022] Further, in the reference storage module circuit, NMOS transistors N1, N2, N3, N4, N5, PMOS transistors P1, P2, P3, P4, P5, resistors R1, R2, R3, and capacitor C1 constitute a unit gain analog buffer, capacitor C4 is a storage capacitor, and TG1 is a voltage transmission gate; VS_EN is an enable control signal, when VS_EN is at a high level, the reference storage module is turned on, and when VS_EN is at a low level, the reference storage module is turned off; Vref_stored is the output of the bandgap reference voltage VREF1 through the analog buffer; when ena_dl2 is at a high level, the voltage transmission gate TG1 is turned on to supplement the storage capacitor C4 with charge, and when ena_dl2 is at a low level, the voltage transmission gate TG1 is turned off, and the storage capacitor C4 maintains the storage reference voltage Vref_stored;

[0023] PMOS transistors P6, P7, P8, NMOS transistors N6, N7, N8, N9, Schmitt trigger SMIT1, inverters INV3 and INV4 form a delay circuit. After a unilateral delay of 2us, ena_dl1 signal is generated, indicating that the analog buffer is established. After a unilateral delay of 0.3us by DELAY1, ena_dl1 generates an ena_dl2 signal. After a unilateral delay of 1.8us by DELAY2, ena_dl2 generates an EN_DL signal to control the configurable divider module.

[0024] Compared with the prior art, the technical effects of the present invention are as follows:

[0025] In the sleep mode of the present invention, a configurable frequency divider is used to adjust the proportion of the opening time of high-power consumption modules such as a bandgap reference source, thereby reducing the overall power consumption of the security chip.

[0026] The present invention utilizes a capacitor to store a reference voltage when a bandgap reference source is turned on, thereby improving the output accuracy of a voltage regulator in a sleep mode.

[0027] A low-power reference module can also be used to generate a reference current to further reduce the overall power consumption of the security chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 The invention is a circuit diagram of a safety chip power supply system in the prior art.

[0029] Figure 2 It is a circuit diagram of a power supply system implemented by the present invention.

[0030] Figure 3 is a circuit diagram of a configurable frequency divider module implemented in the present invention.

[0031] Figure 4 It is a circuit diagram of the low power consumption voltage regulator module implemented by the present invention.

[0032] Figure 5 It is a circuit diagram of the high power consumption voltage regulator module implemented by the present invention.

[0033] Figure 6 is a circuit diagram of a reference storage module implemented in the present invention.

[0034] Figure 7 It is a timing diagram of various enable signals implemented in the present invention. DETAILED DESCRIPTION

[0035] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0036] Figure 2 The power system implementation scheme of the present invention includes a configurable divider module, a bandgap reference module, a low-power reference module, a reference storage module, a low-power regulator module and a high-power regulator module. CLK is a low-frequency clock input signal, and the clock frequency is 2KHz (an embodiment); EN_HP is a sleep mode enable input signal, when EN_HP is high level, it is a normal mode, when EN_HP is low level, it is a sleep mode. EN_LP is the low-power regulator module enable input signal, EN_HP also inputs a signal to the high-power regulator module, high level enable, and always high level. The outputs of the low-power regulator module and the high-power regulator module are short-circuited to provide the digital circuit power supply VDD.

[0037] Among them, the configurable divider module circuit diagram is as follows Figure 3 As shown. The configurable frequency divider module includes a configurable frequency divider circuit and a control circuit. The trigger DFF1~DFF5, the inverter INV1~INV3, the two-input NAND gate ND2_1~ND2_5 and the four-input NAND gate ND4_1 constitute the configurable frequency divider circuit, wherein sp0, sp1, sp2, sp3 control the frequency division cycle. The trigger DFF6, the inverter INV4~INV6, the two-input NAND gate ND2_6 and the two-input NOR gate NR2_1 constitute the control circuit. The trigger DFF1~DFF5 has a reset terminal RB. When RB is low, the trigger output Q terminal is reset. When EN_HP is high, the configurable frequency divider circuit is in a reset state. When the EN_HP signal jumps to a low level, the configurable frequency divider circuit starts to divide the CLK signal; when EN_DL flips to a high level, the trigger DFF6 is reset, BG_EN quickly flips to a low level, and EN_DL flips to a low level at the same time. The output of the configurable divider circuit (i.e., the output of INV3) is input to the CLK terminal of the trigger DFF6. After the frequency division cycle ends, BG_EN flips to a high level, and the cycle repeats.

[0038] The configurable frequency divider circuit includes a trigger DFF, an inverter INV, a NAND gate ND, and a NOR gate NR, all of which have multiples; wherein, the EN_HP signal and the CLK signal are input into DFF1, and DFF1 is connected to four triggers, namely DFF2, DFF3, DFF4, and DFF5, through ND2_1 and the inverter INV2, and these four triggers are connected to the control circuit DFF6, and DFF2, DFF3, DFF4, and DFF5 are respectively connected to ND2_2~ND2_5, and ND2_2~ND2_5 are connected to ND4_1, and are connected to DFF6 through INV3;

[0039] In the control circuit, INV4 is connected to ND2_6, ND2_6 is connected to INV5, INV5 is connected to DFF6, and at the same time, DFF6 is also connected to NR2_1, and NR2_1 is connected to INV6.

[0040] The EN_HP signal, CLK signal and feedback signal EN_DL are input to the configurable divider module, and the bandgap reference module enable signal BG_EN is output. When EN_HP is high, it is in normal mode, and BG_EN is always high; when EN_HP is low, it is in sleep mode, and when EN_DL flips to high, BG_EN quickly flips to low, and maintains low for several frequency division cycles, and then BG_EN flips to high, and repeats this cycle. Through sp0, sp1, sp2, and sp3, the frequency division period can be adjusted to 2, 4, 8, or 16 respectively. That is, when sp0 is high and sp1, sp2, and sp3 are low, the frequency division period is 2; when sp1 is high and sp0, sp2, and sp3 are low, the frequency division period is 4; when sp2 is high and sp0, sp1, and sp3 are low, the frequency division period is 8; when sp3 is high and sp0, sp1, and sp2 are low, the frequency division period is 16.

[0041] When BG_EN is high, the bandgap reference module is turned on to provide a high-precision reference voltage VREF1 for the reference storage module. When BG_EN is low, the bandgap reference module is turned off, and a bandgap reference voltage establishment completion signal VS_EN is generated after a 1.1us unilateral delay on the rising edge of BG_EN.

[0042] The low power reference module is used to generate a low power reference current, and provides relatively low precision reference currents IBIAS1, IBIAS2 and IBIAS3 for the reference storage module, the high power regulator module and the low power regulator module respectively.

[0043] The bandgap reference module and the low power consumption reference module are both existing technologies and will not be described in detail here.

[0044] The low power regulator module and the high power regulator module are respectively as follows Figure 4 and Figure 5 As shown, both are voltage regulators without external capacitors. The outputs of the high-power voltage regulator module and the low-power voltage regulator module provide the digital circuit power supply VDD. The low-power voltage regulator is connected in the form of a voltage follower. Vref_stored is a 1.0V storage reference voltage input. The output VDD follows the input voltage Vref_stored. The low-power voltage regulator module outputs a 1.0V voltage. In the high-power voltage regulator module, VREF2 is a 1.0V reference voltage input, and R2 / R1 is 1.1, so the high-power voltage regulator module outputs a 1.1V voltage. The low-power voltage regulator module is always turned on, and the storage reference voltage Vref_stored is regularly replenished in sleep mode without powering off. When EN_HP is high, the high-power voltage regulator module is turned on. Because the output voltage of the high-power voltage regulator module is higher, the low-power voltage regulator module cannot work normally at this time, and the output voltage of the voltage regulator is 1.1V; when EN_HP is low, the high-power voltage regulator module is turned off, and the output voltage of the voltage regulator is 1.0V. A lower supply voltage in sleep mode helps reduce the overall power consumption of the chip.

[0045] The circuit diagram of the reference storage module is as follows: Figure 6 As shown, VS_EN is an enable control signal. When VS_EN is at a high level, the reference storage module is turned on, and when VS_EN is at a low level, the reference storage module is turned off. NMOS transistors N1, N2, N3, N4, N5, PMOS transistors P1, P2, P3, P4, P5, resistors R1, R2, R3, and capacitor C1 form a unit gain analog buffer. Vref_stored is the output of the bandgap reference voltage VREF1 through the analog buffer. Capacitor C4 is a storage capacitor, and TG1 is a voltage transmission gate. When ena_dl2 is at a high level, the voltage transmission gate TG1 is turned on to supplement the charge for the storage capacitor C4. When ena_dl2 is at a low level, the voltage transmission gate TG1 is turned off, and the storage capacitor C4 maintains the storage reference voltage Vref_stored.

[0046] PMOS transistors P6, P7, P8, NMOS transistors N6, N7, N8, N9, Schmitt trigger SMIT1, inverters INV3 and INV4 form a delay circuit. After a single-side delay (rising edge) of about 2us, the ena_dl1 signal is generated, marking the completion of the analog buffer establishment. After a single-side delay (rising edge) of 0.3us by DELAY1, ena_dl1 generates an ena_dl2 signal. After a single-side delay (rising edge) of 1.8us by DELAY2, ena_dl2 generates an EN_DL signal to control the configurable divider module.

[0047] The timing diagram of each enable signal is as follows Figure 7As shown, CLK is the clock input signal, EN_HP is the mode switching signal, BG_EN is the bandgap reference module enable signal, and VS_EN is the bandgap reference module establishment completion signal. In normal mode, all of the above enable signals are high level. ena_dl1 is the reference storage module enable signal VS_EN, which has a 2us unilateral delay (rising edge), marking the completion of the analog buffer establishment in the reference storage module; ena_dl2 is the 0.3us unilateral delay (rising edge) signal of ena_dl1, which stores the reference voltage when it is high level; EN_DL is the 1.8us unilateral delay (rising edge) signal of ena_dl2. After EN_DL flips to a high level for 4ns, all enable signals quickly flip to a low level.

[0048] In normal mode, all modules are turned on, the low-power regulator module cannot work normally, and the parallel output voltage of the regulator is determined by the output of the high-power regulator module, which is a 1.1V power supply voltage. In sleep mode, EN_HP is low and the high-power regulator module is turned off. BG_EN flips once every N clock cycles (N=2 / 4 / 8 / 16). When BG_EN flips to a high level, the bandgap reference module is turned on; after a 1.1us delay, VS_EN flips to a high level to enable the reference storage module; after a 2us delay, the analog buffer is established, and after a 0.3us delay, the transmission gate is enabled to charge the reference storage capacitor C4. After a 1.8us delay, EN_DL is generated and fed back to the configurable divider module, and all enable signals quickly flip to a low level, turning off the bandgap reference module, the reference storage module and the high-power regulator module. The low-power regulator relies on the stored voltage reference to work and output a 1.0V power supply voltage.

[0049] In summary, the present invention sets a configurable divider module so that BG_EN flips once every N clock cycles. When BG_EN flips to a high level, the bandgap reference module is turned on; after a delay, VS_EN flips to a high level to enable the reference storage module; when EN_HP is a high level, the high-power regulator module is turned on and the low-power regulator module is turned off; when EN_HP is a low level, the high-power regulator module is turned off, and the regulator output voltage is 1.0V. Therefore, a lower supply voltage in sleep mode is beneficial to reducing the overall power consumption of the chip.

[0050] The present invention utilizes a configurable frequency divider to adjust the proportion of the time when high-power consumption modules such as a bandgap reference source are turned on, thereby reducing the overall power consumption of a security chip. At the same time, a capacitor is used to store a reference voltage when the bandgap reference source is turned on, thereby improving the output accuracy of a voltage regulator in a sleep mode.

[0051] A low-power reference module can also be used to generate a reference current to reduce the overall power consumption of the security chip.

[0052] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A power supply system for a security chip, characterized in that It includes a configurable frequency divider module, a bandgap reference module, a low power reference module, a reference storage module, a low power regulator module and a high power regulator module; The output of the configurable frequency divider module is connected to the bandgap reference module, the output of the bandgap reference module is connected to the reference storage module, and the output of the low-power reference module is also connected to the reference storage module, the output of the low-power reference module is also connected to the low-power regulator module and the high-power regulator module, and the output of the reference storage module is connected to the configurable frequency divider module, the low-power regulator module and the high-power regulator module; CLK is the low-frequency clock input signal, EN_HP is the sleep mode enable input signal, CLK and EN_HP input signals to the configurable divider module, and EN_HP simultaneously inputs signals to the high-power regulator module; when EN_HP is high, it is in normal mode, and when EN_HP is low, it is in sleep mode; EN_LP is the low-power regulator module enable input signal, high level enables, and is always high level; the outputs of the low-power regulator module and the high-power regulator module are short-circuited to provide the digital circuit power supply VDD; The configurable frequency divider module includes a configurable frequency divider circuit and a control circuit, wherein the triggers DFF1 to DFF5, the inverters INV1 to INV3, the two-input NAND gates ND2_1 to ND2_5 and the four-input NAND gate ND4_1 constitute the configurable frequency divider circuit, and sp0, sp1, sp2 and sp3 control the frequency division cycle; the trigger DFF6, the inverters INV4 to INV6, the two-input NAND gate ND2_6 and the two-input NOR gate NR2_1 constitute the control circuit; the triggers DFF1 to DFF5 have reset terminals RB , when RB is low, the trigger output Q terminal is reset. When EN_HP is high, the configurable divider circuit is in reset state. When the EN_HP signal jumps to low, the configurable divider circuit starts dividing the CLK signal. When EN_DL flips to high, the trigger DFF6 is reset, BG_EN flips to low, and EN_DL flips to low. The output of the configurable divider circuit is input to the CLK terminal of the trigger DFF6. After the division cycle ends, BG_EN flips to high, and this cycle repeats. When sp0 is high and sp1, sp2 and sp3 are low, the frequency division period is 2; when sp1 is high and sp0, sp2 and sp3 are low, the frequency division period is 4; when sp2 is high and sp0, sp1 and sp3 are low, the frequency division period is 8; when sp3 is high and sp0, sp1 and sp2 are low, the frequency division period is 16; In the reference storage module circuit, NMOS transistors N1, N2, N3, N4, N5, PMOS transistors P1, P2, P3, P4, P5, resistors R1, R2, R3, and capacitor C1 form a unit gain analog buffer, capacitor C4 is a storage capacitor, and TG1 is a voltage transmission gate; VS_EN is an enable control signal, when VS_EN is at a high level, the reference storage module is turned on, and when VS_EN is at a low level, the reference storage module is turned off; Vref_stored is the output of the bandgap reference voltage VREF1 through the analog buffer; when ena_dl2 is at a high level, the voltage transmission gate TG1 is turned on to supplement the charge for the storage capacitor C4, and when ena_dl2 is at a low level, the voltage transmission gate TG1 is turned off, and the storage capacitor C4 maintains the storage reference voltage Vref_stored; PMOS transistors P6, P7, P8, NMOS transistors N6, N7, N8, N9, Schmitt trigger SMIT1, inverters INV3 and INV4 form a delay circuit. After a unilateral delay of 2us, ena_dl1 signal is generated, indicating that the analog buffer is established. After a unilateral delay of 0.3us by DELAY1, ena_dl1 generates an ena_dl2 signal. After a unilateral delay of 1.8us by DELAY2, ena_dl2 generates an EN_DL signal to control the configurable divider module.

2. The power supply system for a security chip as claimed in claim 1, characterized in that The configurable frequency divider circuit includes a trigger DFF, an inverter INV, a NAND gate ND, and a NOR gate NR, all of which have multiples; wherein the EN_HP signal and the CLK signal are input into DFF1, and DFF1 is connected to four triggers, namely DFF2, DFF3, DFF4, and DFF5, through ND2_1 and the inverter INV2, and these four triggers are connected to the control circuit DFF6, and DFF2, DFF3, DFF4, and DFF5 are respectively connected to ND2_2 to ND2_5, and ND2_2 to ND2_5 are connected to ND4_1, and are connected to DFF6 through INV3; In the control circuit, INV4 is connected to ND2_6, ND2_6 is connected to INV5, INV5 is connected to DFF6, and at the same time, DFF6 is also connected to NR2_1, and NR2_1 is connected to INV6.

3. The power supply system for a security chip as claimed in claim 1, characterized in that The high power consumption voltage regulator module is a voltage regulator without external capacitors, and the output of the high power consumption voltage regulator module provides power supply VDD; in the high power consumption voltage regulator module, VREF2 is a 1.0V reference voltage input, the ratio of resistors R1 and R2 is 1.1, and the high power consumption voltage regulator module outputs a 1.1V voltage.

4. The power supply system for a security chip as claimed in claim 1, characterized in that The low-power voltage regulator module is a voltage regulator without external capacitors. The output of the low-power voltage regulator module provides power supply VDD. The low-power voltage regulator is connected in the form of a voltage follower. Vref_stored is a 1.0V storage reference voltage input. The output VDD follows the input voltage Vref_stored. The low-power voltage regulator module outputs a 1.0V voltage. The low-power voltage regulator module is always turned on, and the storage reference voltage Vref_stored is periodically replenished with charge in sleep mode without powering off.

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