Synchronous communication interface based on FPGA, synchronous communication method and electronic equipment

Abstract

The invention provides a synchronous communication interface based on an FPGA, a synchronous communication method and electronic equipment, and relates to the technical field of communication. The synchronous communication interface based on the FPGA comprises a first asynchronous serial port used for transmitting a data signal; the second asynchronous serial port is used for transmitting a clock signal; the FPGA circuit is used for combining the data packets and sending the data packets to the first asynchronous serial port through a synchronous communication protocol, so that the first asynchronous serial port converts the data packets into differential data signals and sends the differential data signals to the outside; and synchronously sending the clock signal to the second asynchronous serial port, so that the second asynchronous serial port converts the clock signal into a differential clock signal and sends the differential clock signal to the outside. Two paths of asynchronous serial ports are changed into one path of synchronous serial communication interface through FPGA circuit design, the existing URAT can be replaced, and the transmission efficiency and the transmission reliability are improved.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to a synchronous communication interface, a synchronous communication method and electronic equipment based on FPGA. Background Art

[0002] In serial communication, data is sent or received bit by bit, and there are two modes: synchronous and asynchronous. Synchronous serial port introduces an external clock during transmission. The sender and receiver synchronize through this clock signal to ensure that data can be accurately transmitted and received. The data transmission speed is relatively fast. Asynchronous serial port does not require clock synchronization, and synchronization is performed through the start and stop bits at the beginning and end of the data. However, when sending data, the Universal Asynchronous Receiver / Transmitter (URAT) needs to add a start bit, a check bit, and a stop bit to each byte of data. The transmission speed is relatively slow, which reduces the data transmission efficiency. In addition, the data verification during transmission generally uses a single byte for parity check. The data reliability is not high, and it is not suitable for large data transmission or certain scenarios with high requirements for data transmission efficiency and data reliability. Summary of the invention

[0003] The present invention provides a synchronous communication interface, a synchronous communication method and an electronic device based on FPGA to replace the traditional asynchronous transceiver and solve the problem of reduced asynchronous transmission efficiency in a scenario with a large amount of data transmission.

[0004] The present invention is achieved through the following technical solutions:

[0005] In a first aspect, the present invention provides a synchronous communication interface based on FPGA, comprising:

[0006] A first asynchronous serial port, used for transmitting data signals;

[0007] The second asynchronous serial port is used to transmit a clock signal;

[0008] an FPGA circuit, configured to combine data packets, and send the data packets to the first asynchronous serial port through a synchronous communication protocol, so that the first asynchronous serial port converts the data packets into differential data signals for external transmission; and

[0009] The clock signal is synchronously sent to the second asynchronous serial port, so that the second asynchronous serial port converts the clock signal into a differential clock signal and sends it externally.

[0010] The present invention realizes two asynchronous serial ports as one synchronous serial communication interface through FPGA circuit design, which can replace the existing URAT, realizes packet assembly, analysis and data transmission and reception through FPGA, and sends data through synchronous communication protocol, with fast transmission speed. In large data volume transmission scenarios, the amount of data transmitted in the data packet is less and the transmission efficiency is high. Finally, the first asynchronous serial port and the second asynchronous serial port are used to transmit the sent data to other asynchronous communication interfaces in a single-ended to differential manner to realize serial output.

[0011] Furthermore, the FPGA circuit is also used to receive data packets from the first asynchronous serial port and the second asynchronous serial port, and parse the received data packets.

[0012] Furthermore, the first asynchronous serial port and the second asynchronous serial port are RS422 interfaces or RS485 interfaces.

[0013] Further, the FPGA circuit includes a data processing module, a sending buffer module, a sending module, a receiving buffer module, a receiving module and a clock module;

[0014] The data processing module is used to combine data packets or parse data packets;

[0015] The clock module is used to provide a clock signal for each module in the FPGA circuit;

[0016] The sending buffer module is connected between the data processing module and the sending module, and is used for buffering the sending data packets;

[0017] The receiving buffer module is connected between the data processing module and the receiving module, and is used for buffering received data packets;

[0018] The sending module is used to sequentially obtain the sending data packets from the data buffer module, send the sending data packets to the first asynchronous serial port, and obtain the sending clock signal from the clock module, and synchronously send the sending clock signal to the second asynchronous serial port;

[0019] The receiving module is used to obtain a received data packet and a received clock signal from the first asynchronous serial port and the second asynchronous serial port, sample the received data at each rising edge of the received clock signal, and send the sampled signal to the receiving buffer module.

[0020] Furthermore, the sending buffer module and the receiving buffer module are first-in-first-out FIFO buffers.

[0021] Furthermore, the data packet includes a data packet header, a source device ID, a destination device ID, data content, a CRC check bit, and a data packet trailer.

[0022] Furthermore, when sending data, the sending module is further used to detect the data content in the sending data packet, and insert a binary 0 after five consecutive binary 1s in the data content;

[0023] When receiving data, the receiving module is further used to detect the data content in the received data packet and delete the binary 0 after five consecutive binary 1s in the data content.

[0024] Furthermore, the synchronous communication interface is a bus type interface.

[0025] In a second aspect, the present invention provides a synchronous communication method, which is applied to the FPGA-based synchronous communication interface described in any one of the first aspects of the present invention, and the method comprises:

[0026] The data to be sent are formed into a sending data packet by the FPGA circuit;

[0027] Sending the transmitted data packet to the first asynchronous serial port through a synchronous communication protocol;

[0028] Synchronously sending a sending clock signal to the second asynchronous serial port;

[0029] Converting the transmitted data packet into a differential data signal through the first asynchronous serial port, and converting the transmitted clock signal into a differential clock signal through the second asynchronous serial port;

[0030] The differential data signal and the differential clock signal are synchronously sent through the first asynchronous serial port and the second asynchronous serial port.

[0031] In a third aspect, the present invention provides an electronic device, comprising an FPGA-based synchronous communication interface as described in any one of the first aspects of the present invention, and communicating with other electronic devices via the synchronous communication interface.

[0032] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0033] 1. The two asynchronous serial ports are realized as one synchronous serial communication interface, which can replace the existing URAT and improve the transmission speed and efficiency.

[0034] 2. Through fixed-format data packets, only the CRC field needs to be calculated when receiving data for verification. Compared with the single-byte parity check used by traditional UART, it has higher reliability and improves data transmission reliability.

[0035] 3. Implementing the synchronous communication interface as a bus interface enables multiple devices connected to the same bus to communicate with each other, thus improving the utilization rate of the communication link.

[0036] 4. Use field-editable logic gate array FPGA for synchronous communication design, which is simple and universal, with low power consumption and good scalability. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions of the exemplary embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present invention and should not be regarded as limiting the scope. For those of ordinary skill in the art, other relevant drawings can be obtained based on these drawings without creative work. In the drawings:

[0038] Figure 1 It is a schematic diagram of the hardware structure of a synchronous communication interface based on FPGA according to an embodiment of the present invention;

[0039] Figure 2 is a schematic structural diagram of a clock module according to an embodiment of the present invention;

[0040] Figure 3 is a schematic diagram of a data processing flow in an embodiment of the present invention;

[0041] Figure 4 is a schematic diagram of a multi-device bus connection according to an embodiment of the present invention;

[0042] Figure 5 This is a schematic diagram of a multi-device communication process according to an embodiment of the present invention;

[0043] Figure 6 The figure is a schematic diagram of the structure of an electronic device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0044] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with embodiments and drawings. The exemplary embodiments of the present invention and their description are only used to explain the present invention and are not intended to limit the present invention.

[0045] It should be noted that the terms "including" and "having" and any variations thereof in the specification and claims of the present invention and the above-mentioned drawings are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to or inherent to other steps or units of the device.

[0046] The terms used in the various embodiments of the application are only used to describe the purpose of specific embodiments and are not intended to limit the various embodiments of the application. As used herein, the singular form is intended to also include the plural form, unless the context clearly indicates otherwise. Unless otherwise limited, all terms used here (including technical terms and scientific terms) have the same meaning as the meanings commonly understood by ordinary technicians in the field of the various embodiments of the application. The terms (such as the terms defined in the dictionary generally used) will be interpreted as having the same meaning as the contextual meaning in the relevant technical field and will not be interpreted as having an idealized meaning or an overly formal meaning, unless clearly defined in the various embodiments of the application.

[0047] The embodiments of the present invention provide a synchronous communication interface, a synchronous communication method and an electronic device based on FPGA, which are used for communication between electronic devices, are conducive to improving transmission efficiency and transmission reliability, and are particularly suitable for scenarios with large data transmission volume and high requirements for data transmission efficiency and data reliability.

[0048] The relevant terms involved in the present invention are explained as follows:

[0049] Serial port: Serial interface (Serial Interface), also called cluster communication port (cluster communication port), any device that performs serial communication is a serial port.

[0050] Serial communication: A communication method that sends and receives bytes bit by bit.

[0051] Synchronous communication: The sender provides a clock signal while sending serial data, and sends data according to the agreement (for example, sending data at the rising edge / falling edge of the clock signal). The receiving end receives data according to the same agreement based on the clock signal provided by the sender.

[0052] Asynchronous communication: The sender only sends data frames and does not transmit the clock. The sender and receiver must agree on the same transmission rate. The receiver achieves information synchronization with the help of the start bit and stop bit of the data.

[0053] UART: Universal Asynchronous Receiver / Transmitter, a serial, asynchronous, full-duplex communication protocol widely used in the embedded field.

[0054] Example 1

[0055] This embodiment provides a synchronous communication interface based on FPGA. The synchronous communication interface is constructed based on two asynchronous serial ports in combination with FPGA, includes hardware design and software design parts, and realizes the two asynchronous serial port communications as one synchronous serial port communication.

[0056] Hardware design see Figure 1 As shown, Figure 1 : is a hardware structure diagram of the synchronous communication interface based on FPGA in this embodiment, including a first asynchronous serial port, a second asynchronous serial port and an FPGA circuit. The first asynchronous serial port and the second asynchronous serial port are used to convert the single-ended signal of FPGA data into a differential signal with the electrical characteristics of the asynchronous serial port, and to convert the differential signal from other asynchronous serial ports into a single-ended signal for reception.

[0057] A differential signal refers to two voltage signals with equal amplitudes and opposite phases. The conversion between single-ended signals and differential signals is the process of converting one signal into two opposite signals. For example, a 1V peak-to-peak sine wave is converted into two differential sine waves, which are a 0.5V peak-to-peak sine wave and a 0.5V peak-to-peak sine wave with a phase difference of 180°. Conversely, the two differential signals are combined into a single-ended signal.

[0058] The first asynchronous serial port and the second asynchronous serial port each include a data conversion module and an interface module, the data conversion module is used to convert single-ended signals and differential signals, and the data interface module is used to transmit the converted single-ended signals or differential signals. The data conversion module is a hardware chip that can realize the above-mentioned mutual conversion process. The present invention does not specify a specific chip model, and preferably uses a chip with a high communication rate.

[0059] In asynchronous serial communication, the clock signal is divided into two differential clock signals CLK_P (positive phase) and CLK_N (negative phase), and the data signal is divided into two differential data signals DATA_P (positive phase) and DATA_N (negative phase). The data signal and the clock signal are synchronously transmitted through two data lines. The first asynchronous serial port is used to transmit the data signal, and the second asynchronous serial port is used to transmit the clock signal, or the first asynchronous serial port is used to transmit the clock signal, and the second asynchronous serial port is used to transmit the data signal.

[0060] The data conversion module in the first asynchronous serial port and the data conversion module in the second asynchronous serial port are respectively used to convert the clock signal and the data signal, such as the first asynchronous serial port converts the data signal (DATA) and the second asynchronous serial port converts the clock signal (CLK), or the first asynchronous serial port converts the clock signal (CLK) and the second asynchronous serial port converts the data signal (DATA).

[0061] The field-editable logic gate array FPGA is used as the peripheral circuit of the two asynchronous serial ports. The asynchronous serial port communication is converted into the synchronous serial port communication through the FPGA software design. It is used to combine data packets, parse data packets, and send the data packets to be sent to the first asynchronous serial port through the synchronous communication protocol. After being converted into differential data signals by the first asynchronous serial port, they are sent to the data receiving end of the other asynchronous serial ports. When sending data, the clock signal is obtained and sent synchronously to the second asynchronous serial port. After being converted into a differential clock signal by the second asynchronous serial port, it is sent to the clock receiving end of the other asynchronous serial port.

[0062] Through the above settings, the two asynchronous serial ports can be combined into a group of synchronous communication interfaces. By connecting the synchronous communication interfaces to electronic equipment, synchronous communication of the asynchronous serial ports can be achieved.

[0063] Furthermore, the synchronous communication interface is implemented as a bidirectional communication interface. When receiving data, data and a synchronous clock signal are received through the first asynchronous serial port and the second asynchronous serial port, and the received data is sampled according to the received synchronous clock signal to complete the reception. The FPGA parses the received data packet and extracts valid data.

[0064] Furthermore, the first asynchronous serial port and the second asynchronous serial port are in half-duplex communication mode.

[0065] Furthermore, the first asynchronous serial port and the second asynchronous serial port are in full-duplex communication mode.

[0066] If the half-duplex communication mode is adopted, the asynchronous serial port can use RS485, and if the full-duplex communication mode is adopted, the asynchronous serial port can use RS422. The corresponding communication mode can be selected according to the application scenario.

[0067] Furthermore, the FPGA circuit includes a data processing module, a sending buffer module, a sending module, a receiving buffer module, a receiving module and a clock module, wherein the clock module provides a clock reference for the data processing module, the sending buffer module, the sending module, the receiving buffer module and the receiving module.

[0068] The data processing module is used for packet assembly and data analysis. The sending end of the data processing module is connected to the sending buffer module and the sending module in sequence, and the receiving end of the data processing module is connected to the receiving buffer module and the receiving module in sequence. After the data processing module assembles the packet, it caches the data packet in the sending buffer module. The sending module takes the data out of the sending buffer and sends the data according to the communication sequence. The receiving module samples the data at each rising edge of the receiving clock signal according to the communication sequence, and caches the sampled data in the receiving buffer module. The data processing module obtains the received data packet from the receiving buffer and analyzes it.

[0069] like Figure 2The figure shows the structure diagram of the clock module. The clock module includes a crystal oscillator and a phase-locked loop (PLL). The crystal oscillator is connected to the outside of the FPGA. The crystal oscillator provides the basic clock for the FPGA. The FPGA calls the IP core of the phase-locked loop to divide and multiply the basic clock to obtain the data processing module, the sending buffer module, the sending module, the receiving buffer module, the receiving module, and the required frequency and clock.

[0070] The data packet format is a synchronous communication protocol data packet format, including a data packet header, a source device ID, a destination device ID, data content, a CRC check bit, and a data packet trailer.

[0071] The header of the data packet is fixed to four hexadecimal 0x7E (corresponding to binary 01111110), occupying a total of 4 bytes, and is used to mark the start of sending a packet of data.

[0072] The source device ID is one of the hexadecimal values ​​0x00 to 0xFF, occupying 1 byte. At the beginning, a unique ID is assigned to all devices connected to the same synchronous communication bus. When sending data, this byte is the device ID of the device itself. When receiving data, this byte is the sender device ID of the current data packet.

[0073] The destination device ID is one of the hexadecimal values ​​0x00 to 0xFF. When data is sent, this byte is the destination device ID of the current data packet.

[0074] The data content is the binary data actually sent. The theoretical data length is any byte length. The actual setting is generally any length within 1012 bytes.

[0075] The CRC check bit adopts the universal CRC16 cyclic redundancy check algorithm. The present invention does not specify the specific polynomial of the CRC algorithm. It only requires that all devices connected to the same bus maintain a consistent CRC16 algorithm. It occupies a total of 2 bytes and is calculated by the data packet header field, source device ID field, destination device ID field and data field through the CRC16 check algorithm.

[0076] The tail of a data packet is fixed to four hexadecimal 0x7E (corresponding to binary 01111110), which occupies a total of 4 bytes and is used to mark the end of sending a data packet.

[0077] Furthermore, the receiving buffer module and the sending buffer module are first-in-first-out FIFO buffers.

[0078] like Figure 3The figure shows a schematic diagram of the data processing flow. When sending data, the data processing module combines the data to be sent into a fixed-format data packet, and then stores the prepared data packet in the send FIFO. The sending module then takes out the data in the send FIFO in sequence. When receiving data, the receiving module stores the received fixed-format data packet in the receive FIFO, and the data processing module takes out the data in the receive buffer. After taking out, the data packet is CRC-checked. If the check is wrong, the packet is discarded. If the check is correct, the data packet is parsed, the data content is extracted, and the data reception is completed.

[0079] Furthermore, when sending data, the sending module detects the data taken out from the sending FIFO, and when five consecutive binary 1s are detected in the data content, a binary 0 is inserted after the five consecutive binary 1s; when receiving data, the receiving module detects the received data packet, and when five consecutive binary 1s are detected in the data content, the binary 0 after the five consecutive binary 1s is removed.

[0080] Since the header and the tail include the hexadecimal 0x7E, which is 01111110 in binary, to ensure that the data string is not mistaken for the header and tail flag fields, when sending data, the sending module detects the continuous "1" in the data other than the header and the tail. When there are 5 consecutive binary 1 bits, a "0" operation is inserted after the 5 consecutive "1". For example, when the sending data is binary "111110", the actual data sent is binary "1111100", and when the sending data is binary "111111", the actual data sent is binary "1111101". The receiving module samples the data at each rising edge of the clock line according to the communication timing. When receiving data, when 4 consecutive hexadecimal 0x7E are detected, it indicates the start of a data transmission. When 4 hexadecimal 0x7E are detected again, it indicates the end of data packet transmission. During the data receiving process, since the data at the sending end has a 0 insertion operation, it is necessary to perform a 0 deletion operation to restore the data during the data receiving process. That is, when 5 binary 1s are received continuously during data receiving, the 0s following these 5 binary 1s need to be deleted. For example: when the actual received data is binary "1111100", the actual data should be binary "111110"; when the actual received data is binary "1111101", the actual received data should be "111111".

[0081] Traditional UART verification uses parity check for a single byte, that is, using 1 bit width to indicate whether the number of binary 1s in a single byte is odd or even. Half of the 256 data from 0 to 255 have the same parity check, so this verification method has a high error rate. Performing CRC16 check calculation on each packet of data improves the reliability of data transmission.

[0082] In addition, each byte transmitted by traditional UART has a start bit, a stop bit and a check bit. To transmit 8 bits of data, 11 bits are actually required, and the transmission efficiency is 8 / 11≈73%. The synchronous communication protocol data packet format is used. There is no start bit and stop bit in the single byte transmission. The header, tail and CRC16 check bytes of the data packet are added. When the size of the transmitted data packet reaches a certain byte, the transmission efficiency is improved. The comparison results of the transmission efficiency of the two are shown in Table 1.

[0083] Table 1 Data transmission efficiency comparison table

[0084]

[0085] Furthermore, the synchronous communication interface is a bus type interface.

[0086] Multiple electronic devices can be connected to each other through a bus, and the devices connected to the bus can communicate with each other. In bus communication, a unique ID must be assigned to each electronic device connected to the bus in advance, and one of them is designated as the master device, and the rest are slave devices.

[0087] like Figure 4 The figure shows a multi-device bus connection diagram. Figure 5 This is a schematic diagram of the multi-device communication process. At the beginning of the communication establishment, all devices on the bus are in the data receiving state. The master device switches from the data receiving state to the data sending state, and sends a packet of data to the slave device. The source device ID in the data packet is the master device ID, and the destination device ID is the ID of the device that needs to receive the data. After the data is sent, the master device state switches from the sending state to the data receiving state, waiting to receive data. Other devices on the bus are in the data receiving state, and all devices can receive the data sent by the master device. The slave device determines whether the currently received data packet is the data sent to this device based on the destination device ID field in the data packet. If the destination ID field of the data packet is the same as its own device ID, it means that this data packet is sent to this device, and the received data packet will be processed later. If the destination ID field of the data packet is different from its own device ID, it means that this data packet is sent to other devices, and the received data packet will be discarded without any processing.

[0088] Example 2

[0089] This embodiment provides a synchronous communication method applied to Embodiment 1, including:

[0090] The data to be sent are formed into a sending data packet by the FPGA circuit;

[0091] Sending a data packet to the first asynchronous serial port via a synchronous communication protocol;

[0092] Synchronously sending a transmit clock signal to the second asynchronous serial port;

[0093] Converting a transmitted data packet into a differential data signal through the first asynchronous serial port, and converting a transmitted clock signal into a differential clock signal through the second asynchronous serial port;

[0094] The differential data signal and the differential clock signal are synchronously sent through the first asynchronous serial port and the second asynchronous serial port.

[0095] Furthermore, when receiving data, a data packet is received through the first asynchronous serial port, a synchronous clock signal is received through the second asynchronous serial port, and the received data is sampled according to the received synchronous clock signal to complete the reception; the FPGA parses the received data packet to extract valid data.

[0096] Furthermore, when sending data, the data processing module caches the data packet in the sending buffer module, the sending module obtains the sending data from the sending buffer module, and sends the data according to the communication timing; when receiving data, the receiving module samples the data received from the first asynchronous serial port according to the synchronous clock signal received from the second asynchronous serial port, caches the sampled signal in the receiving buffer module, and the data processing module obtains the data packet from the receiving buffer for parsing and processing.

[0097] Furthermore, the data processing module performs CRC check on the received data packet. If the check is wrong, the packet is discarded. If the check is correct, the data packet is parsed to extract the data content.

[0098] Furthermore, when sending data, the sending module detects the data content in the sending data packet and inserts a binary 0 after five consecutive binary 1s in the data content; when receiving data, the receiving module detects the data content in the receiving data packet and deletes the binary 0 after five consecutive binary 1s in the data content.

[0099] Example 3

[0100] This embodiment provides an electronic device, which has the FPGA-based synchronous communication interface in Embodiment 1 and can communicate with other electronic devices through the synchronous communication interface.

[0101] like Figure 6 As shown, Figure 6FIG. 1 is a schematic diagram of the structure of an electronic device of the present invention, wherein the electronic device comprises a processor 60, a memory 61, an input device 62, an output device 63 and a communication device 64; the number of the processor 60 in the computer device can be one or more. Figure 6 The processor 50, memory 61, input device 62 and output device 63 in the electronic device can be connected by a bus or other means. Figure 6 The example of connecting through bus is taken in the following.

[0102] The memory 61 is a computer-readable storage medium that can be used to store software programs, computer executable programs, and modules. The processor 60 executes various functional applications and data processing of the electronic device by running the software programs, instructions, and modules stored in the memory 61 to implement the synchronous communication method in Embodiment 2 of the present invention.

[0103] The memory 61 may mainly include a program storage area and a data storage area, wherein the program storage area may store an operating system and at least one application required for a function; the data storage area may store data created according to the use of the terminal, etc. In addition, the memory 61 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, or other non-volatile solid-state storage device. In some instances, the memory 61 may further include a memory remotely arranged relative to the processor 60, and these remote memories may be connected to the electronic device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0104] The input device 62 may be used to receive an ID and password etc. input by a user; the output device 63 is used to output a network configuration page.

[0105] The communication device is configured with the FPGA-based synchronous communication interface in Embodiment 1 of the present invention.

[0106] Example 4

[0107] This embodiment provides a computer program product. When the computer program product runs on a computer, it enables the computer to execute the synchronous communication method in Embodiment 2 of the present invention.

[0108] The specific implementation methods described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific implementation method of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A synchronous communication interface based on FPGA, characterized in that: include: A first asynchronous serial port, used for transmitting data signals; The second asynchronous serial port is used to transmit a clock signal; An FPGA circuit is used for combining data packets and sending the data packets to the first asynchronous serial port through a synchronous communication protocol, so that the first asynchronous serial port converts the data packets into differential data signals for external transmission; as well as, The clock signal is synchronously sent to the second asynchronous serial port, so that the second asynchronous serial port converts the clock signal into a differential clock signal and sends it externally.

2. The FPGA-based synchronous communication interface according to claim 1, characterized in that: The FPGA circuit is also used to receive data packets from the first asynchronous serial port and the second asynchronous serial port, and parse the received data packets.

3. The synchronous communication interface of FPGA according to claim 1, characterized in that: The first asynchronous serial port and the second asynchronous serial port are RS422 interfaces or RS485 interfaces.

4. The FPGA-based synchronous communication interface according to claim 1, characterized in that: The FPGA circuit includes a data processing module, a sending buffer module, a sending module, a receiving buffer module, a receiving module and a clock module; The data processing module is used to combine data packets or parse data packets; The clock module is used to provide a clock signal for each module in the FPGA circuit; The sending buffer module is connected between the data processing module and the sending module, and is used for buffering the sending data packets; The receiving buffer module is connected between the data processing module and the receiving module, and is used for buffering received data packets; The sending module is used to sequentially obtain the sending data packets from the data buffer module, send the sending data packets to the first asynchronous serial port, and obtain the sending clock signal from the clock module, and synchronously send the sending clock signal to the second asynchronous serial port; The receiving module is used to obtain a received data packet and a received clock signal from the first asynchronous serial port and the second asynchronous serial port, sample the received data at each rising edge of the received clock signal, and send the sampled signal to the receiving buffer module.

5. The FPGA-based synchronous communication interface according to claim 4, characterized in that: The sending buffer module and the receiving buffer module are first-in-first-out FIFO buffers.

6. The FPGA-based synchronous communication interface according to claim 4, characterized in that: The data packet includes a data packet header, a source device ID, a destination device ID, data content, a CRC check bit, and a data packet trailer.

7. The synchronous communication interface of FPGA according to claim 6, characterized in that: When sending data, the sending module is further used to detect the data content in the sending data packet, and insert a binary 0 after five consecutive binary 1s in the data content of the sending packet; When receiving data, the receiving module is further used to detect the data content in the received data packet and delete the binary 0 after five consecutive binary 1s in the data content of the received data packet.

8. The synchronous communication interface of FPGA according to claim 1, characterized in that: The synchronous communication interface is a bus type interface.

9. A synchronous communication method, characterized in that: Applied to the FPGA-based synchronous communication interface according to any one of claims 1 to 8, the method comprising: The data to be sent are formed into a sending data packet by the FPGA circuit; Sending the transmitted data packet to the first asynchronous serial port through a synchronous communication protocol; Synchronously sending a sending clock signal to the second asynchronous serial port; Converting the transmitted data packet into a differential data signal through the first asynchronous serial port, and converting the transmitted clock signal into a differential clock signal through the second asynchronous serial port; The differential data signal and the differential clock signal are synchronously sent through the first asynchronous serial port and the second asynchronous serial port.

10. An electronic device, characterized in that: The electronic device comprises the FPGA-based synchronous communication interface according to any one of claims 1 to 8, and communicates with other electronic devices via the synchronous communication interface.

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