Novel silicon carbide MOSFET device and manufacturing method thereof

Abstract

The invention discloses a novel silicon carbide MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device and a manufacturing method thereof. The novel silicon carbide MOSFET device comprises an N + type heavily-doped silicon carbide substrate, a P type buried layer, an N-type lightly-doped primary epitaxy, a silicon dioxide buried layer, a P-type lightly-doped secondary epitaxy, a polycrystalline silicon deep groove, an N + type heavily-doped source region, a gate oxide layer, a polycrystalline silicon gate, a dielectric layer, front metal and back metal, different from the structure and the technological process of a traditional silicon carbide power MOSFET device, the factor that the channel length is unstable due to the fact that the P-type well region is subjected to long-time high-temperature transverse diffusion is avoided, and the gate oxide quality and reliability are improved; meanwhile, the area of a single device is reduced, the integration level is improved, more devices can be manufactured on the same wafer, the manufacturing cost is reduced, and the new structure can also reduce the on resistance of the devices, improve the switching speed and reduce the power consumption.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and in particular relates to a novel silicon carbide MOSFET device and a manufacturing method thereof. Background Art

[0002] The third-generation wide bandgap semiconductor material, silicon carbide (SiC), has many characteristics different from traditional silicon semiconductor materials. Its energy band gap is 2.8 times that of silicon, reaching 3.09 electron volts. The insulation breakdown field strength of silicon carbide is 5.3 times that of silicon, up to 3.2MV / cm. Therefore, in the field of high-voltage power devices, silicon carbide devices can use thinner epitaxial layers than traditional silicon materials to achieve the same withstand voltage level as traditional silicon devices, while having lower on-resistance. The forward and reverse characteristics of silicon carbide power devices change little with temperature and time, so the reliability is better, and silicon carbide devices have good reverse recovery characteristics, reverse recovery time period, small current and small switching loss, which can reduce the power consumption of the entire system. The thermal conductivity of silicon carbide is 3.3 times that of silicon, at 49w / cm·K. Therefore, compared with semiconductor devices made of silicon as a material, semiconductor devices made of silicon carbide have better characteristics when used in high temperature environments.

[0003] At present, in the application field of high-power devices, especially in the fields of rail transportation, new energy vehicles, photovoltaic power generation, etc., the requirements for power devices are getting higher and higher, not only requiring lower system power consumption and more stable high-temperature working performance, but also putting forward more stringent requirements for the miniaturization of modules and systems. Silicon carbide MOSFET power devices have many advantages in one, so they are very suitable for use in fields with high power requirements. The manufacturing process of conventional silicon carbide MOSFET power devices is to first grow a gate oxide layer, then deposit polysilicon, and then form a gate electrode made of doped polysilicon through coating, exposure, development and etching, and then perform photolithography and implantation of the P-type well region, and then diffuse the P-type well region laterally through high-temperature diffusion to form the channel region of the MOSFET. The lateral diffusion region thus formed is the channel region of the device, and the diffusion rate of impurities in silicon carbide is extremely low compared to the diffusion rate of impurities in silicon, which requires this step of the process to diffuse for a very long time at high temperature to form the required channel length. The disadvantages of this conventional manufacturing process method for silicon carbide MOSFET power devices are obvious: first, the stability of the equipment at high temperature becomes increasingly unstable as the working time increases, which in turn leads to the instability of the lateral diffusion channel length, affecting the basic performance of silicon carbide MOSFET, such as the instability of threshold voltage and breakdown voltage, poor consistency of electrical parameter results between batches, and inability to mass produce; second, in order to improve the voltage capability of silicon carbide MOSFET power devices, it is usually necessary to continuously increase the lateral diffusion channel length, which leads to an increase in the overall area of ​​the device, a decrease in the output quantity per unit wafer, and an increase in cost; third, the high-temperature and long-term lateral diffusion process is difficult to achieve in general furnace tube equipment, and requires the use of expensive special equipment, which greatly increases the manufacturing cost. Summary of the invention

[0004] In view of this, the present invention provides a new type of silicon carbide MOSFET device and a manufacturing method thereof, which is different from the structure and process flow of traditional silicon carbide power MOSFET devices, avoids the factor of unstable channel length caused by long-term high-temperature lateral diffusion of the P-type well region, improves the gate oxide quality and reliability; at the same time, it reduces the area size of a single device, improves the integration, and can manufacture more devices on the same wafer, reducing the manufacturing cost; in addition, the new structure can also reduce the on-resistance of the device, increase the switching speed, and reduce power consumption. The following technical solutions are specifically adopted to achieve this.

[0005] In a first aspect, the present invention provides a novel silicon carbide MOSFET device, comprising:

[0006] a substrate of a first conductivity type;

[0007] forming a plurality of buried layers of the second conductivity type arranged at intervals in the substrate;

[0008] A first epitaxial layer of a first conductivity type formed on the upper surface of the substrate, a second epitaxial layer of a second conductivity type formed on the first epitaxial layer, and a first oxide layer extending from the second epitaxial layer into the first epitaxial layer and arranged at intervals;

[0009] A trench extending from the upper surface of the second epitaxial layer into the first epitaxial layer and located between the first oxide layers, an implantation region of the first conductivity type located in the second epitaxial layer and arranged corresponding to the first oxide layer, and a second oxide layer formed on the upper surface of the second epitaxial layer and located on the sidewalls and bottom of the trench;

[0010] a polysilicon layer formed on an upper surface of the second oxide layer and extending from the second oxide layer between the implanted regions to within the trench;

[0011] A dielectric layer formed on the second oxide layer and the polysilicon layer, a first contact hole penetrating the dielectric layer and the second oxide layer and located on the upper surface of the implantation region, and a second contact hole located on the polysilicon layer and arranged corresponding to the trench, wherein the second oxide layer includes a first sub-oxide layer located on the second epitaxial layer and connected to the implantation region, a second sub-oxide layer located between the first contact holes and located on the sidewalls of the trench and the bottom of the trench, and the second sub-oxide layer is connected to the implantation region;

[0012] A first metal layer located on the dielectric layer and filling the first contact hole, a second metal layer located on the dielectric layer between the first metal layers and filling the second contact hole, and a third metal layer formed on the lower surface of the substrate.

[0013] As a preferred embodiment of the above technical solution, the thickness of the second epitaxial layer is smaller than the thickness of the first epitaxial layer.

[0014] As a preferred embodiment of the above technical solution, the first conductivity type is N type, and the second conductivity type is P type.

[0015] In a second aspect, the present invention further provides a method for manufacturing a novel silicon carbide MOSFET device, comprising the following steps:

[0016] providing a substrate of a first conductivity type;

[0017] forming a plurality of buried layers of the second conductivity type arranged at intervals in the substrate;

[0018] Forming a first epitaxial layer of a first conductivity type on the upper surface of the substrate, forming a first oxide layer arranged at intervals on the upper surface of the first epitaxial layer and extending into the first epitaxial layer, and forming a second epitaxial layer of a second conductivity type on the upper surface of the first epitaxial layer and covering the first oxide layer;

[0019] A trench extending from the upper surface of the second epitaxial layer into the first epitaxial layer is formed between the first oxide layers, and a second oxide layer located on the sidewalls and the bottom of the trench is formed on the upper surface of the second epitaxial layer;

[0020] forming a polysilicon layer on the upper surface of the second oxide layer and extending from the second oxide layer between the first oxide layers to the inside of the trench;

[0021] forming an implantation region of a first conductivity type in a second epitaxial layer disposed corresponding to the first oxide layer;

[0022] Forming a dielectric layer on the second oxide layer and the polysilicon layer, forming a first contact hole penetrating the dielectric layer and the second oxide layer and located on the upper surface of the implantation region, and forming a second contact hole located on the polysilicon layer and arranged corresponding to the trench, wherein the second oxide layer includes a first sub-oxide layer located on the second epitaxial layer and connected to the implantation region, and a second sub-oxide layer located between the first contact holes and located on the sidewalls of the trench and the bottom of the trench, and the second sub-oxide layer is connected to the implantation region;

[0023] A first metal layer is formed on the dielectric layer and fills the first contact holes, a second metal layer is formed on the dielectric layer between the first metal layers and fills the second contact holes, and a third metal layer is formed on the lower surface of the substrate.

[0024] As a preferred embodiment of the above technical solution, the first conductivity type is N-type, the second conductivity type is P-type, and the material of the substrate is silicon carbide.

[0025] As a preferred embodiment of the above technical solution, the thickness of the second epitaxial layer is less than the thickness of the first epitaxial layer, and the doping concentration of the first epitaxial layer is 5E14-5E15CM -3 The thickness of the first epitaxial layer is 15-20 μm, the thickness of the second epitaxial layer is 10 μm, and the doping concentration of the second epitaxial layer is 5E16-1E18CM -3 .

[0026] As a preferred embodiment of the above technical solution, the first oxide layer located on the upper surface of the first epitaxial layer and extending into the first epitaxial layer to form an interval arrangement includes:

[0027] A layer of silicon dioxide is grown on the first epitaxial layer with a thickness of

[0028] A layer of silicon nitride is deposited by low-pressure chemical vapor deposition with a thickness of 0.2 μm;

[0029] Selectively etching the silicon nitride photolithography, and removing the silicon nitride at the window by wet etching with phosphoric acid;

[0030] The photoresist is removed, and the product enters a furnace tube for local growth of a wet or dry oxide layer, and hot phosphoric acid is used to remove the remaining silicon nitride on the surface to obtain the first oxide layer.

[0031] As a preferred embodiment of the above technical solution, a trench extending from the upper surface of the second epitaxial layer to the first epitaxial layer and located between the first oxide layers is formed, comprising:

[0032] A layer of silicon dioxide is grown by wet oxidation, and a photoresist is used as a mask to define deep trench windows;

[0033] The silicon dioxide at the window is completely removed, and the silicon carbide in the window area is dry-etched using silicon carbide etching technology;

[0034] The photoresist on the surface is removed, and then the silicon dioxide on the surface is removed cleanly with hydrofluoric acid to obtain the groove.

[0035] As a preferred embodiment of the above technical solution, the groove has a depth of 12 μm, a width of 1.2 μm, and an aspect ratio of 10.

[0036] As a preferred embodiment of the above technical solution, a polysilicon layer is formed on the upper surface of the second oxide layer and extends from the second oxide layer between the first oxide layers to the inside of the trench, comprising:

[0037] The device corresponding to the groove is cleaned by using a formula of hydrochloric acid, ammonia, hydrogen peroxide and pure water, and then enters the furnace tube for dry oxidation growth to produce the second sub-oxide layer, wherein the second sub-oxide layer is a gate oxide layer, and the thickness of the gate oxide layer is

[0038] Polysilicon deposition, photolithography and etching are performed on the second sub-oxide layer to form the polysilicon layer.

[0039] The present invention provides a novel silicon carbide MOSFET device and a manufacturing method thereof, which has the following beneficial effects compared with the prior art:

[0040] 1. By using the second epitaxial layer of the second conductivity type, it is only necessary to control the impurity concentration during the growth of the second epitaxial layer to accurately control the channel concentration, which completely avoids the long-term high-temperature advancement of the channel PW required by traditional technologies, improves the electrical characteristics of silicon carbide MOSFET devices, and also improves the stability of parameters during mass production;

[0041] 2. By adding a buried layer between the two epitaxy processes, the buried layer has a high dielectric strength, so the parasitic NPN composed of the first epitaxial layer, the second epitaxial layer and the injection region completely avoids the possibility of transistor emitter and collector punch-through breakdown, improves the breakdown voltage from drain to source, and breaks through the technical bottleneck of traditional processes;

[0042] 3. After adding the first oxide layer, due to the increase in breakdown voltage, the thickness of the second epitaxial layer can be reduced as much as possible, which reduces the on-resistance of the MOSFET device, thereby increasing the switching speed, reducing power consumption, and greatly improving the performance of the MOSFET device in a high-frequency and high-power environment;

[0043] 4. By introducing the deep trench process, part of the gate oxide layer is distributed vertically, which reduces the area of ​​a single device, improves the integration of the device, and enables more devices to be produced on each wafer, greatly reducing the production cost;

[0044] 5. The pattern of the first oxide layer is exactly the same as that of the implantation area, so the same photoresist can be used in manufacturing, saving costs;

[0045] 6. Add some spaced buried layers between the substrate and the first epitaxial layer to form a parasitic NPN transistor. When the drain and source ends of the MOS tube are turned on, this parasitic NPN transistor starts to work, which can further amplify the substrate current and greatly improve the current capability of the MOSFET device. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0047] Figure 1 A schematic diagram of the structure of a novel silicon carbide MOSFET device provided by the present invention;

[0048] Figure 2 A flow chart of a method for manufacturing a novel silicon carbide MOSFET device provided by the present invention;

[0049] Figures 3 to 11 A diagram of the manufacturing process of the novel silicon carbide MOSFET device provided by the present invention.

[0050] The main component symbols are described as follows:

[0051] 1-new silicon carbide MOSFET device; 10-substrate; 11-buried layer; 12-first epitaxial layer; 13-second epitaxial layer; 14-first oxide layer; 15-trench; 16-implantation region; 17-second oxide layer; 18-polysilicon layer; 19-dielectric layer; 20-first contact hole; 21-second contact hole; 22-first sub-oxide layer; 23-second sub-oxide layer; 24-first metal layer; 25-second metal layer; 26-third metal layer. DETAILED DESCRIPTION

[0052] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.

[0053] It should be noted that when an element is referred to as being "fixed to" another element, it may be directly on the other element or there may be a central element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a central element at the same time. In contrast, when an element is referred to as being "directly on" another element, there is no intermediate element. The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are for illustrative purposes only.

[0054] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0055] See also Figure 1 The present invention provides a novel silicon carbide MOSFET device 1, comprising:

[0056] A substrate 10 of a first conductivity type;

[0057] A plurality of buried layers 11 of the second conductivity type are formed in the substrate 10 and arranged at intervals;

[0058] A first epitaxial layer 12 of a first conductivity type formed on the upper surface of the substrate 10, a second epitaxial layer 13 of a second conductivity type formed on the first epitaxial layer 12, and first oxide layers 14 extending from the second epitaxial layer 13 into the first epitaxial layer 12 and arranged at intervals;

[0059] A trench 15 extending from the upper surface of the second epitaxial layer 13 to the first epitaxial layer 12 and located between the first oxide layers 14, an implantation region 16 of the first conductivity type located in the second epitaxial layer 13 and arranged corresponding to the first oxide layer 14, and a second oxide layer 17 formed on the upper surface of the second epitaxial layer 13 and located on the sidewalls of the trench 15 and the bottom of the trench 15;

[0060] a polysilicon layer 18 formed on the upper surface of the second oxide layer 17 and extending from the second oxide layer 17 between the implantation regions 16 to the inside of the trench 15;

[0061] a dielectric layer 19 formed on the second oxide layer 17 and the polysilicon layer 18, a first contact hole 20 penetrating the dielectric layer 19 and the second oxide layer 17 and located on the upper surface of the implantation region 16, and a second contact hole 21 located on the polysilicon layer 18 and arranged corresponding to the trench 15, wherein the second oxide layer 17 includes a first sub-oxide layer 22 located on the second epitaxial layer 13 and connected to the implantation region 16, and a second sub-oxide layer 23 located between the first contact holes 20 and located on the sidewalls of the trench 15 and the bottom of the trench 15, and the second sub-oxide layer 23 is connected to the implantation region 16;

[0062] A first metal layer 24 located on the dielectric layer 19 and filling the first contact hole 20 , a second metal layer 25 located on the dielectric layer 19 between the first metal layers 24 and filling the second contact hole 21 , and a third metal layer 26 formed on the lower surface of the substrate 10 .

[0063] In this embodiment, the thickness of the second epitaxial layer 13 is less than the thickness of the first epitaxial layer 12. The first conductivity type is N type, and the second conductivity type is P type. The material of the substrate 10 is silicon carbide, and the substrate 10 is N+ heavily doped SiC. The novel silicon carbide MOSFET device 1 of the present invention mainly includes: N+ type heavily doped silicon carbide substrate, P type buried layer (PBL), N-type lightly doped primary epitaxy, silicon dioxide buried layer, P-type lightly doped secondary epitaxy, polysilicon deep trench, N+ type heavily doped source region, gate oxide layer, polysilicon gate, dielectric layer, front metal and back metal. A plurality of spaced P type buried layers are formed in the substrate 10, that is, some spaced P type buried layers are added between the N+ substrate and the N- epitaxial layer, which can further amplify the current of the substrate 10 and also improve the current capacity of the device. The first oxide layer 14 is located on the N-type lightly doped epitaxial layer, that is, a thin oxide layer grown on the first epitaxial layer 12.

[0064] It should be noted that the groove 15 extends through the second epitaxial layer 13 to the first epitaxial layer 12 and is located between the first oxide layer 14. The first oxide layer 14 can be regarded as a buried silicon dioxide layer. A second oxide layer 17 is formed on the sidewalls of the groove 15, the bottom of the groove 15 and the second epitaxial layer 13. The second oxide layer 17 includes a first sub-oxide layer 22 located on the second epitaxial layer 13 and connected to the injection area 16, and a second sub-oxide layer 23 located between the first contact holes 20 and located on the sidewalls of the groove 15 and the bottom of the groove 15. The second sub-oxide layer 23 is a gate oxide layer. The polysilicon layer 18 corresponding to the gate oxide layer is a polysilicon gate. A part of the gate oxide layer is distributed vertically, which reduces the area of ​​a single device and improves the integration of the device. The first oxide layer 14 is corresponding to the injection area 16, that is, the patterns of the two are exactly the same. The same photolithography plate can be used during manufacturing, saving manufacturing costs. The first metal layer 24 is the source metal, the second metal layer 25 is the gate metal, and the third metal layer 26 is the back drain metal. In other words, the first metal layer 24, the second metal layer 25, and the third metal layer 26 are the source, gate, and drain of the MOSFET device, respectively. The P-type buried layer added between the N+ substrate and the N]- epitaxial layer can form a parasitic NPN transistor. When the drain and source ends of the MOS tube are turned on, the parasitic NPN transistor starts to work, which can further increase the current of the substrate 10 and also improve the current capacity of the MOSFET device.

[0065] It should be understood that the first epitaxial layer 12 and the second epitaxial layer 13 have different conductivity types, and the first oxide layer 14 is located at the connection between the first epitaxial layer 12 and the second epitaxial layer 13. The first epitaxial layer 12 is N-type, the second epitaxial layer 13 is P-type, and the conductivity type of the implantation region 16 is the first conductivity type, i.e., N+ type. Since silicon dioxide has a very high dielectric strength (107V / CM), the parasitic NPN (N-epitaxial layer, P-epitaxial layer, and N+ source region) completely avoids the possibility of transistor emitter and collector punch-through breakdown, improves the breakdown voltage from the drain to the source, and breaks through the technical bottleneck of the traditional process. After adding the first oxide layer 14, due to the increase in the breakdown voltage, the thickness of the second epitaxial layer 13 can be reduced as much as possible, thereby reducing the on-resistance of the MOSFET device, improving the switching speed, reducing the power consumption, and greatly improving the performance of the MOSFET device in a high-frequency and high-power environment.

[0066] See also Figure 2 , Figures 3 to 11 The present invention also provides a method for manufacturing a novel silicon carbide MOSFET device, comprising the following steps:

[0067] S1: providing a substrate 10 of a first conductivity type;

[0068] In this embodiment, the first conductivity type is N type, the second conductivity type is P type, the material of the substrate 10 is silicon carbide, and the conductivity type of the substrate 10 is the first conductivity type, i.e., N+ heavily doped. The doping concentration of the SiC substrate is twice that of silicon, which reduces the surface resistance of the device and significantly reduces the conduction loss.

[0069] S2: forming a plurality of buried layers 11 of the second conductivity type arranged at intervals in the substrate 10;

[0070] In this embodiment, Figure 3 As shown, a plurality of second conductivity type buried layers 11 are formed by selective implantation through photolithography on an N+ heavily doped SiC substrate. The conductivity type of the buried layer 11 is the second conductivity type, namely, a P-type buried layer. The buried layer 11 is denoted as PBL.

[0071] S3: forming a first epitaxial layer 12 of a first conductivity type on the upper surface of the substrate 10, forming a first oxide layer 14 arranged at intervals on the upper surface of the first epitaxial layer 12 and extending into the first epitaxial layer 11, and forming a second epitaxial layer 13 of a second conductivity type on the upper surface of the first epitaxial layer 11 and covering the first oxide layer 14;

[0072] In this embodiment, the first oxide layer 14 is formed on the upper surface of the first epitaxial layer 12 and extends into the first epitaxial layer 12 to form an interval arrangement, including: growing a layer of silicon dioxide on the first epitaxial layer 12 with a thickness of A layer of silicon nitride is deposited by low-pressure chemical vapor deposition with a thickness of 0.2 μm; the silicon nitride is selectively etched by photolithography, and the silicon nitride at the window is removed by wet etching with phosphoric acid; the photoresist is removed, and the furnace tube is entered for local growth of a wet or dry oxide layer, and the remaining silicon nitride on the surface is removed by hot phosphoric acid to obtain the first oxide layer 14.

[0073] It should be noted that if Figure 4 As shown, an N-type lightly doped primary epitaxial layer, i.e., the first epitaxial layer 12, is grown on an N+ heavily doped SiC substrate. The doping concentration and thickness of the N-epitaxial layer are adjusted according to the specific withstand voltage of the device. The doping concentration of nitrogen ions is 5E14-5E15CM-3, and the thickness of the first epitaxial layer 12 is 15-20μm, which can achieve a breakdown voltage of 600V-1200V or more. Figure 5 As shown, a thin oxide layer is grown on the N-type lightly doped epitaxial layer, i.e., the first epitaxial layer 12, with a thickness of Then, a layer of silicon nitride (Si3N4) is deposited by CVD with a thickness of 0.2 μm. The silicon nitride is selectively etched by photolithography, and the silicon nitride at the window is removed by wet etching with phosphoric acid. Then, the photoresist is removed, and the thin oxide layer is locally grown by wet etching or dry etching in the furnace tube. The thickness of the first oxide layer 14 is 0.5 μm, and then the remaining silicon nitride on the surface is removed by hot phosphoric acid. Figure 6 As shown, a P-type lightly doped secondary epitaxial growth is first performed. When the thickness of the secondary epitaxial layer, i.e., the second epitaxial layer 13, exceeds the thickness of the silicon dioxide, i.e., the first oxide layer 14, the secondary epitaxial layer will grow laterally while growing upward until it closes and completely covers the silicon dioxide. The thickness of the second epitaxial layer 13 is 10 μm. Aluminum ions are doped in the entire secondary epitaxial growth process, and the doping concentration is 5E16-1E18CM -3 .

[0074] S4: extending from the upper surface of the second epitaxial layer 13 to the inside of the first epitaxial layer 12 to form a trench 15 located between the first oxide layers 14 , and forming a second oxide layer 17 located on the sidewalls and bottom of the trench 15 on the upper surface of the second epitaxial layer 13 ;

[0075] In this embodiment, a groove 15 extending from the upper surface of the second epitaxial layer 13 to the first epitaxial layer 12 is formed between the first oxide layers 14, including: growing a layer of silicon dioxide by wet oxidation, using photoresist as a mask and defining a deep groove window; removing the silicon dioxide at the window, and dry etching the silicon carbide in the window area by silicon carbide etching technology; removing the photoresist on the surface, and then removing the silicon dioxide on the surface with hydrofluoric acid to obtain the groove 15.

[0076] It should be noted that if Figure 7 As shown, a thin layer of silicon dioxide (SiO 2 ) layer, and then use photoresist as a mask to define a deep groove window. First, the silicon dioxide at the window is removed cleanly, and then the silicon carbide etching technology is used to dry-etch the silicon carbide in the window area, and then the photoresist on the surface is removed, and then the thin silicon dioxide layer on the surface is removed cleanly with hydrofluoric acid. The depth of groove 15 is 12μm, the width is 1.2μm, and the aspect ratio reaches 10.

[0077] S5: forming a polysilicon layer 18 on the upper surface of the second oxide layer 17 and extending from the second oxide layer 17 between the first oxide layers 14 to the inside of the trench 15;

[0078] In this embodiment, the device corresponding to the groove is cleaned by using a formula of hydrochloric acid, ammonia, hydrogen peroxide and pure water, and then enters the furnace tube for dry oxidation growth to produce the second sub-oxide layer 23, wherein the second sub-oxide layer 23 is a gate oxide layer, and the thickness of the gate oxide layer is Polysilicon deposition, photolithography and etching are performed on the second sub-oxide layer 23 to form the polysilicon layer 18 .

[0079] It should be noted that if Figure 8 As shown, a cleaning step is first performed, and the specific formula is hydrochloric acid, ammonia, hydrogen peroxide and pure water for cleaning, and then enters the furnace tube for dry oxidation growth to produce a second oxide layer 17, and then polysilicon deposition, photolithography and etching are performed to form a polysilicon gate, that is, a polysilicon layer 18. The second oxide layer 17 is a gate oxide layer, and the thickness of the gate oxide layer is

[0080] S6: forming an implantation region 16 of the first conductivity type in the second epitaxial layer 13 corresponding to the first oxide layer 14;

[0081] In this embodiment, Fig. 9 As shown, N+ type heavily doped region photolithography, implantation, stripping, and annealing processes are performed to form a nitrogen-doped source region, namely, an implantation region 16 .

[0082] S7: forming a dielectric layer 19 on the second oxide layer 17 and the polysilicon layer 18, forming a first contact hole 20 penetrating the dielectric layer 19 and the second oxide layer 17 and located on the upper surface of the implantation region 16, and forming a second contact hole 21 located on the polysilicon layer 18 and arranged corresponding to the trench 15, wherein the second oxide layer 17 includes a first sub-oxide layer 22 located on the second epitaxial layer 13 and connected to the implantation region 16, and a second sub-oxide layer 23 located between the first contact holes 20 and located on the sidewalls of the trench 15 and the bottom of the trench 15, and the second sub-oxide layer 23 is connected to the implantation region 16;

[0083] In this embodiment, Fig.10 , a dielectric layer 19 is deposited, and then photolithography and etching are performed to form gate and source contact holes, the first contact hole 20 is a source contact hole, the second contact hole 21 is a gate contact hole, the second sub-oxide layer 23 is a gate oxide layer, and the polysilicon layer 18 is located on the upper surface of the gate oxide layer between the implantation regions 16.

[0084] S8: forming a first metal layer 24 located on the dielectric layer 19 and filling the first contact holes 20 , a second metal layer 25 located on the dielectric layer 19 between the first metal layers 24 and filling the second contact holes 21 , and forming a third metal layer 26 on the lower surface of the substrate 10 .

[0085] In this embodiment, Fig.11 First, metal deposition, photolithography, and etching are performed to form gate and source metal leads, and then metal deposition is performed on the back to form drain metal leads.

[0086] It should be noted that, compared with the prior art, the present invention has the following main advantages and benefits: (1) By using a P-type epitaxial layer, the channel concentration can be precisely controlled by controlling the impurity concentration during the growth of the P-epitaxial layer, which completely avoids the need for the traditional technology to perform a long-term high-temperature advancement of the channel PW, improves the electrical characteristics of the SiC MOSFET, and greatly improves the stability of parameters during mass production; (2) By adding a silicon dioxide (SiO2) buried layer between two epitaxy processes, since SiO2 has a very high dielectric strength (107V / CM), the parasitic NPN (N-epitaxial layer, P-epitaxial layer and N+ source region) completely avoids the possibility of transistor emitter and collector punch-through breakdown, improves the breakdown voltage from drain to source, and breaks through the technical bottleneck of the traditional process; (3) After adding the SiO2 buried layer, due to the increase in the breakdown voltage, the thickness of the P-epitaxial layer can be reduced as much as possible, which brings the benefit of reducing the on-resistance of the MOSFET device, thereby increasing the switching speed, reducing power consumption, and greatly improving the MOSFET device. (4) By introducing a deep trench process, a portion of the gate oxide layer is distributed vertically, which reduces the area of ​​a single device and improves the integration of the device, allowing more devices to be produced on each wafer, greatly reducing the production cost; (5) The silicon dioxide (SiO2) buried layer pattern is exactly the same as the N+ source region pattern, so the same photolithography plate can be used during manufacturing, saving costs; (6) Some spaced P-type buried layers (PBL) are added between the N+ substrate and the N- epitaxial layer to form a parasitic NPN transistor. When the drain and source ends of the MOS tube are turned on, this parasitic NPN transistor starts to work, which can further amplify the substrate current, greatly improving the current capability of this MOSFET device.

[0087] In all examples shown and described herein, any specific values ​​should be interpreted as merely exemplary and not as limiting, and thus other examples of the exemplary embodiments may have different values.

[0088] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0089] The above-mentioned embodiments only express several implementation methods of the present invention, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the scope of the present invention. It should be pointed out that for ordinary technicians in this field, several modifications and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention.

Claims

1. A novel silicon carbide MOSFET device, characterized in that: include: a substrate of a first conductivity type; forming a plurality of buried layers of the second conductivity type arranged at intervals in the substrate; A first epitaxial layer of a first conductivity type formed on the upper surface of the substrate, a second epitaxial layer of a second conductivity type formed on the first epitaxial layer, and a first oxide layer extending from the second epitaxial layer into the first epitaxial layer and arranged at intervals; A trench extending from the upper surface of the second epitaxial layer into the first epitaxial layer and located between the first oxide layers, an implantation region of the first conductivity type located in the second epitaxial layer and arranged corresponding to the first oxide layer, and a second oxide layer formed on the upper surface of the second epitaxial layer and located on the sidewalls and bottom of the trench; a polysilicon layer formed on an upper surface of the second oxide layer and extending from the second oxide layer between the implanted regions to within the trench; A dielectric layer formed on the second oxide layer and the polysilicon layer, a first contact hole penetrating the dielectric layer and the second oxide layer and located on the upper surface of the implantation region, and a second contact hole located on the polysilicon layer and arranged corresponding to the trench, wherein the second oxide layer includes a first sub-oxide layer located on the second epitaxial layer and connected to the implantation region, a second sub-oxide layer located between the first contact holes and located on the sidewalls of the trench and the bottom of the trench, and the second sub-oxide layer is connected to the implantation region; A first metal layer located on the dielectric layer and filling the first contact hole, a second metal layer located on the dielectric layer between the first metal layers and filling the second contact hole, and a third metal layer formed on the lower surface of the substrate.

2. The novel silicon carbide MOSFET device according to claim 1, characterized in that: The thickness of the second epitaxial layer is smaller than the thickness of the first epitaxial layer.

3. The novel silicon carbide MOSFET device according to claim 1, characterized in that: The first conductivity type is N type, and the second conductivity type is P type.

4. A novel method for manufacturing a silicon carbide MOSFET device, characterized in that: The following steps are involved: providing a substrate of a first conductivity type; forming a plurality of buried layers of the second conductivity type arranged at intervals in the substrate; Forming a first epitaxial layer of a first conductivity type on the upper surface of the substrate, forming a first oxide layer arranged at intervals on the upper surface of the first epitaxial layer and extending into the first epitaxial layer, and forming a second epitaxial layer of a second conductivity type on the upper surface of the first epitaxial layer and covering the first oxide layer; A trench extending from the upper surface of the second epitaxial layer into the first epitaxial layer is formed between the first oxide layers, and a second oxide layer located on the sidewalls and the bottom of the trench is formed on the upper surface of the second epitaxial layer; forming a polysilicon layer on the upper surface of the second oxide layer and extending from the second oxide layer between the first oxide layers to the inside of the trench; forming an implantation region of a first conductivity type in a second epitaxial layer disposed corresponding to the first oxide layer; Forming a dielectric layer on the second oxide layer and the polysilicon layer, forming a first contact hole penetrating the dielectric layer and the second oxide layer and located on the upper surface of the implantation region, and forming a second contact hole located on the polysilicon layer and arranged corresponding to the trench, wherein the second oxide layer includes a first sub-oxide layer located on the epitaxial layer and connected to the implantation region, and a second sub-oxide layer located between the first contact holes and located on the sidewalls of the trench and the bottom of the trench, and the second sub-oxide layer is connected to the implantation region; A first metal layer is formed on the dielectric layer and fills the first contact holes, a second metal layer is formed on the dielectric layer between the first metal layers and fills the second contact holes, and a third metal layer is formed on the lower surface of the substrate.

5. The method for manufacturing a novel silicon carbide MOSFET device according to claim 4, characterized in that: The first conductivity type is N type, the second conductivity type is P type, and the material of the substrate is silicon carbide.

6. The method for manufacturing a novel silicon carbide MOSFET device according to claim 4, characterized in that: The thickness of the second epitaxial layer is less than that of the first epitaxial layer, and the doping concentration of the first epitaxial layer is 5E14-5E15CM -3 The thickness of the first epitaxial layer is 15-20 μm, the thickness of the second epitaxial layer is 10 μm, and the doping concentration of the second epitaxial layer is 5E16-1E18CM -3 .

7. The method for manufacturing a novel silicon carbide MOSFET device according to claim 4, characterized in that: The first oxide layer is located on the upper surface of the first epitaxial layer and extends into the first epitaxial layer to form an alternately arranged first oxide layer, including: A layer of silicon dioxide is grown on the first epitaxial layer with a thickness of A layer of silicon nitride is deposited by low-pressure chemical vapor deposition with a thickness of 0.2 μm; Selectively etching the silicon nitride photolithography, and removing the silicon nitride at the window by wet etching with phosphoric acid; The photoresist is removed, and the product enters a furnace tube for local growth of a wet or dry oxide layer, and hot phosphoric acid is used to remove the remaining silicon nitride on the surface to obtain the first oxide layer.

8. The method for manufacturing a novel silicon carbide MOSFET device according to claim 4, characterized in that: A trench extending from the upper surface of the second epitaxial layer into the first epitaxial layer and located between the first oxide layers is formed, comprising: A layer of silicon dioxide is grown by wet oxidation, and a photoresist is used as a mask to define deep trench windows; The silicon dioxide at the window is completely removed, and the silicon carbide in the window area is dry-etched using silicon carbide etching technology; The photoresist on the surface is removed, and then the silicon dioxide on the surface is removed cleanly with hydrofluoric acid to obtain the groove.

9. The method for manufacturing a novel silicon carbide MOSFET device according to claim 8, characterized in that: The groove has a depth of 12 μm, a width of 1.2 μm, and an aspect ratio of 10.

10. The method for manufacturing a novel silicon carbide MOSFET device according to claim 4, characterized in that: Forming a polysilicon layer on the upper surface of the second oxide layer and extending from the second oxide layer between the first oxide layers to the inside of the trench, comprising: The device corresponding to the groove is cleaned by using a formula of hydrochloric acid, ammonia, hydrogen peroxide and pure water, and then enters the furnace tube for dry oxidation growth to produce the second sub-oxide layer, wherein the second sub-oxide layer is a gate oxide layer, and the thickness of the gate oxide layer is Polysilicon deposition, photolithography and etching are performed on the second sub-oxide layer to form the polysilicon layer.

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