Preparation method of electronic device and electronic device
By setting a dielectric layer and metal layer on the silicon wafer, performing photolithography and wet etching, and cleaning deionized water before removing the sacrificial layer, the problem of low metal corrosion rate is solved, and the electrical performance of electronic devices is improved. reliability.
Patent Information
- Application Number
- CN202411290916.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-14
- Publication Date
- 2024-12-13
AI Technical Summary
In the existing etching metal process, the metal corrosion rate is low, resulting in the corrosion holes not being fully opened, affecting the electrical performance of micro-electromechanical chips and integrated circuit sensors.
A dielectric layer and a metal layer are arranged on one side of the silicon wafer, through the lithography process, and through wet etching is performed, and deionized water is cleaned at least once before removing the sacrificial layer, thereby increasing the corrosion rate of the sacrificial layer and the electronic device. reliability.
Avoid breakdown by cleaning deionized water, improve the conductivity of the electronic device and the corrosion rate of the sacrificial layer, so that the release hole is fully opened, and improve the reliability and yield of the electronic device.
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Figure CN119118054A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of microelectronics technology, and in particular to a method for preparing an electronic device and an electronic device. Background Art
[0002] At present, the manufacturing of micro-electromechanical chips and integrated circuit sensors involves the deposition of multiple film layers such as multiple metals and their patterning processes. Various manufacturing processes include film deposition, photolithography and etching processes. Micro-electromechanical chips such as filters form a piezoelectric structure on a wafer substrate. The piezoelectric structure includes a metal layer and a sacrificial layer. Generally, a dry etching process is used to form an etched hole on the front side of the substrate. The etched hole is connected to the sacrificial layer. The sacrificial layer is contacted by controlling the plasma, and then a wet etching process is used to remove the sacrificial layer through the etched hole.
[0003] However, in the existing metal etching process, the metal corrosion rate is low, which easily leads to the corrosion hole not being fully opened, affecting the electrical performance of the device. Summary of the invention
[0004] The embodiments of the present application provide a method for preparing an electronic device and an electronic device, which can improve the electrical performance of the electronic device.
[0005] According to a first aspect of an embodiment of the present application, a method for preparing an electronic device is provided, comprising:
[0006] A dielectric layer and a first metal layer are sequentially arranged on one side of the silicon wafer, wherein the dielectric layer includes a first hollow, and a sacrificial layer is arranged in the first hollow;
[0007] Disposing a photoresist on a side of the first metal layer away from the silicon wafer, and patterning the photoresist using a photolithography process to form a first via hole on the photoresist;
[0008] Performing electroplating on the first via hole to form a second metal layer in the first via hole;
[0009] removing the photoresist;
[0010] Sequentially wet-etching the second metal layer and the first metal layer to form a second via hole in the second metal layer and a third via hole in the first metal layer, wherein the second via hole is connected to the third via hole, to obtain a transition substrate, wherein the orthographic projections of the second via hole and the third via hole on the silicon wafer both fall within the orthographic projection of the sacrificial layer on the silicon wafer;
[0011] Cleaning the transition substrate with deionized water at least once;
[0012] The sacrificial layer is removed through the second via hole and the third via hole to obtain a cavity structure, and the cavity structure is connected to the third via hole.
[0013] In some embodiments, the transition substrate is cleaned with deionized water at least once, comprising:
[0014] Fixing the transition substrate on the suction cup, and connecting the transition substrate to the ground wire;
[0015] Rinse the surface of the transition substrate with deionized water to remove charges on the surface of the transition substrate and in the third via hole;
[0016] The suction cup is controlled to rotate so as to drive the transition substrate to rotate, wherein the rotation of the transition substrate is suitable for evaporating water on a surface of the transition substrate facing away from the silicon wafer and in the third via hole.
[0017] In some embodiments, the transition substrate is cleaned with deionized water at least once, comprising:
[0018] Soaking the transition substrate in deionized water;
[0019] The suction cup is controlled to drive the transition substrate to rotate, so as to remove impurities on the surface of the transition substrate.
[0020] In some embodiments, soaking the transition substrate in deionized water comprises:
[0021] The transition substrate is immersed in flowing deionized water.
[0022] In some embodiments, the water flow rate of the deionized water washing is 10 to 80 ml / min; and / or,
[0023] The rotation speed of the transition substrate is 300 to 500 r / min; and / or,
[0024] The temperature of the deionized water is 50 to 70°C.
[0025] In some embodiments, the transition substrate is cleaned with deionized water at least once, comprising:
[0026] The transition substrate is cleaned with deionized water at least twice, wherein the water flow rate of the two adjacent deionized water cleanings is the same, and / or the water temperature of the two adjacent deionized water cleanings is the same, and / or the rotation speed of the transition substrate in the two adjacent deionized water cleanings is the same.
[0027] In some embodiments, the number of the second via holes is plural, and / or the number of the third via holes is plural;
[0028] The orthographic projections of the plurality of second vias on the silicon wafer fall within the orthographic projections of the sacrificial layer on the silicon wafer; and / or,
[0029] The orthographic projections of the plurality of third via holes on the silicon wafer fall within the orthographic projection of the sacrificial layer on the silicon wafer.
[0030] In some embodiments, the orthographic projection of the cavity structure on the silicon wafer falls within the orthographic projection of the first metal layer on the silicon wafer; and / or,
[0031] The angle between the sidewall of the cavity structure and the first metal layer is in the range of 30° to 60°; and / or,
[0032] The angle between the sidewall of the cavity structure and the silicon wafer is in the range of 100° to 120°; and / or,
[0033] The angle between the sidewall of the third via hole and the first metal layer is 90°; and / or,
[0034] The depth of the third via hole is equal to the depth of the cavity structure; and / or,
[0035] The thickness of the silicon wafer in a direction perpendicular to the cavity structure is less than or equal to the depth of the cavity structure.
[0036] In some embodiments, the diameter of the cavity structure at a side away from the silicon wafer is smaller than the diameter of the cavity structure at a side close to the silicon wafer.
[0037] According to the first and second aspects of the embodiments of the present application, there is provided an electronic device, which is prepared according to the method for preparing the electronic device according to the first aspect.
[0038] The method for preparing an electronic device provided in an embodiment of the present application is to arrange a dielectric layer and a metal layer on one side of a silicon wafer, and wet-etch the metal layer and the dielectric layer in sequence. After the metal layer wet-etching process and before the sacrificial layer removal process, the transition substrate is cleaned with deionized water at least once, which, on the one hand, avoids breakdown of the electronic device after power-on, thereby improving the conductivity of the electronic device, and on the other hand, increases the corrosion rate of the sacrificial layer, so that the release hole of the sacrificial layer is fully opened, thereby improving the reliability and yield of the electronic device. BRIEF DESCRIPTION OF THE DRAWINGS
[0039] Figure 1 A schematic flowchart of a method for preparing an electronic device provided in an embodiment of the present application;
[0040] Figure 2 A schematic process flow chart of a method for preparing an electronic device provided in an embodiment of the present application;
[0041] Figure 3 A schematic partial structural diagram of an electronic device provided in an embodiment of the present application;
[0042] Figure 4 A schematic partial structural diagram of another electronic device provided in an embodiment of the present application;
[0043] Figure 5 A schematic partial structural diagram of another electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION
[0044] In order to better understand the technical solutions provided by the embodiments of this specification, the technical solutions of the embodiments of this specification are described in detail below through the accompanying drawings and specific embodiments. It should be understood that the embodiments of this specification and the specific features in the embodiments are detailed descriptions of the technical solutions of the embodiments of this specification, rather than limitations on the technical solutions of this specification. In the absence of conflict, the embodiments of this specification and the technical features in the embodiments can be combined with each other.
[0045] In this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or equipment. In the absence of more restrictions, the elements limited by the statement "comprise one..." do not exclude the existence of other identical elements in the process, method, article or equipment including the elements. The term "more than two" includes two or more than two situations.
[0046] At present, the manufacturing of MEMS chips and integrated circuit sensors involves the deposition of multiple metal layers and their graphic processes. The various manufacturing processes include film deposition, photolithography and etching processes. MEMS chips such as filters form a piezoelectric structure on a wafer substrate. The piezoelectric structure includes a metal layer and a sacrificial layer. Generally, a dry etching process is used to form an etched hole on the front of the substrate. The etched hole is connected to the sacrificial layer, and the sacrificial layer is contacted by controlling the plasma. Then, a wet etching process is used to remove the sacrificial layer through the etched hole. With the changes in process design and dry etching restrictions, wet etching of etched holes connecting the sacrificial layer is becoming more and more popular.
[0047] However, in the existing metal etching process, the metal corrosion rate is low, which easily leads to the corrosion hole not being fully opened, affecting the electrical performance of the device.
[0048] In view of this, the embodiments of the present application provide a method for preparing an electronic device and an electronic device, which can improve the electrical performance of the electronic device.
[0049] According to a first aspect of an embodiment of the present application, a method for preparing an electronic device is provided. Figure 1 The following is a schematic flow chart of a method for preparing an electronic device provided in an embodiment of the present application. Figure 1 As shown, the method for preparing the electronic device comprises:
[0050] S101: a dielectric layer and a first metal layer are sequentially disposed on one side of a silicon wafer, wherein the dielectric layer includes a first hollow, and a sacrificial layer is disposed in the first hollow.
[0051] Figure 2 A schematic process flow chart of a method for preparing an electronic device provided in an embodiment of the present application. Figure 2 As shown, step S101: a dielectric layer 200 and a first metal layer 300 are sequentially deposited on one side of a silicon wafer 100. Exemplarily, the dielectric layer may be a stack of silicon dioxide and silicon nitride, and the first metal layer 300 may be a stack of titanium tungsten and copper. The dielectric layer 200 includes a first hollow, and a sacrificial layer 201 is disposed in the first hollow.
[0052] S102: a photoresist is disposed on a side of the first metal layer away from the silicon wafer, and the photoresist layer is patterned by a photolithography process to form a first via hole on the photoresist layer.
[0053] For example, Figure 2 As shown, step S102: spin-coating a photoresist 400 on a surface of the first metal layer 300 away from the silicon wafer 100 , exposing and developing the photoresist 400 to complete the patterning process of the photoresist 400 , and forming a first via hole 410 in the photoresist 400 .
[0054] S103: performing electroplating on the first via hole to form a second metal layer in the first via hole.
[0055] For example, Figure 2 As shown, step S103: electroplating the first via hole 410 to form a second metal layer 420 in the first via hole 410, and the second metal layer can be copper.
[0056] S104: removing the photoresist.
[0057] For example, Figure 2 As shown, step 104: performing a wet etching process on the photoresist 400 after the electroplating process to remove the photoresist 400.
[0058] S105: wet-etching the second metal layer and the first metal layer in sequence to form a second via hole in the second metal layer and a third via hole in the first metal layer, wherein the second via hole is connected to the third via hole, and a transition substrate is obtained, wherein the orthographic projections of the second via hole and the third via hole on the silicon wafer both fall within the orthographic projection of the sacrificial layer on the silicon wafer. For example, Figure 2 As shown, step 105: wet-etch the second metal layer 420 and the first metal layer 300 using a copper etching solution and a hydrogen peroxide etching solution in sequence to form a second via hole 421 in the second metal layer, and a third via hole 310 in the first metal layer 300, the second via hole 421 is connected to the third via hole 310, and a transition substrate 500 is obtained. The orthographic projections of the second via hole 421 and the third via hole 310 on the silicon wafer 100 coincide. The orthographic projections of the second via hole 421 and the third via hole 310 on the silicon wafer 100 both fall within the orthographic projection of the sacrificial layer 201 on the silicon wafer 100.
[0059] S106: Clean the transition substrate with deionized water at least once.
[0060] Exemplarily, the transition substrate 500 is subjected to at least one deionized water cleaning, and the deionized water cleaning can be spray cleaning or immersion cleaning, and the front and back sides of the transition substrate 500 are rinsed with deionized water respectively. The deionized water cleaning can rinse away the copper etching solution and hydrogen peroxide etching solution remaining in the first metal layer. The deionized water cleaning of the transition substrate can be a single cleaning operation or multiple cleaning operations, which can prevent the residual metal etching solution from chemically reacting with the metal to generate electric charge, thereby preventing the electric charge from forming a loop with the first metal layer 300, the second metal layer 420, the metal etching solution and the sacrificial layer etching solution during the process of using hydrofluoric acid to remove the sacrificial layer. By cleaning the transition substrate with deionized water, on the one hand, the circuit is prevented from being broken down after the electronic device is powered on, thereby improving the conductivity of the electronic device, and on the other hand, the corrosion rate of the sacrificial layer is increased, so that the release hole of the sacrificial layer is fully opened, thereby improving the reliability and yield of the electronic device.
[0061] S107: removing the sacrificial layer through the second via hole and the third via hole to obtain a cavity structure, wherein the cavity structure is connected to the third via hole.
[0062] For example, Figure 2 As shown, step 107: inject hydrofluoric acid etching solution into the dielectric layer 200 through the second via hole 421 and the third via hole 310, and use hydrofluoric acid to remove the sacrificial layer to form a cavity structure 210 in the dielectric layer 200. The cavity structure 210 is formed by the first metal layer 300, the dielectric layer 200 and the silicon wafer 100. The cavity structure 210 is used to support the first metal layer 300 to prevent the first metal layer from collapsing. The third via hole 310 can be used as a release hole of the cavity structure 210 to release the sacrificial layer to the outside of the cavity structure 210.
[0063] The method for preparing an electronic device provided in an embodiment of the present application is to arrange a dielectric layer and a metal layer on one side of a silicon wafer, and wet-etch the metal layer and the dielectric layer in sequence. After the metal layer wet-etching process and before the sacrificial layer removal process, the transition substrate is cleaned with deionized water at least once, which, on the one hand, avoids breakdown of the electronic device after power-on, thereby improving the conductivity of the electronic device, and on the other hand, increases the corrosion rate of the sacrificial layer, so that the release hole of the sacrificial layer is fully opened, thereby improving the reliability and yield of the electronic device.
[0064] In some embodiments, step S105 includes: fixing the transition substrate on the suction cup and connecting the transition substrate to a ground wire. Rinse the surface of the transition substrate with deionized water to remove the charge on the surface of the transition substrate and in the third via hole. Control the suction cup to rotate to drive the transition substrate to rotate, wherein the rotation of the transition substrate is suitable for evaporating the water on the surface of the transition substrate away from the silicon wafer and in the third via hole.
[0065] Exemplarily, the transition substrate 500 is fixed on the suction cup, and the transition substrate 500 is connected to the ground wire. The transition substrate 500 is connected to the ground wire, and the charge generated by the circuit formed by the first metal layer 300, the second metal layer 400, the metal layer etching solution and the sacrificial layer 201 etching solution can be introduced into the ground. Deionized water is then used to accelerate the flow of charge, and the charge on the surface of the transition substrate 500, the second via 421 and the third via 310 is quickly removed. While the deionized water is used to clean the transition substrate 500, the suction cup carrying the transition substrate 500 is controlled to rotate, thereby driving the transition substrate 500 to perform centrifugal accelerated rotation. The deionized water on the transition substrate is quickly dried under the action of centrifugal force, and the water on the surface of the transition substrate away from the silicon wafer and the water in the third via are evaporated.
[0066] The embodiment of the present application fixes the transition substrate on the suction cup, cleans the charges on the surface of the transition substrate and the third via hole with deionized water, and controls the suction cup to rotate to accelerate the drying of the deionized water on the surface of the transition substrate and the third via hole, thereby improving the cleaning efficiency of the transition substrate, thereby speeding up the processing speed of the electronic device and saving the processing cost of the electronic device.
[0067] In some embodiments, step S105 includes: immersing the transition substrate 500 in deionized water, controlling the suction cup to drive the transition substrate to rotate, and diluting the residual corrosive liquid on the transition substrate surface 500, the second via hole 421, and the third via hole 310, and removing impurities such as metal residues and photoresist residues on the transition substrate surface 500, the second via hole 41, and the third via hole 310. The corrosive liquid and impurities on the transition substrate surface, the second via hole, and the third via hole are removed by immersion, so as to avoid splashing of the corrosive liquid and damage to other film structures. At the same time, the flow rate of deionized water can be accelerated by rotating the transition substrate, so as to efficiently complete the cleaning of the transition substrate and improve the yield of the electronic device.
[0068] In some examples, the transition substrate 500 is immersed in deionized water, and the transition substrate 500 can be immersed in flowing deionized water. The flowing deionized water can quickly wash away the diluted corrosive solution and impurities from the surface of the transition substrate 500, avoiding the deionized water from being mixed with corrosive solution and impurities, which affects the cleaning effect of the deionized water.
[0069] In some embodiments, the temperature of the deionized water can be set to 50 to 70° C. Using high-temperature deionized water for cleaning can speed up the dilution of the corrosive solution by the deionized water and improve the cleaning rate of the deionized water. The water flow rate of the deionized water cleaning can be set to 10 to 80 ml / min, and the rotation speed of the transition substrate can be set to 300 to 500 r / min. By setting the deionized water temperature, water flow rate, and transition substrate rotation speed, the parameters of the deionized water cleaning transition substrate can be effectively controlled, so that the deionized water cleaning process is simple, easy to operate, and can be mass-produced.
[0070] Exemplarily, the metal layer etching solution includes copper etching solution and hydrogen peroxide etching solution. When the residual concentration of the metal layer etching solution is greater than 70%, the water flow rate of deionized water can be set to 80ml / min, the temperature of the ionized water can be set to 70°C, and the rotation speed of the transition substrate can be set to 500r / min. When the residual concentration of the metal layer etching solution is less than 70% and greater than 50%, the water flow rate of deionized water can be set to 50ml / min, the temperature of the ionized water can be set to 60°C, and the rotation speed of the transition substrate can be set to 400r / min. When the residual concentration of the metal layer etching solution is less than 50%, the water flow rate of deionized water can be set to 10ml / min, the temperature of the ionized water can be set to 50°C, and the rotation speed of the transition substrate can be set to 300r / min. By setting the deionized water temperature, water flow rate and transition substrate rotation speed, the parameters of deionized water cleaning the transition substrate can be effectively controlled to adapt to the cleaning of transition substrates with different corrosion liquid residues, improve the cleaning efficiency of the transition substrate, and thus speed up the processing speed of electronic devices and save the processing cost of electronic devices.
[0071] In some embodiments, the deionized water cleaning of the transition substrate may be performed at least twice, the water flow rate of the two adjacent deionized water cleanings may be set to be the same, the water temperature of the two adjacent deionized water cleanings may be set to be the same, and the rotation speed of the transition substrate in the two adjacent deionized water cleanings may be set to be the same. Setting the conditions of the two adjacent deionized water cleanings to be the same can further strengthen the cleaning operation of the transition substrate, avoid the presence of metal corrosion liquid and impurities on the transition substrate, facilitate the deposition of subsequent film layers, and improve the yield of electronic devices.
[0072] In some embodiments, a plurality of second vias 421 and a plurality of third vias 310 may be provided on the transition substrate 500. The orthographic projections of the plurality of second vias 421 on the silicon wafer 100 fall within the orthographic projections of the sacrificial layer 201 on the silicon wafer 100, and the orthographic projections of the plurality of third vias 310 on the silicon wafer 100 fall within the orthographic projections of the sacrificial layer 201 on the silicon wafer 100. By providing a plurality of second vias and a plurality of third vias in communication with the cavity structure, the hydrofluoric acid etching solution enters the cavity structure through the plurality of second vias and the third vias, thereby accelerating the etching rate of the sacrificial layer, and the cavity structure can better support the film layer structure covering the upper layer of the cavity structure, thereby improving the reliability of the electronic device.
[0073] In some embodiments, the orthographic projection of the cavity structure 210 on the silicon wafer 100 falls within the orthographic projection of the first metal layer 300 on the silicon wafer 100. By setting the orthographic projection of the cavity structure 210 on the silicon wafer 100 to fall within the orthographic projection of the first metal layer 300 on the silicon wafer 100, the dielectric layer 200 can support the first metal layer 300 and the second metal layer 400, thereby preventing the dielectric layer from collapsing and causing the film layer structure above the dielectric layer to be destroyed, thereby improving the yield of electronic devices.
[0074] In some embodiments, the angle between the sidewall of the cavity structure and the first metal layer ranges from 30° to 60°, the angle between the sidewall of the cavity structure and the silicon wafer ranges from 100° to 120°, and the angle between the sidewall of the third via and the first metal layer is 90°.
[0075] Exemplarily, the angle range of the angle between the sidewall of the cavity structure 210 and the first metal layer 300 can be set to 30°, the angle range of the angle between the sidewall of the cavity structure 210 and the silicon wafer 100 can be 100°, and the angle between the sidewall of the third via 310 and the first metal layer 300 can be 90°. The angle range of the angle between the sidewall of the cavity structure 210 and the first metal layer 300 can be set to 50°, the angle range of the angle between the sidewall of the cavity structure 210 and the silicon wafer 100 can be 110°, and the angle between the sidewall of the third via 310 and the first metal layer 300 can be 90°. The angle range of the angle between the sidewall of the cavity structure 210 and the first metal layer 300 can also be set to 60°, the angle range of the angle between the sidewall of the cavity structure 210 and the silicon wafer 100 can be 120°, and the angle between the sidewall of the third via 310 and the first metal layer 300 can be 90°. By setting angle parameters such as the angle between the side wall of the cavity structure 210 and the first metal layer 300, the angle between the side wall of the cavity structure 210 and the silicon wafer 100, and the angle between the side wall of the third via 310 and the first metal layer 300, different cavity structures can be prepared according to the needs of electronic devices, thereby improving product diversity.
[0076] In some embodiments, Figure 3 The following is a schematic partial structural diagram of an electronic device provided in an embodiment of the present application. Figure 3 As shown, the depth of the third via hole 310 is equal to the depth of the cavity structure 210. Exemplarily, the depth of the third via hole 310 is the first depth h1, the depth of the cavity is the second depth h2, and the first depth h1 is equal to the second depth h2. By setting the depth of the third via hole equal to the depth of the cavity structure, the consistency of the processing dimensions between the film layers can be improved and the processing difficulty can be reduced.
[0077] In some embodiments, the thickness of the silicon wafer 100 in a direction perpendicular to the cavity structure 210 is less than or equal to the depth of the cavity structure. The thickness of the silicon wafer in a direction perpendicular to the cavity structure 210 is a first thickness h3, and the silicon wafer 100 is thinned so that the first thickness is less than or equal to the second depth h2 to meet different packaging requirements.
[0078] In some embodiments, Figure 4 This is a schematic partial structural diagram of another electronic device provided in an embodiment of the present application. Figure 4 As shown, the aperture of the cavity structure away from the silicon wafer is the first aperture L1, and the aperture of the cavity structure close to the silicon wafer is the second aperture L2. By setting the first aperture smaller than the second aperture, the hydrofluoric acid etching solution can be slowly extended to both sides of the first aperture, avoiding the second aperture being too large to cause damage to the dielectric layer and affect the service life of the electronic device.
[0079] According to a second aspect of an embodiment of the present application, an electronic device is provided, which is prepared according to the method for preparing an electronic device according to the first aspect. The electronic device may be a cavity filter, a capacitive microphone or a gas sensor. Figure 5 A schematic partial structural diagram of another electronic device provided in an embodiment of the present application. Figure 5 As shown, the electronic device includes a silicon wafer 100, a dielectric layer 200, a first metal layer 300 and a second metal layer 400. The dielectric layer 200 is disposed on one side of the silicon wafer 100, and the dielectric layer 200 includes a cavity structure 210. The dielectric layer 200 is used to support the first metal layer 300, and the first metal layer 300 is disposed between the dielectric layer 200 and the second metal layer 400. The first metal layer 300 is provided with a third via hole 310, and the second metal layer 400 is provided with a second via hole 421, and the second via hole 421 is connected to the third via hole 310. The orthographic projections of the second via hole 421 and the third via hole 310 on the silicon wafer 100 both fall within the orthographic projection of the cavity structure 210 on the silicon wafer 100. The first metal layer 300, the second metal layer 400 and the cavity structure 210 of the electronic device form a piezoelectric structure. There is no residual charge on the piezoelectric structure, which can prevent the piezoelectric structure and the residual charge from conducting and breaking down the electronic device during the use of the electrical device, thereby improving the yield and conductivity of the electronic device.
[0080] It should be noted that in the above embodiments, the description of each embodiment has its own emphasis, and for parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.
[0081] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.
[0082] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.
[0083] Although the preferred embodiments of this specification have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of this specification.
[0084] Obviously, those skilled in the art can make various changes and modifications to this specification without departing from the spirit and scope of this specification. Thus, if these modifications and variations of this specification fall within the scope of the claims of this specification and their equivalents, this specification is also intended to include these modifications and variations.
Claims
1. A method for preparing an electronic device, It is characterized in that include: A dielectric layer and a first metal layer are sequentially arranged on one side of the silicon wafer, wherein the dielectric layer includes a first hollow, and a sacrificial layer is arranged in the first hollow; Disposing a photoresist on a side of the first metal layer away from the silicon wafer, and patterning the photoresist using a photolithography process to form a first via hole on the photoresist; Performing electroplating on the first via hole to form a second metal layer in the first via hole; removing the photoresist; Sequentially wet-etching the second metal layer and the first metal layer to form a second via hole in the second metal layer and a third via hole in the first metal layer, wherein the second via hole is connected to the third via hole, to obtain a transition substrate, wherein the orthographic projections of the second via hole and the third via hole on the silicon wafer both fall within the orthographic projection of the sacrificial layer on the silicon wafer; Cleaning the transition substrate with deionized water at least once; The sacrificial layer is removed through the second via hole and the third via hole to obtain a cavity structure, and the cavity structure is connected to the third via hole.
2. The method for preparing an electronic device according to claim 1, It is characterized in that The transition substrate is cleaned with deionized water at least once, comprising: Fixing the transition substrate on the suction cup, and connecting the transition substrate to the ground wire; Rinse the surface of the transition substrate with deionized water to remove charges on the surface of the transition substrate and in the third via hole; The suction cup is controlled to rotate so as to drive the transition substrate to rotate, wherein the rotation of the transition substrate is suitable for evaporating water on a surface of the transition substrate facing away from the silicon wafer and in the third via hole.
3. The method for preparing an electronic device according to claim 1, It is characterized in that The transition substrate is cleaned with deionized water at least once, comprising: Soaking the transition substrate in deionized water; The suction cup is controlled to drive the transition substrate to rotate, so as to remove impurities on the surface of the transition substrate.
4. The method for preparing an electronic device according to claim 3, It is characterized in that Soaking the transition substrate in deionized water comprises: The transition substrate is immersed in flowing deionized water.
5. The method for preparing an electronic device according to claim 2 or 3, It is characterized in that The water flow rate of the deionized water cleaning is 10 to 80 ml / min; and / or, The rotation speed of the transition substrate is 300 to 500 r / min; and / or, The temperature of the deionized water is 50 to 70°C.
6. The method for preparing an electronic device according to claim 1, It is characterized in that The transition substrate is cleaned with deionized water at least once, comprising: The transition substrate is cleaned with deionized water at least twice, wherein the water flow rate of the two adjacent deionized water cleanings is the same; and / or, The water temperature of two adjacent deionized water washings is the same; and / or, The rotation speed of the transition substrate in two adjacent deionized water cleanings is the same.
7. The method for preparing an electronic device according to claim 1, It is characterized in that The number of the second via holes is plural, and / or the number of the third via holes is plural; The orthographic projections of the plurality of second via holes on the silicon wafer fall within the orthographic projection of the sacrificial layer on the silicon wafer; and / or, The orthographic projections of the plurality of third via holes on the silicon wafer fall within the orthographic projection of the sacrificial layer on the silicon wafer.
8. The method for preparing an electronic device according to claim 7, It is characterized in that The orthographic projection of the cavity structure on the silicon wafer falls within the orthographic projection of the first metal layer on the silicon wafer; and / or, The angle between the sidewall of the cavity structure and the first metal layer is in the range of 30° to 60°; and / or, The angle between the sidewall of the cavity structure and the silicon wafer is in the range of 100° to 120°; and / or, The angle between the sidewall of the third via hole and the first metal layer is 90°; and / or, The depth of the third via hole is equal to the depth of the cavity structure; and / or, The thickness of the silicon wafer in a direction perpendicular to the cavity structure is less than or equal to the depth of the cavity structure.
9. The method for preparing an electronic device according to claim 8, It is characterized in that The diameter of the cavity structure at a side away from the silicon wafer is smaller than the diameter of the cavity structure at a side close to the silicon wafer.
10. An electronic device, It is characterized in that The electronic device is prepared according to the method for preparing the electronic device according to any one of claims 1 to 9.