MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) photovoltaic bypass protection module and preparation method thereof

Abstract

The invention discloses an MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) photovoltaic bypass protection module and a preparation method thereof. The photovoltaic bypass protection module comprises a first conductor, a second conductor, an MOSFET device, a control chip, a capacitor and a carrier plate, wherein an insulation gap is arranged between the first electric conductor and the second electric conductor, and the carrier plate crosses the insulation gap and is connected with the first electric conductor and the second electric conductor; the carrier plate comprises an insulating substrate and a conducting layer arranged on the insulating substrate, the control chip and the capacitor are arranged on the carrier plate and are electrically connected through the conducting layer, and the control chip is electrically connected with the first conductor and the second conductor through the conducting layer; the MOSFET device is arranged on the first conductor or the second conductor, and the MOSFET device is electrically connected with the control chip, the first conductor and the second conductor. Conductive connection between parts through metal wires can be greatly reduced, the process is simplified, the cost is reduced, and the product reliability is improved.

Description

Technical Field

[0001] The present invention relates to the field of photovoltaic technology, and in particular to a MOSFET photovoltaic bypass protection module and a preparation method thereof. Background Art

[0002] The photovoltaic bypass protection module is an important component of the photovoltaic module, mainly used to improve the reliability and efficiency of the photovoltaic system. When a cell in the photovoltaic cell string is blocked, damaged or has performance degradation, resulting in current mismatch, the bypass module can provide a low-resistance bypass path for this part of the cell, allowing the current to bypass the faulty cell and continue to flow, thereby reducing the hot spot effect and maintaining the power generation efficiency of the entire photovoltaic module.

[0003] Compared with traditional photovoltaic bypass protection modules, MOSFET photovoltaic bypass protection modules have higher efficiency and stability. When used in photovoltaic systems, they can achieve more efficient power management and protection functions. MOSFET photovoltaic bypass protection modules are usually integrated in the junction box of photovoltaic modules. Their main function is to provide bypass protection under specific conditions to cope with different working conditions, such as shadow obstruction, hot spot effect or component failure, thereby ensuring the stability and efficiency of the entire photovoltaic system.

[0004] When a part of the photovoltaic cell string cannot work properly due to shading or damage, the impedance of the photovoltaic cell in this part becomes larger, which may cause the output of the entire string to be blocked and the current to decrease. After detecting this imbalance, the MOSFET photovoltaic bypass protection module will provide a relatively lower impedance path for the string current to ensure that the remaining normal parts can continue to generate electricity. And because the MOSFET photovoltaic bypass protection module has a lower on-resistance, it can significantly reduce energy loss, reduce the heating of the junction box, and improve the overall conversion efficiency of the photovoltaic system.

[0005] The disclosure of the above background technology content is only used to assist in understanding the inventive concept and technical solution of the present invention. It does not necessarily belong to the prior art of the present application, nor does it necessarily provide technical guidance. In the absence of clear evidence that the above content has been disclosed before the filing date of the present application, the above background technology should not be used to evaluate the novelty and creativity of the present application. Summary of the invention

[0006] The purpose of the present invention is to provide a MOSFET photovoltaic bypass protection module and a preparation method thereof, which can greatly reduce the use of metal wires for electrical connection between its components during production and packaging in the MOSFET photovoltaic bypass protection module, thereby simplifying the process, reducing costs and improving product reliability.

[0007] To achieve the above object, the technical solution adopted by the present invention is as follows: A MOSFET photovoltaic bypass protection module, comprising a first conductor, a second conductor, a MOSFET device, a control chip, a capacitor and a carrier; wherein an insulating gap is provided between the first conductor and the second conductor, and the carrier spans the insulating gap and connects the first conductor and the second conductor; The carrier includes an insulating substrate and a conductive layer arranged on the insulating substrate, the control chip and the capacitor are arranged on the surface of the carrier and are electrically connected through the conductive layer, and the control chip is electrically connected to the first conductor and the second conductor respectively through the conductive layer; The MOSFET device is disposed on the first conductor or the second conductor, and the MOSFET device is electrically connected to the control chip, the first conductor, and the second conductor, respectively.

[0008] Further, based on any one of the technical solutions or a combination of multiple technical solutions described above, the MOSFET device is arranged on the first conductor, one of the source and the drain of the MOSFET device is electrically connected to the first conductor, the other of the source and the drain of the MOSFET device is electrically connected to the second conductor, the gate of the MOSFET device is electrically connected to the control electrode of the control chip through a first metal conductor, and the upper surface of the MOSFET device is electrically connected to the second conductor through a second metal conductor; preferably, one of the drain and the source of the MOSFET device is arranged on the lower surface of the MOSFET device and is electrically connected to the first conductor, and the other of the drain and the source of the MOSFET device is arranged on the upper surface of the MOSFET device and is electrically connected to the second conductor through the second metal conductor.

[0009] Further, based on any one of the above technical solutions or a combination of multiple technical solutions, the lower surface of the carrier is provided with a first conductive area and a second conductive area which are insulated and isolated, the first conductive area is electrically connected to the first conductor, and the second conductive area is electrically connected to the second conductor; The upper surface of the carrier is provided with an insulated and isolated third conductive area and a fourth conductive area, the first port of the control chip is electrically connected to the third conductive area, and the second port of the control chip is electrically connected to the fourth conductive area; The third conductive region is electrically connected to the first conductive region, and the fourth conductive region is electrically connected to the second conductive region.

[0010] Furthermore, based on any one of the technical solutions or a combination of multiple technical solutions mentioned above, a fifth conductive area is also provided on the upper surface of the carrier, the control electrode of the control chip is electrically connected to the fifth conductive area, and the control electrode of the MOSFET device is electrically connected to the fifth conductive area through the second metal conductor.

[0011] Further, based on any one of the technical solutions or a combination of multiple technical solutions mentioned above, the carrier board is a PCB board, the third conductive area is electrically connected to the first conductive area through a first via, and the fourth conductive area is electrically connected to the second conductive area through a second via.

[0012] Further, based on any one of the above technical solutions or a combination of multiple technical solutions, the first conductive area and the second conductive area are conductive layers arranged on the lower surface of the insulating substrate; The third conductive region and the fourth conductive region are conductive layers arranged on the upper surface of the insulating substrate.

[0013] Further, based on any one of the above-mentioned technical solutions or a combination of multiple technical solutions, a resistance device is provided on the surface of the carrier; One end of the resistor is electrically connected to the first conductive region, and the other end of the resistor is electrically connected to the second conductive region; or one end of the resistor is electrically connected to the third conductive region, and the other end of the resistor is electrically connected to the fourth conductive region.

[0014] Further, based on any one of the above-mentioned technical solutions or a combination of multiple technical solutions, the control chip and the capacitor are both arranged on the upper surface of the carrier board; A sixth conductive area and a seventh conductive area are provided on the upper surface of the carrier board, the third port of the control chip is electrically connected to one end of the capacitor through the sixth conductive area, and the fourth port of the control chip is electrically connected to the other end of the capacitor through the seventh conductive area.

[0015] Further, based on any one of the above technical solutions or a combination of multiple technical solutions, the first metal conductor is a metal wire; and / or, The second metal conductor is a metal interconnection sheet, and a bent portion that arches upward is provided in the middle of the metal interconnection sheet.

[0016] Further, based on any one of the technical solutions or a combination of multiple technical solutions mentioned above, at least one through hole is provided on the carrier board, and the through hole is configured as a glue leakage hole or a hole for reducing mechanical stress.

[0017] Further, based on any one of the technical solutions or a combination of multiple technical solutions mentioned above, the MOSFET device is an unpackaged MOSFET wafer die.

[0018] According to another aspect of the present invention, the present invention provides a method for preparing a MOSFET photovoltaic bypass protection module, comprising the following steps: Preparing a carrier, a first conductor and a second conductor in advance, wherein the carrier comprises an insulating substrate and a conductive layer disposed on the insulating substrate; An insulating gap is arranged between the first conductor and the second conductor, the carrier board spans the insulating gap, and two ends of the carrier board are respectively connected to the first conductor and the second conductor; Disposing a MOSFET device on the first conductor and electrically connecting the first conductor, and electrically connecting the upper surface of the MOSFET device to the second conductor using a second metal conductor; The control chip and the capacitor are arranged on the carrier board, wherein the control chip and the capacitor are electrically connected through the conductive layer, and the control chip is electrically connected to the first conductive body and the second conductive body respectively through the conductive layer; A first metal conductor is used to electrically connect the gate of the MOSFET device to the control electrode of the control chip.

[0019] Furthermore, any one of the above-mentioned technical solutions or a combination of multiple technical solutions further includes the following steps: The preparation of the carrier includes: separately and insulatedly arranging a first conductive area and a second conductive area on a first surface of a prefabricated insulating substrate; separately and insulatedly arranging a third conductive area, a fourth conductive area and a fifth conductive area on a second surface of the insulating substrate, wherein the second surface is opposite to the first surface; electrically connecting the third conductive area to the first conductive area, and electrically connecting the fourth conductive area to the second conductive area; Connecting the first conductor and the second conductor using the carrier includes: electrically connecting the first conductive area to the first conductor, and electrically connecting the second conductive area to the second conductor; The control chip is arranged on the second surface of the carrier board, including: electrically connecting the first port of the control chip to the third conductive area, and electrically connecting the second port of the control chip to the fourth conductive area.

[0020] Furthermore, any one of the above-mentioned technical solutions or a combination of multiple technical solutions further includes the following steps: The preparation of the carrier further comprises: disposing a sixth conductive area and a seventh conductive area on the second surface of the carrier, wherein; The control chip and the capacitor are arranged on the second surface of the carrier, including: electrically connecting the third port and the fourth port of the control chip to the sixth conductive area and the seventh conductive area respectively, and electrically connecting the two ends of the capacitor to the sixth conductive area and the seventh conductive area respectively.

[0021] The beneficial effects brought by the technical solution provided by the present invention are as follows: a. The present invention provides a carrier including a conductive layer of an insulating substrate, connects a first conductor and a second conductor with the carrier, and provides a control chip and a capacitor on the carrier. The control chip and the conductor and the MOSFET device are electrically connected through the conductive layer on the carrier, which can greatly reduce the number of components in the MOSFET photovoltaic bypass protection module that are electrically connected through metal wiring, thereby simplifying the process, integrating the process, reducing costs, and improving product reliability; b. The present invention arranges the control chip and the capacitor on the carrier, and arranges the MOSFET device on the first conductor or the second conductor. The layout of the MOSFET photovoltaic bypass protection module can not only simplify the process, reduce metal leads, reduce costs and improve product reliability, but also has excellent heat dissipation performance; c. The present invention provides at least one through hole on the carrier board. When packaging the MOSFET photovoltaic bypass protection module, the packaging colloid leaks in from the leaking hole. On the one hand, the packaging speed can be increased, and on the other hand, the overall structural strength of the product can be improved because the glue penetrates up and down through the through hole to firmly lock the carrier board and improve the stratification. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0023] Figure 1 A three-dimensional schematic diagram of a MOSFET photovoltaic bypass protection module provided by an exemplary embodiment of the present invention; Figure 2 A schematic top view of a MOSFET photovoltaic bypass protection module provided by an exemplary embodiment of the present invention; Figure 3 A front view schematic diagram of a MOSFET photovoltaic bypass protection module provided by an exemplary embodiment of the present invention; Figure 4An exploded schematic diagram of a control chip, a capacitor and a first carrier board provided for an exemplary embodiment of the present invention; Figure 5 An exploded schematic diagram of a control chip, a capacitor and a second carrier board provided by an exemplary embodiment of the present invention; Figure 6 A bottom view of a carrier provided for an exemplary embodiment of the present invention; Figure 7 A bottom view of a carrier board with a resistor device disposed on the lower surface is provided for an exemplary embodiment of the present invention.

[0024] Among them, the figure marks include: 1-first conductor, 11-first wave structure, 2-second conductor, 21-second wave structure, 3-MOSFET device, 31-gate of MOSFET device, 4-control chip, 5-capacitor, 6-carrier, 60-through hole, 61-first conductive area, 62-second conductive area, 63-third conductive area, 64-fourth conductive area, 65-fifth conductive area, 66-sixth conductive area, 67-seventh conductive area, 68-first via hole, 69-second via hole, 7-first metal conductor, 8-second metal conductor, 81-bending portion, 10-resistance device. DETAILED DESCRIPTION

[0025] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0026] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, device, product or equipment that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or equipment.

[0027] At present, there are many technical solutions for the layout of MOSFET photovoltaic bypass protection modules, but these technical solutions all use metal connecting wires to connect the various components in the MOSFET photovoltaic bypass protection module. There are many reasons for this technical status quo. On the one hand, the use of metal connecting wires does have a relatively large advantage in reducing the volume; on the other hand, perhaps the existing gold-plated wire connection technology is also relatively mature. Therefore, technical personnel in this field will assume that the use of metal connecting wires to connect the various components in the MOSFET photovoltaic bypass protection module is the preferred solution, and will not think about other non-metallic wire connection layout solutions.

[0028] But in fact, the metal connecting wires in the MOSFET photovoltaic bypass protection module are generally gold-plated wires. It takes 5-6 gold-plated wires to complete a complete MOSFET photovoltaic bypass protection module layout. Secondly, the control chip and capacitor connections, and the control chip and MOS tube connections are all connected through gold-plated wires. In addition, in order to increase the solderable wires, it is also necessary to gold-plate or silver-plate the control chip, capacitor, and MOS tube, which further increases the cost. Therefore, the existing MOSFET photovoltaic bypass protection module is not only costly, but also has a relatively high risk of gold-plated wire breakage, which makes it difficult to further improve the yield rate of the MOSFET photovoltaic bypass protection module during the production and preparation process and the reliability during use.

[0029] In addition, the existing MOSFET photovoltaic bypass protection modules generally adopt a solution of placing the control chip and capacitor directly on the conductive copper plate, i.e., the conductor. This technical solution requires brushing a layer of insulating glue on the conductor. If the insulating glue is brushed too thin, it may cause the control chip and the capacitor to be electrically connected to the conductive copper plate below, forming a short circuit. If the insulating glue is brushed too thick, the control chip and the capacitor may not be on the same plane, thereby increasing the defective rate of wiring.

[0030] Based on the technical problems raised above, the present invention provides a MOSFET photovoltaic bypass protection module, which breaks through the inherent thinking of using metal connecting wires to connect the various components in the MOSFET photovoltaic bypass protection module in the prior art, and provides a new MOSFET photovoltaic bypass protection module layout idea, which can further reduce its production cost and improve its reliability.

[0031] In one embodiment of the present invention, a MOSFET photovoltaic bypass protection module is proposed. Figures 1 to 3 As shown, it includes a first conductor 1, a second conductor 2, a MOSFET device 3, a control chip 4, a capacitor 5 and a carrier 6; wherein an insulating gap is provided between the first conductor 1 and the second conductor 2, and the carrier 6 spans the insulating gap and connects the first conductor 1 and the second conductor 2; The carrier 6 includes an insulating substrate and a conductive layer disposed on the insulating substrate, the control chip 4 and the capacitor 5 are disposed on the carrier 6 and are electrically connected through the conductive layer, and the control chip 4 is electrically connected to the first conductor 1 and the second conductor 2 respectively through the conductive layer; The MOSFET device 3 is disposed on the first conductor 1 or the second conductor 2 , and the MOSFET device 3 is electrically connected to the control chip 4 , the first conductor 1 , and the second conductor 2 , respectively.

[0032] In one embodiment of the present invention, the carrier board 6 is a PCB board. Figure 4 and Figure 5 As shown, the carrier board 6 includes an insulating substrate and a conductive layer arranged on the insulating substrate, preferably a copper foil metal layer.

[0033] In one embodiment of the present invention, a first conductive area 61 and a second conductive area 62 are provided on the lower surface of the PCB board. In this embodiment, the first conductive area 61 is electrically connected to the first conductor 1, and the second conductive area 62 is electrically connected to the second conductor 2. Preferably, the first conductive area 61 is electrically connected to the first conductor 1 by tinning welding, and the second conductive area 62 is electrically connected to the second conductor 2 by tinning welding. In other embodiments, the first conductive area 61 can be electrically connected to the first conductor 1 and the second conductive area 62 can be electrically connected to the second conductor 2 by other means such as conductive glue.

[0034] In addition, the third conductive area 63, the fourth conductive area 64, the fifth conductive area 65, the sixth conductive area 66 and the seventh conductive area 67 are provided on the upper surface of the PCB board with insulation isolation. The control chip 4 and the capacitor 5 are welded on the PCB board. The control electrode of the control chip 4 is electrically connected to the fifth conductive area 65, the first port of the control chip 4 is welded and electrically connected to the third conductive area 63, the second port of the control chip 4 is welded and electrically connected to the fourth conductive area 64, the third port of the control chip 4 is welded and electrically connected to the sixth conductive area 66, and the fourth port of the control chip 4 is welded and electrically connected to the seventh conductive area 67. The two ends of the capacitor 5 are electrically connected to the sixth conductive area 66 and the seventh conductive area 67 respectively, thereby realizing that the third port of the control chip 4 is electrically connected to one end of the capacitor 5 through the sixth conductive area 66, and the fourth port of the control chip 4 is electrically connected to the other end of the capacitor 5 through the seventh conductive area 67. The technical solution proposed in this embodiment eliminates the metal leads used to connect the control chip 4 and the capacitor 5 in the prior art, simplifies the production process, reduces costs and improves product reliability.

[0035] The electrical connection can be achieved by welding or by gluing with conductive adhesive. Preferably, the control chip 4 and the capacitor 5 are both arranged on the PCB board by welding.

[0036] In this embodiment, the third conductive area 63 is electrically connected to the first conductive area 61, and the fourth conductive area 64 is electrically connected to the second conductive area 62. More preferably, the third conductive area 63 is electrically connected to the first conductive area 61 through a first via 68, and the fourth conductive area 64 is electrically connected to the second conductive area 62 through a second via 69. The first conductive area 61, the third conductive area 63, and the first via 68 are arranged in at least Figure 4 and Figure 5 The method shown.

[0037] exist Figure 4 In the embodiment shown, the third conductive area 63 is correspondingly arranged on the target arrangement area of ​​the control chip 4 on the carrier 6, and the third conductive area 63 is conductively connected to the lower surface of the insulating substrate through the first via 68. The first conductive area 61 is connected to the lower surface of the insulating substrate through the conductive layer ( Figure 4The first conductive area 61 is electrically connected to the first via hole 68 through the first conductive area 61 and the second conductive area 62, and is further electrically connected to the third conductive area 63. It should be noted that, for the PCB board, since both ends of the PCB board are connected to the first conductor and the second conductor through the first conductive area 61 and the second conductive area 62, respectively, the first conductive area 61 preferably extends from the location of the first via hole 68 on the lower surface of the PCB board to a metal layer far away from the location of the second conductive area 62.

[0038] exist Figure 5 In the embodiment shown, the first conductive area 61 is conductively connected to the upper surface of the insulating substrate through the first via 68. The third conductive area 63 is conductively connected to the upper surface of the insulating substrate through the conductive layer ( Figure 5 The third conductive area 63 is electrically connected to the first via hole 68 or metal connection, and further electrically connected to the first conductive area 61. It should be noted that, for the PCB board, since both the third conductive area 63 and the fourth conductive area 64 are electrically connected to the control chip 4, the third conductive area 63 is preferably extended from the location of the first via hole 68 on the upper surface of the PCB board to the metal layer close to the location of the fourth conductive area 64.

[0039] Similarly, the second conductive area 62 is electrically connected to the fourth conductive area 64 through the second via 69. Figure 4 The via-first method shown can also be used Figure 5 The rear via method shown will not be described in detail.

[0040] In one embodiment of the present invention, the first conductive area 61 and the second conductive area 62 are disposed on the lower surface of the PCB board. Figure 6 The first conductive area 61 and the second conductive area 62 are respectively arranged at the two ends of the lower surface of the PCB. The first conductive area 61 and the second conductive area 62 are equal to or close to the width of the PCB, and the length of the first conductive area 61 and the second conductive area 62 is not less than 1 / 4 of the length of the PCB. In this way, the PCB is conveniently welded with the first conductor 1 and the second conductor 2, and the reliability of both the mechanical connection and the electrical connection is relatively high.

[0041] In the above embodiment, since the third conductive area 63 is electrically connected to the first conductive area 61 through the first via 68, the fourth conductive area 64 is electrically connected to the second conductive area 62 through the second via 69, and the first conductive area 61 is electrically connected to the first conductor 1 through welding, and the second conductive area 62 is electrically connected to the second conductor 2 through welding, it is not necessary to use metal wires to electrically connect the first port of the control chip 4 to the first conductor 1, and the second port of the control chip 4 to the second conductor 2, and the process is simple and easy to implement, and the connection reliability is strong, and the risk of circuit breakage is not easy to occur during the production process.

[0042] The MOSFET device 3 preferably uses an unpackaged MOSFET wafer. The MOSFET device 3 is arranged on the first conductor 1, and the upper surface of the MOSFET device 3 is electrically connected to the second conductor 2 via the second metal conductor 8. The gate 31 of the MOSFET device 3 is electrically connected to the fifth conductive area 65 via the first metal conductor 7. Since the control electrode of the control chip 4 is electrically connected to the fifth conductive area 65, the gate of the MOSFET device 3 is electrically connected to the control electrode of the control chip 4. Figure 2 As shown, the end where the control chip 4 is located is led to an end close to the MOSFET device 3 through the fifth conductive area 65, which is convenient for wiring.

[0043] The first metal conductor 7 is preferably a gold-plated wire or a silver-plated wire. The second metal conductor 8 is preferably a metal interconnection sheet, and a bent portion 81 that arches upward is provided in the middle of the metal interconnection sheet.

[0044] In order to improve the reliability of the connection between the MOSFET device 3 and other components and the electrical performance of the product, a first metal-plated area is provided on the gate of the MOSFET device 3, and a second metal-plated area is provided on each conductive area (the first conductive area 61 to the seventh conductive area 67) at a position used for welding. The metal plating of the first metal-plated area and the second metal-plated area can be made of gold, silver or tin.

[0045] It should be noted that in other embodiments, the carrier board may not be a PCB board, as long as there is an insulating substrate and the conductive areas and the via structure conductive layer as described above are arranged on the insulating substrate, so that the conductive areas that need to be electrically connected can be electrically connected. In addition, the plating layer of each conductive area can be made of metals such as gold, silver or tin in addition to copper.

[0046] The MOSFET device 3, the control chip 4, the capacitor 5, the PCB board, the first metal conductor 7, the second metal conductor 8, and a portion of the first conductor 1 and a portion of the second conductor 2 are insulated and packaged by a plastic package.

[0047] Preferably, at least one through hole 60 is provided on the carrier board 6, and the through hole is configured as a glue leakage hole. When packaging the MOSFET photovoltaic bypass protection module, the packaging colloid leaks in from the glue leakage hole, which can improve the packaging speed on the one hand, and improve the overall structural strength of the product on the other hand, because through the through hole 60, the glue penetrates up and down to firmly lock the PCB board and improve the delamination effect (the surface of the PCB board is smooth and easy to delaminate), thereby achieving firm glue locking, improving delamination and reducing mechanical stress.

[0048] Preferably, if Figure 1 and Figure 2 As shown, a first wave structure 11 is provided at the target packaging position on the first conductor 1, and a second wave structure 21 is provided at the target packaging position on the second conductor 2. When the first conductor 1 and the second conductor 2 are insulated and packaged by a plastic package, the grooves of the first wave structure 11 and the second wave structure will be filled with epoxy resin accordingly. This structure will increase the resistance and pulling force of the two conductors to the glue, and can effectively achieve an anti-pull-off effect.

[0049] In this embodiment, the control chip 4 and the capacitor 5 are arranged on the carrier 6, and the MOSFET device 3 is arranged on the first conductor 1 or the second conductor 2. This is because the MOSFET device 3 generates a large amount of heat during operation. The layout of the MOSFET photovoltaic bypass protection module can not only simplify the process, reduce metal leads, reduce costs and improve product reliability, but also has excellent heat dissipation performance.

[0050] In one embodiment of the present invention, a resistor device 10 is mounted on the surface of the PCB board. Specifically, one end of the resistor device 10 is electrically connected to the first conductive area 61, and the other end of the resistor device 10 is electrically connected to the second conductive area 62; or, one end of the resistor device 10 is electrically connected to the third conductive area 63, and the other end of the resistor device 10 is electrically connected to the fourth conductive area 64. The resistor device can be a single resistor or a resistor module composed of multiple resistors electrically connected. By setting the resistor device, when multiple MOSFET photovoltaic bypass protection modules are used in series, the voltage balancing function can be achieved.

[0051] In one embodiment of the present invention, a MOSFET photovoltaic bypass protection module is proposed. Different from the technical solution in which the control chip 4 and the capacitor 5 are arranged on the carrier 6 and the MOSFET device 3 is arranged on the first conductor 1 or the second conductor 2 in the above-mentioned embodiment, in this embodiment, the MOSFET device 3, the control chip 4 and the capacitor 5 are all arranged on the carrier 6.

[0052] In this embodiment, an eighth conductive area is added to the upper surface of the carrier 6, and the lower surface of the MOSFET device 3 is welded and electrically connected to the eighth conductive area, and the eighth conductive area is electrically connected to the third conductive area in the above embodiment. The connection method between other components and electrodes is the same as the above embodiment, and will not be repeated. In order to improve the heat dissipation performance of the product, the size of the carrier 6 should be larger, and the area of ​​the eighth conductive area is preferably larger than the area of ​​the lower surface of the MOSFET device 3.

[0053] In one embodiment of the present invention, a method for preparing a MOSFET photovoltaic bypass protection module is provided, and the preparation method is as follows: Preparing a carrier 6, a first conductor 1 and a second conductor 2 in advance, wherein the carrier 6 includes an insulating substrate and a conductive layer disposed on the insulating substrate; An insulating gap is arranged between the first conductor 1 and the second conductor 2, so that the carrier 6 spans the insulating gap, and two ends of the carrier 6 are respectively connected to the first conductor 1 and the second conductor 2; The MOSFET device 3 is disposed on the first conductor 1, and the upper surface of the MOSFET device 3 is electrically connected to the second conductor 2 by using a second metal conductor 8; The control chip 4 and the capacitor 5 are arranged on the carrier board 6, wherein the control chip 4 and the capacitor 5 are electrically connected through the conductive layer, and the control chip 4 is electrically connected to the first conductive body 1 and the second conductive body 2 respectively through the conductive layer; The gate of the MOSFET device 3 is electrically connected to the control electrode of the control chip 4 by using a first metal conductor 7 .

[0054] Preferably, the prefabricated carrier board 6 is specifically a prefabricated PCB board. The PCB board includes an insulating substrate and a first conductive area 61, a second conductive area 62, a third conductive area 63, a fourth conductive area 64, a fifth conductive area 65, a sixth conductive area 66 and a seventh conductive area 67. The first conductive area 61 and the second conductive area 62 are arranged at two ends of the lower surface of the insulating substrate, the third conductive area 63, the fourth conductive area 64, the fifth conductive area 65, the sixth conductive area 66 and the seventh conductive area 67 are arranged in a separated and insulated manner on the upper surface of the insulating substrate, and the third conductive area 63 is electrically connected to the first conductive area 61 through a first via 68, and the fourth conductive area 64 is electrically connected to the second conductive area 62 through a second via 69.

[0055] An insulating gap is configured between the first conductor 1 and the second conductor 2 so that the carrier 6 spans the insulating gap, the first conductive area 61 of the carrier 6 is welded and electrically connected to the first conductor 1, and the second conductive area 62 of the carrier 6 is welded and electrically connected to the second conductor 2.

[0056] The MOSFET device 3 is welded on the first conductor 1 , and the upper surface of the MOSFET device 3 is welded and connected to the second conductor 2 by a metal conductor.

[0057] The control chip 4 and the capacitor 5 are welded to the upper surface of the carrier board 6. Specifically, the first port of the control chip 4 is welded and connected to the third conductive area 63, and the source of the control chip 4 is welded and electrically connected to the fourth conductive area 64. The third port and the fourth port of the control chip 4 are welded and electrically connected to the sixth conductive area 66 and the seventh conductive area 67, respectively, and the two ends of the capacitor 5 are welded and connected to the sixth conductive area 66 and the seventh conductive area 67, respectively.

[0058] Thereby, the control chip 4 and the capacitor 5 are electrically connected through the conductive layer on the upper surface of the carrier 6 , and the control chip 4 is electrically connected to the MOSFET device 3 , the first conductor 1 , and the second conductor 2 , respectively.

[0059] It should be noted that, in a specific embodiment, the control chip adopts an ideal diode control chip, the first port of which is the anode of the ideal diode control chip, connected to the source of the MOSFET device, the second port of the ideal diode control chip is the cathode of the ideal diode control chip, connected to the drain of the MOSFET device, and the third port and the fourth port are respectively the charge pump output ports of the ideal diode control chip, connected to the external charge pump capacitor, and connected to the two ends of the charge pump capacitor. The control pole of the ideal diode control chip is a gate drive output port, connected to the gate of the external MOSFET. The lower surface of the MOSFET device is provided with one of the source and the drain and is electrically connected to one of the two conductors; the upper surface of the MOSFET device is provided with the other of the source and the drain and is electrically connected to the second metal conductor. It should be noted that in other specific embodiments, the control chip can also adopt other control chips. In practical applications, the corresponding control chip is selected according to the functional requirements and application requirements of the MOSFET photovoltaic bypass protection module, and the protection scope of this application is not limited by the specific selection of the control chip.

[0060] It should be noted that the above-mentioned MOSFET photovoltaic bypass protection module preparation method embodiment and the MOSFET photovoltaic bypass protection module embodiment belong to the same inventive concept, and the entire content of the MOSFET photovoltaic bypass protection module embodiment is incorporated into the MOSFET photovoltaic bypass protection module preparation method embodiment by reference.

[0061] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0062] The above is only a specific implementation of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. A MOSFET photovoltaic bypass protection module, characterized in that: The device comprises a first conductor (1), a second conductor (2), a MOSFET device (3), a control chip (4), a capacitor (5) and a carrier (6); wherein an insulating gap is provided between the first conductor (1) and the second conductor (2), and the carrier (6) spans the insulating gap and connects the first conductor (1) and the second conductor (2); The carrier (6) comprises an insulating substrate and a conductive layer arranged on the insulating substrate, the control chip (4) and the capacitor (5) are arranged on the carrier (6) and are electrically connected via the conductive layer, and the control chip (4) is electrically connected to the first conductor (1) and the second conductor (2) respectively via the conductive layer; The MOSFET device (3) is arranged on the first conductor (1) or the second conductor (2), and the MOSFET device (3) is electrically connected to the control chip (4), the first conductor (1) and the second conductor (2) respectively.

2. The MOSFET photovoltaic bypass protection module according to claim 1, characterized in that: The MOSFET device (3) is arranged on the first conductor (1); the gate of the MOSFET device (3) is electrically connected to the control electrode of the control chip (4) via a first metal conductor (7); one of the drain and the source of the MOSFET device is electrically connected to the first conductor; and the other of the drain and the source of the MOSFET device is electrically connected to the second conductor via a second metal conductor.

3. The MOSFET photovoltaic bypass protection module according to claim 2, characterized in that: The lower surface of the carrier (6) is provided with an insulated and isolated first conductive area (61) and a second conductive area (62), the first conductive area (61) being electrically connected to the first conductor (1), and the second conductive area (62) being electrically connected to the second conductor (2); The upper surface of the carrier (6) is provided with an insulated and isolated third conductive area (63) and a fourth conductive area (64); the control chip (4) is arranged on the upper surface of the carrier (6) and its first port is electrically connected to the third conductive area (63); and the second port of the control chip (4) is electrically connected to the fourth conductive area (64); The third conductive region (63) is electrically connected to the first conductive region (61), and the fourth conductive region (64) is electrically connected to the second conductive region (62).

4. The MOSFET photovoltaic bypass protection module according to claim 3, characterized in that: A fifth conductive area (65) is also provided on the upper surface of the carrier board (6), the control electrode of the control chip (4) is electrically connected to the fifth conductive area (65), and the gate (31) of the MOSFET device (3) is electrically connected to the fifth conductive area (65) via the second metal conductor (8).

5. The MOSFET photovoltaic bypass protection module according to claim 3, characterized in that: The carrier board (6) is a PCB board, the third conductive area (63) is electrically connected to the first conductive area (61) through a first via hole (68), and the fourth conductive area (64) is electrically connected to the second conductive area (62) through a second via hole (69).

6. The MOSFET photovoltaic bypass protection module according to claim 5, characterized in that: The first conductive area (61) and the second conductive area (62) are conductive layers arranged on the lower surface of the insulating substrate; The third conductive region (63) and the fourth conductive region (64) are conductive layers arranged on the upper surface of the insulating substrate.

7. The MOSFET photovoltaic bypass protection module according to claim 3, characterized in that: A resistance device (10) is provided on the surface of the carrier board (6); One end of the resistor device (10) is electrically connected to the first conductive area (61), and the other end of the resistor device (10) is electrically connected to the second conductive area (62); or one end of the resistor device (10) is electrically connected to the third conductive area (63), and the other end of the resistor device (10) is electrically connected to the fourth conductive area (64).

8. The MOSFET photovoltaic bypass protection module according to claim 2, characterized in that: The control chip (4) and the capacitor (5) are both arranged on the upper surface of the carrier board (6); A sixth conductive area (66) and a seventh conductive area (67) are provided on the upper surface of the carrier board (6); the third port of the control chip (4) is electrically connected to one end of the capacitor (5) through the sixth conductive area (66); and the fourth port of the control chip (4) is electrically connected to the other end of the capacitor (5) through the seventh conductive area (67).

9. The MOSFET photovoltaic bypass protection module according to claim 2, characterized in that: The first metal conductor (7) is a metal wire; and / or, The second metal conductor (8) is a metal interconnection sheet, and a bent portion (81) that arches upward is provided in the middle of the metal interconnection sheet.

10. The MOSFET photovoltaic bypass protection module according to claim 1, characterized in that: The carrier plate (6) is provided with at least one through hole (60); and / or, The MOSFET device (3) is an unpackaged MOSFET wafer bare chip.

11. A method for preparing a MOSFET photovoltaic bypass protection module, characterized in that: The following steps are involved: Preparing a carrier (6), a first conductor (1) and a second conductor (2) in advance, wherein the carrier (6) comprises an insulating substrate and a conductive layer arranged on the insulating substrate; An insulating gap is arranged between the first conductor (1) and the second conductor (2), the carrier (6) spans the insulating gap, and two ends of the carrier (6) are respectively connected to the first conductor (1) and the second conductor (2); The MOSFET device (3) is arranged on the first conductor (1) and electrically connected to the first conductor (1), and the upper surface of the MOSFET device (3) is electrically connected to the second conductor (2) using a second metal conductor (8); The control chip (4) and the capacitor (5) are arranged on the carrier board (6), the control chip (4) and the capacitor (5) are electrically connected via the conductive layer, and the control chip (4) is electrically connected to the first conductive body (1) and the second conductive body (2) respectively via the conductive layer; A first metal conductor (7) is used to electrically connect the gate of the MOSFET device (3) and the control electrode of the control chip (4).

12. The method for preparing a MOSFET photovoltaic bypass protection module according to claim 11, characterized in that: The following steps are also included: The preparation of the carrier (6) comprises: separately and insulatedly arranging a first conductive area (61) and a second conductive area (62) on a first surface of a prefabricated insulating substrate; separately and insulatedly arranging a third conductive area (63), a fourth conductive area (64) and a fifth conductive area (65) on the second surface of the insulating substrate, the second surface being above and below the first surface, the third conductive area (63) being electrically connected to the first conductive area (61), and the fourth conductive area (64) being electrically connected to the second conductive area (62); Using the carrier board (6) to connect the first conductor (1) and the second conductor (2) comprises: electrically connecting the first conductive area (61) to the first conductor (1), and electrically connecting the second conductive area (62) to the second conductor (2); The control chip (4) is arranged on the second surface of the carrier board (6), comprising: electrically connecting the first port of the control chip (4) to the third conductive area (63), and electrically connecting the second port of the control chip (4) to the fourth conductive area (64).

13. The method for preparing a MOSFET photovoltaic bypass protection module according to claim 12, characterized in that: The following steps are also included: The preparation of the carrier (6) further comprises: arranging a sixth conductive area (66) and a seventh conductive area (67) on the second surface of the carrier (6); The control chip (4) and the capacitor (5) are arranged on the second surface of the carrier board (6), comprising: electrically connecting the third port and the fourth port of the control chip (4) to the sixth conductive area (66) and the seventh conductive area (67) respectively, and electrically connecting the two ends of the capacitor (5) to the sixth conductive area (66) and the seventh conductive area (67) respectively.

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