Diamond-based CMOS (Complementary Metal Oxide Semiconductor) inverter and preparation method thereof

Abstract

The invention belongs to the technical field of semiconductor devices, and discloses a diamond-based CMOS (complementary metal oxide semiconductor) inverter and a preparation method thereof. The diamond-based CMOS inverter comprises a diamond substrate, a monocrystalline diamond film, a hydrogen terminal region, a mesa isolation region, an n-type oxide semiconductor layer, a first source electrode, a first drain electrode, a second source electrode, a second drain electrode, a first gate dielectric layer, a first gate electrode, a second gate dielectric layer and a second gate electrode. The first drain electrode and the second drain electrode are in metal interconnection; the first gate electrode and the second gate electrode are metal-interconnected. The diamond-based CMOS phase inverter is prepared by combining the p-type hydrogen terminal diamond and the n-type oxide semiconductor, so that the technical problem that an n-type MOS device is difficult to realize by the diamond at present is effectively avoided, respective advantages of the diamond and the n-type oxide semiconductor are fully exerted, and the high-performance diamond-based monolithic integrated CMOS phase inverter is realized.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a diamond-based CMOS inverter (Complementary Metal-Oxide-Semiconductor) and a preparation method thereof. Background Art

[0002] With the application of the first-generation semiconductor materials silicon and germanium in the field of electronic devices, human scientific and technological life has entered the fast lane. Driven by scientific and technological progress and the demand for the development of integrated circuits, the second-generation semiconductor material gallium arsenide and the third-generation semiconductor materials silicon carbide and gallium nitride have also been developed and utilized. Moore's Law requires the integration of more electronic devices per unit area, resulting in increasingly prominent problems such as device heat dissipation, gate breakdown, and tunneling leakage current. To solve these problems, people gradually turn their attention to emerging semiconductor materials.

[0003] Compared with other semiconductor materials, diamond has a wide bandgap, high mobility, high thermal conductivity, large Johnson, Baliga and Keyes quality factors, and its electrical properties are significantly better than those of other three generations of semiconductor materials, making diamond-based electronic devices better than other semiconductor electronic devices. At the same time, it covers the application fields of output power and operating frequency to the greatest extent, and is very suitable for the preparation of ultra-high frequency, ultra-high power, high temperature resistant and radiation resistant electronic devices. Studies in the prior art have shown that the electrons in the diamond valence band on the hydrogen terminal surface are transferred to the lowest unoccupied molecular orbital LOMO (Lowest Occupied Molecular Orbital) in the adsorbed molecule, resulting in the formation of a two-dimensional hole gas on the diamond surface, which can obtain 10 12 cm -2 ~10 14 cm -2 The surface carrier concentration, and 20cm 2 ·V -1 ·s -1 ~680cm 2 ·V -1 ·s -1 The carrier mobility is within the range of 2.17 W / m and 1.34 W, so it can be used to prepare high-performance p-type field-effect transistors.

[0004] As an important component in the application of logic circuits, the design of inverters has always been a research hotspot. At present, diamond-based devices mainly adopt a normally open / normally closed structure, also known as an E / D logic inverter. However, due to the presence of depletion-type devices, the on-current of the inverter is seriously increased, resulting in energy waste. In applications, CMOS inverters have become the most popular technology due to their low power consumption, fast switching speed, high gain and strong anti-interference ability. However, due to technical limitations, the n-type doping of diamond materials has not yet met the requirements for the use of electronic devices, so diamond-based CMOS devices cannot be realized. Summary of the invention

[0005] In order to solve the above-mentioned deficiencies in the prior art, the present invention provides a diamond-based CMOS inverter and a method for preparing the same.

[0006] A diamond-based CMOS inverter of the present invention comprises a diamond substrate, a single crystal diamond film, a hydrogen terminal region, a table isolation region, an n-type oxide semiconductor layer, a first source electrode, a first drain electrode, a first gate dielectric layer, a first gate electrode, a second source electrode, a second drain electrode, a second gate dielectric layer and a second gate electrode.

[0007] It should be noted that, in order to overcome the defect that n-type doped diamond materials in the prior art are difficult to meet the requirements for use in electronic devices, the present invention uses a diamond substrate as a base, which can not only prepare for the subsequent construction of a voltage-resistant and heat-resistant diamond-based CMOS device, but also provide a good heat dissipation effect for the overall CMOS inverter device structure. In some preferred embodiments of the present invention, the diamond substrate used is a homogeneous or heterogeneous diamond substrate prepared by high temperature and high pressure technology or vapor phase epitaxy technology, such as homoepitaxial single crystal diamond or heteroepitaxial single crystal diamond, including single crystal diamond, to ensure that a pure diamond substrate can be obtained.

[0008] In some preferred embodiments of the present invention, a single crystal diamond film is also provided on the surface of the diamond substrate as a functional layer, that is, the single crystal diamond film is used as the basis for preparing a diamond-based CMOS device. In order to ensure that the single crystal diamond film provided on the surface of the diamond substrate can achieve the above-mentioned effect, in some preferred embodiments of the present invention, the thickness of the single crystal diamond film is 50nm to 5mm.

[0009] In some preferred embodiments of the present invention, the single crystal diamond film is obtained by depositing on the diamond substrate by chemical vapor deposition. The resistivity of the single crystal diamond film deposited by the present invention by chemical vapor deposition is >100MΩ·cm to ensure the insulation of the formed single crystal diamond film. The root mean square surface roughness of the single crystal diamond film of the present invention is ≤0.5nm, and the root mean square surface roughness is related to the p-type conductive channel carrier mobility in the hydrogen terminal region. By controlling the root mean square surface roughness ≤0.5nm, it is beneficial to regulate the p-type conductive channel carrier mobility in the hydrogen terminal region to 20cm 2 / V·s~2500cm 2 / V·s. The half-peak width of the Raman curve of the single crystal diamond film of the present invention is ≤2cm -1 , the half-peak width of the XRD rocking curve is ≤30arcsec, thereby ensuring that the quality of the obtained single-crystal diamond film material is at the electronic device level.

[0010] The present invention further provides a hydrogen termination region on the single crystal diamond film so that the hydrogen termination region serves as a p-type conductive channel. In order to ensure that the hydrogen termination region provided on the single crystal diamond film can be used as a p-type conductive channel, in some preferred embodiments of the present invention, the surface carrier concentration of the p-type conductive channel in the hydrogen termination region is 1×10 12 cm -2 ~5×10 14 cm -2 , the mobility is 20cm 2 / V·s~2500cm 2 / V·s. In some other preferred embodiments of the present invention, the thickness of the hydrogen terminal region is 1 nm to 20 nm.

[0011] The present invention also provides a mesa isolation region on the single crystal diamond film, and the mesa isolation region is located around the hydrogen termination region to serve as an insulating layer to achieve electrical isolation between devices. In some preferred embodiments of the present invention, the mesa isolation region is oxygen-terminated diamond.

[0012] The present invention further provides an n-type oxide semiconductor layer on the mesa isolation region to serve as an n-type conductive channel, and carriers migrate in the n-type conductive channel. In order to ensure that the n-type oxide semiconductor layer can achieve the above-mentioned effects, in some feasible embodiments of the present invention, the material of the n-type oxide semiconductor layer is any one or more of tin dioxide, zinc oxide, indium oxide, zirconium dioxide, indium tin oxide, aluminum zinc oxide and indium gallium zinc oxide. In some feasible embodiments of the present invention, when the n-type oxide semiconductor layer is provided on the mesa isolation region, any one of electron beam evaporation, magnetron sputtering, metal organic chemical vapor deposition, laser pulse deposition, atomic layer deposition and sol-gel is used for deposition.

[0013] See also Figure 1 In order to construct a complete logic device, the present invention provides a first source electrode and a first drain electrode at both ends of the n-type oxide semiconductor layer, and the first source electrode and the first drain electrode both form an ohmic contact with the n-type oxide semiconductor layer; a second source electrode and a second drain electrode are provided at both ends of the hydrogen terminal region, and the second source electrode and the second drain electrode both form an ohmic contact with the hydrogen terminal region. The first drain electrode and the second drain electrode are metal interconnected to serve as the output of the CMOS inverter; the first gate electrode and the second gate electrode are metal interconnected to serve as the input of the CMOS inverter.

[0014] In some preferred embodiments of the present invention, the materials of the first source electrode, the first drain electrode, the second source electrode and the second drain electrode are selected from any one or more of Au, Pd, Ir, Pt and Ti to achieve ohmic contact and reduce resistance.

[0015] To ensure that the first drain electrode and the second drain electrode are metal interconnected, and the first gate electrode and the second gate electrode are metal interconnected, in some preferred embodiments of the present invention, the first drain electrode and the second drain electrode are metal interconnected through a first interconnection line, so that the first drain electrode and the second drain electrode are connected to each other and have the same potential, and then serve as the signal output of the CMOS inverter. The first gate electrode and the second gate electrode are metal interconnected through a second interconnection line, so that the first gate electrode and the second gate electrode are metal interconnected, so that the first gate electrode and the second gate electrode are connected to each other and have the same potential, and then serve as the signal input of the CMOS inverter.

[0016] It should also be emphasized that the present invention further provides a first gate dielectric layer on the n-type oxide semiconductor layer so that the first gate dielectric layer improves gate control and reduces gate leakage current. A first gate electrode is provided on the first gate dielectric layer so that the first gate electrode provides a gate voltage to regulate the n-type conductive channel current. The present invention further provides a second gate dielectric layer on the hydrogen terminal region, and the function of the second gate dielectric layer is equivalent to the first gate dielectric layer. A second gate electrode is provided on the second gate dielectric layer, and the function of the second gate electrode is equivalent to the first gate electrode.

[0017] In some feasible embodiments of the present invention, the materials of the first gate dielectric layer and the second gate dielectric layer are selected from Al2O3, SiO2, SiN x , HfO2 and MoO3, so as to achieve the purpose of reducing leakage.

[0018] In some feasible embodiments of the present invention, the materials of the first gate electrode and the second gate electrode are selected from any one or more of Al, Zr, Hf and Mo.

[0019] A method for preparing a diamond-based CMOS inverter of the present invention comprises the following steps:

[0020] A diamond substrate is provided as a base.

[0021] A single crystal diamond layer is deposited on the surface of the diamond substrate to form a single crystal diamond thin film on the surface of the diamond substrate.

[0022] It should be noted that, in order to prevent the impurities that may exist on the surface of the diamond substrate from affecting the quality and performance of the subsequently formed device, the diamond substrate needs to be pretreated before forming the single crystal diamond film to remove the impurities on the surface of the diamond substrate, and at the same time facilitate the subsequent single crystal diamond film to better combine with the surface of the diamond substrate. In order to ensure that the above effects can be achieved through pretreatment, in some feasible embodiments of the present invention, the pretreatment is achieved by the following steps: the diamond substrate is cleaned and blown dry for standby use, that is, a clean diamond substrate is obtained.

[0023] In order to ensure that a single crystal diamond film can be formed on the surface of the diamond substrate, in some preferred embodiments of the present invention, a chemical vapor deposition method is used for preparation, and the specific steps are as follows: placing the diamond substrate in a chamber of a chemical vapor deposition device and evacuating the chamber to a vacuum of ≤10 -1 Pa, after the pressure is stable, hydrogen is introduced, the hydrogen flow rate is 100sccm~500sccm, the microwave source is turned on and the power is slowly increased to 600W~1500W, the hydrogen plasma atmosphere is maintained for 1min~2h, the microwave source is turned off, the hydrogen flow is maintained, and the sample is cooled to room temperature, the hydrogen is turned off, and the sample is taken out. The single crystal diamond film formed by the chemical vapor deposition method of the present invention is tested and shows that the resistivity of the single crystal diamond film is ≥100MΩ·cm, and its root mean square surface roughness is ≤0.5nm, and its Raman curve half peak width is ≤2cm -1 , the half-peak width of the XRD (X-ray diffraction) rocking curve is ≤30arcsec.

[0024] The single crystal diamond film is subjected to hydrogenation treatment to form a two-dimensional hole gas conductive layer on the surface of the single crystal diamond film.

[0025] Using photolithography and etching technology, a partial area of ​​the two-dimensional hole gas conductive layer is etched, and the unetched area still retains the characteristics of the two-dimensional hole gas conductive layer to form a hydrogen terminal area; the etched area forms a mesa isolation area.

[0026] It should be noted that, in order to ensure that the formed hydrogen terminal region can be used as a p-type conductive channel, the present invention preferably adopts a hydrogenation treatment method to allow hydrogen to react with the carbon on the surface of the single crystal diamond film, thereby converting the carbon layer on the surface of the single crystal diamond film into a carbon-hydrogen terminal layer, that is, a two-dimensional hole gas conductive layer is formed in situ on the surface of the single crystal diamond film, and according to the size of the actual required hydrogen terminal region, other regions are etched so that the unetched region still retains the characteristics of the two-dimensional hole gas conductive layer, forming a hydrogen terminal region to serve as a p-type conductive channel; and the etched region is oxygen-terminated diamond, which serves as a table isolation region to achieve electrical isolation between devices.

[0027] In order to ensure that a two-dimensional hole gas conductive layer can be formed on the surface of the single crystal diamond film through hydrogenation treatment, in some preferred embodiments of the present invention, the hydrogenation treatment is carried out in hydrogen plasma or hydrogen atmosphere, and the hydrogen flow rate is 50sccm to 1000sccm, so as to provide hydrogen through hydrogen plasma or hydrogen atmosphere to achieve the above reaction.

[0028] In order to further ensure that a two-dimensional hole gas conductive layer can be formed on the surface of the single crystal diamond film by hydrogenation treatment, in some preferred embodiments of the present invention, the reaction temperature of the hydrogenation treatment is 500°C to 900°C. At this temperature, the carbon layer on the surface of the single crystal diamond film is converted into a carbon-hydrogen terminal layer by hydrogen plasma or hydrogen, thereby forming a two-dimensional hole gas conductive layer on the surface of the single crystal diamond film. In order to ensure that a two-dimensional hole gas conductive layer with a carbon-hydrogen terminal layer can be formed at this reaction temperature, in some preferred embodiments of the present invention, the reaction time of the hydrogenation treatment is 10s to 2h. And the carrier concentration of the two-dimensional hole gas conductive layer of the present invention (that is, the carrier concentration of the p-type conductive channel in the hydrogen terminal region) is 1×10 12 cm -2 ~5×10 14 cm -2 , the mobility is 20cm 2 / V·s~2500cm 2 / V·s.

[0029] It should be noted that in order to facilitate the formation of the hydrogen termination region and the mesa isolation region, in some preferred embodiments of the present invention, a mask method is adopted, that is, according to actual needs, a mask plate matching the actual required p-type channel size is selected to form the required photoresist pattern, and then the uncovered area of ​​the two-dimensional hole gas conductive layer is etched using photolithography technology, so that the etched area forms a mesa isolation region, while the unetched area still retains the characteristics of the two-dimensional hole gas conductive layer to form a hydrogen termination region.

[0030] In order to ensure that the two-dimensional hole gas conductive layer can be formed into a hydrogen terminal region and a mesa isolation region by combining a mask method with a photolithography technique, in some preferred embodiments of the present invention, the following steps are performed:

[0031] The diamond substrate material with a two-dimensional hole gas conductive layer formed on the surface is ultrasonically cleaned with acetone, isopropanol, and deionized water, and then dried for use. Subsequently, a layer of photoresist is spin-coated on the surface of the sample, and the diamond substrate material with the photoresist spin-coated is baked at 85°C to 95°C for 60 to 120s, and a designed mask is used for ultraviolet lithography exposure for 2s to 8s, and developed for 50s to 70s; so that the photoresist only covers the p-type channel. Then, reactive ion etching is used to form a mesa isolation area, and finally acetone is used to remove the photoresist on the surface of the sample, that is, the two-dimensional hole gas conductive layer is formed into a hydrogen terminal area and a mesa isolation area, and a diamond substrate material with a hydrogen terminal area and a mesa isolation area on the surface is obtained. Among them, during etching, the plasma power used is 30W to 300W, and the rate is 1nm / min to 1000nm / min.

[0032] After depositing a protective layer on the hydrogen terminal area using a deposition technique, an oxide layer is deposited on the surface of the sample deposited with the protective layer, and an n-type channel pattern is etched on the surface of the oxide layer to form an n-type oxide semiconductor layer as an n-type conductive channel.

[0033] It should be noted that the present invention takes into account that during the specific deposition, the entire surface of the sample will be exposed to the preparation environment. In order to avoid the hydrogen terminal area from being damaged during the deposition of the oxide layer and sample processing, it is necessary to first deposit a protective layer on the hydrogen terminal area, and then perform deposition processing on the sample to deposit an oxide layer on the surface of the sample deposited with the protective layer, and then etch to form an n-type channel pattern, and remove the protective layer on the hydrogen terminal area, that is, to achieve only a layer of oxide layer deposited on the surface of the mesa isolation area. Considering that the deposited protective layer must not only protect the hydrogen terminal area to avoid accidental etching, but also be easy to remove without damaging the hydrogen terminal area, in some preferred embodiments of the present invention, the material of the protective layer is selected from metal or dielectric material, and the thickness of the protective layer is 130nm to 170nm. Among them, the metal can be selected from gold. The dielectric material can be selected from SiO2 or Si3N4. It should be noted that when the protective layer on the hydrogen terminal region is a metal, there is no need to remove the protective layer. After etching the surface of the oxide layer to form an n-type channel pattern, an n-type oxide semiconductor layer is formed; when the protective layer on the hydrogen terminal region is a dielectric material, an n-type channel pattern is etched on the surface of the oxide layer, and the protective layer is removed to form an n-type oxide semiconductor layer. In order to ensure that the protective layer can be removed, in some feasible embodiments of the present invention, I2 / KI solution, BOE (Buffered Oxide Etch) or hydrofluoric acid is used for cleaning to remove the protective layer.

[0034] In some feasible embodiments of the present invention, when depositing a protective layer on the hydrogen terminal area and when depositing an oxide layer on the surface of the mesa isolation area, deposition can be performed by any one of electron beam evaporation physical vapor deposition, magnetron sputtering, metal organic chemical vapor deposition, laser pulse deposition, atomic layer deposition and sol-gel.

[0035] In some preferred embodiments of the present invention, when electron beam evaporation physical vapor deposition is used to deposit the protective layer, the protective layer deposited on the hydrogen terminal region is achieved by the following steps:

[0036] 1) Spin-coating a layer of photoresist on the surface of the sample with hydrogen terminal area and mesa isolation area formed on the surface, then baking at 90℃~105℃ for 80s~100s, using a mask designed according to the device performance requirements to perform ultraviolet lithography exposure for 5s~6s, and developing for 60s~80s to expose the hydrogen terminal area to realize the pattern of the protective layer. The photoresist is AZ5214 photoresist or RN246 photoresist.

[0037] 2) Using EB-PVD deposition technology, a layer of corresponding protective layer material with a thickness of 130nm to 170nm is deposited to complete the lift-off process, and only the dielectric layer in the area not covered by the photoresist is retained to form a protective layer on the hydrogen terminal area.

[0038] In order to ensure that the formed oxide layer can be used as an n-type conductive channel, in some preferred embodiments of the present invention, the material of the deposited oxide layer can be selected according to actual needs, for example, it can be selected from any one or more of SnO2, ZnO, In2O3, ZrO2, ITO, AZO and IGZO.

[0039] In order to further ensure that the formed oxide layer can be used as an n-type conductive channel, in some preferred embodiments of the present invention, according to actual needs, after etching the surface of the oxide layer to form the required n-type channel pattern, annealing is performed to improve the crystallization quality of the oxide layer through annealing, thereby improving the carrier mobility performance of the n-type conductive channel, so that it forms an n-type oxide semiconductor layer to meet the use requirements as an n-type conductive channel material. In some preferred embodiments of the present invention, the gas atmosphere of the annealing treatment is one of oxygen and argon, the temperature is 300°C to 600°C, and the time is 1min to 60min.

[0040] The test results show that the carrier concentration of the n-type conductive channel of the n-type oxide semiconductor layer formed by the above method of the present invention is 1×10 15 cm -3 ~1×10 20 cm -3 , the mobility is 1cm 2 / V·s~500cm 2 / V·s.

[0041] A first source electrode and a first drain electrode are respectively deposited at both ends of the n-type oxide semiconductor layer so that the first drain electrode and the second drain electrode form ohmic contacts with the n-type oxide semiconductor layer; a second source electrode and a second drain electrode are respectively deposited at both ends of the hydrogen terminal region so that the second source electrode and the second drain electrode form ohmic contacts with the hydrogen terminal region serving as a p-type conductive channel.

[0042] It should be noted that the present invention preferably adopts a mask method, that is, according to actual needs, a mask plate matching the sizes of the actually required first source electrode, first drain electrode, second source electrode and second drain electrode is selected to form the required photoresist pattern, and then the corresponding first source electrode, first drain electrode, second source electrode and second drain electrode are deposited respectively.

[0043] In some feasible embodiments of the present invention, when depositing the first source electrode, the first drain electrode, the second source electrode and the second drain electrode, any one of electron beam evaporation, magnetron sputtering, metal organic chemical vapor deposition, laser pulse deposition, atomic layer deposition and sol-gel can be used for deposition. In some preferred embodiments of the present invention, electron beam evaporation technology is used for deposition.

[0044] It should also be noted that the first source electrode is grounded, and the second source electrode is connected to a power supply voltage, so as to construct a complete logic device structure to ensure that the CMOS inverter can work.

[0045] A first gate dielectric layer and a first gate electrode are sequentially deposited on the n-type oxide semiconductor layer, and a second gate dielectric layer and a second gate electrode are sequentially deposited on the hydrogen terminal region.

[0046] The first interconnection line and the second interconnection line are formed on the sample surface by using photolithography and deposition technology, so as to realize the metal interconnection between the first drain electrode and the second drain electrode through the first interconnection line, and realize the metal interconnection between the first gate electrode and the second gate electrode through the second interconnection line.

[0047] It should be noted that the present invention preferably adopts a mask method, that is, according to actual needs, a mask plate that matches the actual required sizes of the first gate dielectric layer and the first gate electrode, the second gate dielectric layer and the second gate electrode is selected to form the required photoresist pattern, and then the corresponding first gate dielectric layer and the first gate electrode, the second gate dielectric layer and the second gate electrode are deposited respectively.

[0048] In some feasible embodiments of the present invention, when depositing the first gate dielectric layer and the first gate electrode, the second gate dielectric layer and the second gate electrode, any one of electron beam evaporation, magnetron sputtering, metal organic chemical vapor deposition, laser pulse deposition, atomic layer deposition and sol-gel can be used for deposition. In some preferred embodiments of the present invention, electron beam evaporation physical vapor deposition technology is used for deposition.

[0049] In some feasible embodiments of the present invention, the photolithography described in the present invention is any one of ultraviolet photolithography, electron beam photolithography and step-and-step non-contact photolithography.

[0050] Compared with the prior art, the present invention has the following beneficial effects:

[0051] The diamond-based CMOS inverter of the present invention comprises: a diamond substrate, a single crystal diamond film, a hydrogen termination region, a mesa isolation region, an n-type oxide semiconductor layer, a first source electrode, a first drain electrode, a second source electrode, a second drain electrode, a first gate dielectric layer, a first gate electrode, a second gate dielectric layer and a second gate electrode; a single crystal diamond film is provided on the diamond substrate; a hydrogen termination region and a mesa isolation region are provided on the single crystal diamond film; an n-type oxide semiconductor layer is provided on the mesa isolation region; a first source electrode and a first drain electrode are provided at both ends of the n-type oxide semiconductor layer; a second source electrode and a second drain electrode are provided at both ends of the hydrogen termination region; a first gate dielectric layer is provided on the n-type oxide semiconductor layer; a second gate dielectric layer is provided on the hydrogen termination region; a first gate electrode is provided on the first gate dielectric layer; and a second gate electrode is provided on the second gate dielectric layer. The first drain electrode and the second drain electrode are metal interconnected as the output of the CMOS inverter; the first gate electrode and the second gate electrode are metal interconnected as the input of the CMOS inverter.

[0052] The present invention combines p-type hydrogen-terminated diamond and n-type oxide semiconductor together, effectively avoiding the technical difficulty that diamond is difficult to realize n-type MOS devices (Metal-Oxide-Semiconductor Field-Effect Transistor, Metal-Oxide-Semiconductor Field-Effect Transistor), giving full play to the respective advantages of diamond and n-type oxide semiconductor, and realizing a high-performance diamond-based monolithic integrated CMOS inverter. Among them, diamond carrier mobility is high, n-type oxide semiconductor has high conductive electron concentration, low resistivity, monolithic integration reduces device spacing, and ensures that the CMOS inverter has high switching speed, high gain and low loss; diamond has high thermal conductivity and strong radiation resistance, reduces the junction temperature of the device, and n-type oxide semiconductor has good thermal stability, thus ensuring that the CMOS inverter can be applied to high temperature and strong radiation environment applications, confirming that diamond has great potential in the application of integrated circuits, and has multiple functions in digital system design, computer processors and communication circuits, including logic gate implementation, clock signal driving, buffer amplifier, signal inversion control and digital signal processing, etc., promoting the development of digital circuit technology, and providing an efficient and reliable working basis for digital systems. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] Figure 1 FIG. 4 is a connection logic diagram of the diamond-based CMOS inverter of the present invention. Figure 1 In, M P It is a p-type enhancement mode device, M N It is an n-type enhancement mode device, V DD is the operating voltage, gnd is ground, V INis the input terminal and represents the connection between the first gate electrode and the second gate electrode, V OUT is an output terminal and indicates that the first drain electrode and the second drain electrode are connected.

[0054] Figure 2 A schematic flow chart of the method for preparing a diamond-based CMOS inverter of the present invention.

[0055] Figure 3 It is a schematic diagram of the cross-sectional structure of a diamond-based CMOS inverter of the present invention; Figure 3 In the figure, diamond substrate 1; single crystal diamond film 2; hydrogen termination region 3; mesa isolation region 4; n-type oxide semiconductor layer 5; first source electrode 6; first drain electrode 7; second source electrode 8; second drain electrode 9; first gate dielectric layer 10; first gate electrode 11; second gate dielectric layer 12; second gate electrode 13; first interconnection line 14; second interconnection line 15.

[0056] Figure 4 It is a top view of a diamond-based CMOS inverter of the present invention. DETAILED DESCRIPTION

[0057] The technical solutions in the embodiments of the present invention will be described clearly and completely below. It should be noted that in each of the following embodiments of the present invention, the standard cleaning process for diamond substrates in the art is used for cleaning, so the specific cleaning steps will not be repeated, and those skilled in the art should know. In each of the following embodiments of the present invention, the preparation process used to grow and form the diamond substrate is a conventional process in the art, as long as the diamond substrate 1 can be formed, so the present invention will not be repeated, and those skilled in the art should know. It should also be noted that, in order to facilitate concise expression, as shown in the Chinese-English comparison table of Table 1, in each of the following embodiments of the present invention, the following substances or preparation methods are replaced by their corresponding English abbreviations.

[0058] Table 1 Chinese-English comparison table

[0059]

[0060] The diamond-based CMOS inverter of the present invention comprises: a diamond substrate 1; a single crystal diamond film 2, which is arranged on the diamond substrate 1; a hydrogen termination region 3 is arranged on the single crystal diamond film 2, serving as a p-type conductive channel; a mesa isolation region 4 is arranged on the single crystal diamond film 2 and is located around the hydrogen termination region 3; an n-type oxide semiconductor layer 5 is arranged on the mesa isolation region 4, serving as an n-type conductive channel; a first gate dielectric layer 10 is arranged on the n-type oxide semiconductor layer 5; and a first gate electrode 11 is arranged on the first gate dielectric layer 10; a second gate dielectric layer 12 is arranged on the hydrogen termination region 3, and a second gate dielectric layer 12 is provided with a first gate electrode 11; two gate electrodes 13; wherein, the first source electrode 6 and the first drain electrode 7 are respectively provided at both ends of the n-type oxide semiconductor layer 5, and the first gate dielectric layer 10 and the first gate electrode 11 are both located between the first source electrode 6 and the first drain electrode 7; the second source electrode 8 and the second drain electrode 9 are respectively provided at both ends of the hydrogen terminal region 3, and the second gate dielectric layer 12 and the second gate electrode 13 are both located between the second source electrode 8 and the second drain electrode 9; the first drain electrode 7 and the second drain electrode 9 are metal interconnected as the output of the CMOS inverter; the first gate electrode 11 and the second gate electrode 13 are metal interconnected as the input of the CMOS inverter. The present invention effectively circumvents the current technical difficulties of diamond in realizing n-type MOS devices by combining p-type hydrogen-terminated diamond (i.e., hydrogen terminal region 3) and n-type oxide semiconductor (i.e., n-type oxide semiconductor layer 5), gives full play to the respective advantages of diamond and n-type oxide semiconductor, and realizes a high-performance diamond-based monolithic integrated CMOS inverter.

[0061] Furthermore, a portion of the first source electrode 6 and the first drain electrode 7 are both located on the mesa isolation region 4, and the other portions are both located on the n-type oxide semiconductor layer 5, for forming an ohmic contact; a portion of the second source electrode 8 and the second drain electrode 9 are both located on the mesa isolation region 4, and the other portions are both located on the hydrogen terminal region 3, for forming an ohmic contact; the second source electrode 8 and the second drain electrode 9 are both not in contact with the second gate dielectric layer 12 and the second gate electrode 13; the first gate dielectric layer 10 and the first gate electrode 11 are both located on the first source electrode 6 and the first drain electrode 7 without contact.

[0062] The present invention also provides a method for preparing a diamond-based CMOS inverter, including the following embodiments.

[0063] Example 1

[0064] See also Figure 2 This embodiment provides a diamond-based CMOS inverter, which is manufactured by the following steps:

[0065] Step 1, providing a diamond substrate 1 as a base:

[0066] 1.1) A diamond substrate 1 is grown using CVD technology.

[0067] 1.2) After cleaning the diamond substrate 1 grown by CVD technology, it is blown dry with nitrogen to obtain a clean diamond substrate 1, which is used as a base for standby use.

[0068] Step 2, epitaxially growing a single crystal diamond layer on the surface of the diamond substrate 1 to form a single crystal diamond film 2 on the surface of the diamond substrate 1:

[0069] By using the MPCVD technology, under the conditions of a plasma power of 1.2 kW, a chamber pressure of 100 Torr, and a total gas flow rate of 500 sccm, a single crystal diamond film 2 with a thickness of 2 μm is deposited on the cleaned diamond substrate 1 .

[0070] According to the test, the single crystal diamond film 2 obtained in this embodiment has a resistivity of 120 MΩ·cm, a root mean square surface roughness of 0.4 nm, and a Raman curve half peak width of 1.9 cm. -1 , the half-peak width of the XRD rocking curve is 28 arcsec.

[0071] Step 3, performing hydrogenation treatment on the single crystal diamond film 2 to form a two-dimensional hole gas conductive layer on the surface of the single crystal diamond film 2:

[0072] The MPCVD technology is used to hydrogenate the single crystal diamond film 2 for 20 minutes at a chamber temperature of 700° C. and a hydrogen flow rate of 100 sccm to form a two-dimensional hole gas conductive layer on the surface of the single crystal diamond film 2 .

[0073] Step 4, using photolithography and etching technology to etch part of the two-dimensional hole gas conductive layer, the unetched area still retains the characteristics of the two-dimensional hole gas conductive layer to form a hydrogen terminal area 3, and the etched area forms a mesa isolation area 4:

[0074] 4.1) The sample obtained in step 3 was ultrasonically cleaned with acetone, isopropanol and deionized water, and then dried for later use.

[0075] 4.2) A layer of AZ5214 photoresist was spin-coated on the surface of the sample obtained in 4.1) above, and then baked at 90°C for 90 seconds to remove the photoresist solvent; then, UV lithography was performed using a mask designed according to the device performance requirements for 5 seconds, developed for 60 seconds, and the exposed photoresist was removed, leaving the mask area pattern.

[0076] 4.3) RIE etching is performed under RIE etching process conditions with a plasma power of 100 W and a rate of 500 nm / min to etch the area where the two-dimensional hole gas conductive layer is not covered by the photoresist to form a mesa isolation area 4. Finally, acetone is used to remove the photoresist on the surface of the sample to expose the unetched area that still retains the characteristics of the two-dimensional hole gas conductive layer to form a hydrogen terminal area 3.

[0077] And after testing, the two-dimensional hole gas surface density of the hydrogen terminal region 3 obtained in this embodiment is 1×10 13 cm -2 , the mobility is 180cm 2 / V·s.

[0078] Step 5, after depositing a protective layer on the hydrogen terminal region 3 using a deposition technique, an oxide layer is deposited on the surface of the sample on which the protective layer is deposited:

[0079] 5.1) Spin-coat a layer of AZ5214 photoresist on the surface of the sample obtained in 4.3) above, then bake at 90°C for 90 seconds, perform UV lithography exposure for 5 seconds using a mask designed according to the device performance requirements, develop for 60 seconds, and remove the exposed photoresist to expose the hydrogen terminal area 3 to achieve the pattern of the protective layer.

[0080] 5.2) Using EB-PVD deposition technology, the background vacuum is 5×10 -4 Under the condition of Pa, the electron beam current is set to 30 mA, and a SiO2 layer with a thickness of 150 nm is deposited to complete the lift-off process, leaving only the dielectric layer in the area not covered by the photoresist to form a protective layer on the hydrogen terminal area 3.

[0081] 5.3) Using radio frequency magnetron sputtering technology, a layer of In2O3 with a thickness of 220nm is deposited on the surface of the sample. In this embodiment, the sputtering conditions of radio frequency magnetron sputtering are: temperature of 300°C, sputtering power of 300W, deposition time of 10min, working pressure of 0.6Pa, and a target material prepared by mixing In2O3, SnO2 and WO3 in a mass ratio of 90:9:1 as the In2O3 target material to adjust the performance of the n-type oxide, and the background is vacuumed to 10 -4 Pa, and the argon flow rate was 40 mL / min.

[0082] Step 6, etching the surface of the oxide layer to form an n-type channel pattern, and removing the protective layer on the hydrogen terminal region, that is, forming an n-type oxide semiconductor layer 5: and in this embodiment, the carrier concentration in the n-type conductive channel region of the obtained In2O3 layer is 10 18 cm -3 , the mobility is 27.3cm 2 / V·s.

[0083] 6.1) After the sputtering, the sample is naturally cooled to room temperature, and then a layer of AZ5214 photoresist is spin-coated on the surface of the obtained sample. The single crystal diamond sample with the photoresist spin-coated is baked at 90°C for 90s. According to the device performance requirements, a designed mask is used for UV lithography exposure for 5s, developed for 60s, and the exposed photoresist is removed, leaving the mask area pattern.

[0084] 6.2) Using EB-PVD technology, 150nm SiO2 was deposited, and the background vacuum was 5×10 -4 Pa, complete the lift-off process in acetone solution to obtain SiO2 mask pattern. Then put the sample into the etcher for etching to remove the In2O3 in the non-n-type conductive channel area and only keep the In2O3 in the n-type conductive channel area, that is, obtain the n-type oxide semiconductor layer 5.

[0085] 6.3) The sample obtained in 6.2) above is immersed in BOE solution to remove the SiO2 layer formed in 6.2) and step 5. Since the hydrogen terminal area is conductive and SiO2 is non-conductive, if the sample in this area is conductive again, it means that SiO2 is completely removed. In the actual process, it is found that a 150nm SiO2 layer can be completely etched after being immersed in BOE solution for 3 minutes.

[0086] Step 7, depositing a first source electrode 6 and a first drain electrode 7 at both ends of the n-type oxide semiconductor layer 5, and depositing a second source electrode 8 and a second drain electrode 9 at both ends of the hydrogen terminal region 3:

[0087] 7.1) Spin-coat a layer of AZ5214 photoresist on the surface of the sample obtained in 6.3) above, bake the single crystal diamond sample with the photoresist spin-coated at 90°C for 90 seconds, perform UV lithography exposure for 5 seconds using a designed mask according to the device performance requirements, develop for 60 seconds, remove the exposed photoresist, and expose the source and drain electrode areas.

[0088] 7.2) Using electron beam evaporation technology, the background vacuum is 5×10 -4 Under the condition of 100 Pa, Au with a thickness of 150 nm is deposited at both ends of the n-type oxide semiconductor layer 5 to serve as the first source electrode 6 and the first drain electrode 7, respectively. At the same time, Au with a thickness of 150 nm is deposited at both ends of the hydrogen terminal region 3 to serve as the second source electrode 8 and the second drain electrode 9, respectively.

[0089] 7.3) Take out the sample deposited in 7.2) above, immerse it in acetone solution for 5 minutes to complete the lift-off process to strip off the AZ5214 photoresist coated in 7.1) above, and obtain the first source electrode 6 and the first drain electrode 7, the second source electrode 8 and the second drain electrode 9.

[0090] Step 8, a first gate dielectric layer 10 and a first gate electrode 11 are sequentially deposited on the n-type oxide semiconductor layer 5, and a second gate dielectric layer 12 and a second gate electrode 13 are sequentially deposited on the hydrogen terminal region 3:

[0091] 8.1) Spin-coat a layer of AZ5214 photoresist on the surface of the sample obtained in 7.3) above, bake the single crystal diamond sample with the photoresist spin-coated at 90°C for 90 seconds, perform UV lithography exposure for 5 seconds using a designed mask according to the device performance requirements, develop for 60 seconds, remove the exposed photoresist, and obtain the gate dielectric layer pattern.

[0092] 8.2) Using EB-PVD technology, the background vacuum is 3.7×10 -5 Pa, under the condition that the current intensity is 20 mA, a 50 nm thick Al2O3 layer is first deposited on the n-type oxide semiconductor layer 5 as the first gate dielectric layer 10, and then an Al layer is continuously deposited on the formed Al2O3 layer to obtain a first gate electrode 11. At the same time, a 50 nm thick Al2O3 layer is first deposited on the hydrogen terminal region 3 as the second gate dielectric layer 12, and then an Al layer is continuously deposited on the formed Al2O3 layer to obtain a second gate electrode 13.

[0093] 8.3) Take out the sample deposited in step 8.2) above, and immerse it in an acetone solution for 5 minutes to strip off the AZ5214 photoresist coated in step 1) above, and obtain a first gate dielectric layer 10, a first gate electrode 11, a second gate dielectric layer 12 and a second gate electrode 13.

[0094] Step 9, metal interconnecting the first drain electrode 7 and the second drain electrode 9, and metal interconnecting the first gate electrode 11 and the second gate electrode 13 to form a logic device:

[0095] A layer of AZ5214 photoresist was spin-coated on the surface of the sample obtained in 8.3) above, and the single crystal diamond sample with the photoresist was baked at 90°C for 90s. According to the device performance requirements, a designed mask was used for UV exposure for 5s, and developed for 60s. The exposed photoresist was removed to obtain the interconnect metal pattern. Electron beam evaporation technology was used, and the background vacuum was 5×10 -4Under the condition of Pa, Al metal interconnection lines are deposited, the first drain electrode 7 and the second drain electrode 9 are interconnected through the first interconnection line 14, and the first gate electrode 11 and the second gate electrode 13 are interconnected through the second interconnection line 15, so as to obtain a diamond-based CMOS inverter.

[0096] The overall structure of the diamond-based CMOS inverter formed in this embodiment is as follows: Figure 3 and Figure 4 shown.

[0097] Example 2

[0098] This embodiment provides a diamond-based CMOS inverter, which is manufactured by the following steps:

[0099] Step 1, providing a diamond substrate 1 as a base:

[0100] 1.1) A diamond substrate 1 is grown using HPHT technology.

[0101] 1.2) After cleaning the diamond substrate 1 grown by HPHT technology, it is blown dry with nitrogen to obtain a clean diamond substrate 1, which is used as a base for standby use.

[0102] Step 2, epitaxially growing a single crystal diamond layer on the surface of the diamond substrate 1 to form a single crystal diamond film 2 on the surface of the diamond substrate 1:

[0103] The single crystal diamond layer 2 was deposited on the cleaned diamond substrate using MPCVD technology. The plasma power was 1 kW, the chamber pressure was 100 Torr, and the total gas flow rate was 500 sccm. The obtained single crystal diamond film had a thickness of 1 μm, a resistivity of 100 MΩ·cm, a root mean square surface roughness of 0.5 nm, and a Raman curve half peak width of 2 cm. -1 , the half-peak width of the XRD rocking curve is 30 arcsec.

[0104] Step 3, performing hydrogenation treatment on the single crystal diamond film 2 to form a two-dimensional hole gas conductive layer on the surface of the single crystal diamond film 2:

[0105] The microwave plasma power was controlled so that the chamber temperature was 700°C and the hydrogen flow rate was maintained at 150 sccm. The grown single crystal diamond film 2 was hydrogenated for 5 min to form a two-dimensional hole gas conductive layer on the surface of the single crystal diamond film 2. The surface density of the obtained two-dimensional hole gas conductive layer was 2×10 13 cm -2 , the mobility is 150cm 2 / V·s.

[0106] Step 4, using photolithography and etching technology to etch part of the two-dimensional hole gas conductive layer, the unetched area still retains the characteristics of the two-dimensional hole gas conductive layer to form a hydrogen terminal area 3, and the etched area forms a mesa isolation area 4:

[0107] 4.1) Use acetone, isopropanol, and deionized water to ultrasonically clean the sample and blow dry it for later use.

[0108] 4.2) Spin-coat a layer of RN246 photoresist on the surface of the sample obtained in 4.1) above, and bake the single crystal diamond sample with the photoresist spun on at 100°C for 90s to remove the photoresist solvent; use the designed mask to perform UV lithography exposure for 5.5s, post-bake at 103°C for 100s, develop for 80s, remove the unexposed photoresist, and leave the mask area pattern.

[0109] 4.3) ICP etching is performed under RIE etching process conditions with a plasma power of 100 W and a rate of 500 nm / min to form a mesa isolation region 4. Finally, acetone is used to remove the photoresist on the surface of the sample to expose an unetched area that still retains the characteristics of the two-dimensional hole gas conductive layer to form a hydrogen terminal region 3.

[0110] Step 5, after depositing a protective layer on the hydrogen terminal region 3 using a deposition technique, an oxide layer is deposited on the surface of the sample on which the protective layer is deposited:

[0111] 5.1) A layer of RN246 photoresist is spin-coated on the surface of the sample obtained in 4.3) above, and the single crystal diamond sample with the photoresist spin-coated is baked at 100°C for 90s, exposed to UV light for 5.5s using a designed mask, post-baked at 103°C for 100s, developed for 80s, and the unexposed photoresist is removed to expose the hydrogen terminal area 3 to realize the pattern of the protective layer.

[0112] 5.2) Using EB-PVD deposition technology, the background vacuum is 5×10 -4 Under the condition of Pa, the electron beam current is set to 20 mA, and a layer of Au with a thickness of 150 nm is deposited to complete the lift-off process, leaving only the Au layer in the area not covered by the photoresist to form a protective layer on the hydrogen terminal area 3.

[0113] 5.3) Using atomic layer deposition technology, a layer of n-type Al-doped ZnO semiconductor layer with a thickness of 80 nm is deposited on the surface of the sample. In this embodiment, the aluminum doping source is trimethylaluminum, the zinc source precursor is dimethylzinc, the oxygen source precursor is water, the deposition temperature is 200°C, the chamber pressure is 0.2 Torr, and the Al doping content is 2.17%.

[0114] Step 6, etching the surface of the oxide layer to form an n-type channel pattern, that is, forming an n-type oxide semiconductor layer 5:

[0115] 6.1) After deposition, the sample was naturally cooled to room temperature, and then a layer of RN246 photoresist was spin-coated on the surface of the obtained sample. The single crystal diamond sample with the photoresist was baked at 100°C for 90s, and the designed mask was used for UV lithography exposure for 5.5s, and then post-baked at 103°C for 100s, developed for 80s, and the unexposed photoresist was removed, leaving the mask area pattern; 100nm SiO2 was deposited using EB-PVD, and the background vacuum was 5×10 -4 Pa, after peeling, the SiO2 mask pattern is obtained. Then the sample is placed in an etcher for etching to remove the ZnO in the non-n-type conductive channel area and only retain the ZnO in the n-type conductive channel area.

[0116] 6.2) Immerse the sample in BOE solution for 7 minutes to remove the SiO2 mask formed in 6.1) above.

[0117] 6.3) The annealed sample was placed in a rapid annealing furnace for annealing at 400°C for 60 seconds. The carrier concentration in the n-type conductive channel region of the obtained ZnO film was 4×10 18 cm -3 , the mobility is 17.4cm 2 / V·s.

[0118] Step 7, depositing a second source electrode, a second drain electrode, a second gate dielectric layer and a second gate electrode respectively:

[0119] 7.1) Spin-coat a layer of RN246 photoresist on the surface of the sample obtained in 6.3), bake the single crystal diamond sample with the photoresist spin-coated at 100°C for 90 seconds, use a mask to perform UV photolithography exposure for 5.5 seconds, post-bake at 103°C for 100 seconds, develop for 80 seconds, remove the unexposed photoresist, and leave the mask area pattern; use KI / I2 aqueous solution to corrode the Au layer at the dielectric layer position of the p-type device to obtain a second source electrode 8 and a second drain electrode 9.

[0120] 7.2) Using the mask in 7.1) above, 50 / 100 nm ZrO2 / Al was deposited on the gate dielectric layer of the p-type device by electron beam evaporation, with a background vacuum of 5×10 -4 The deposited diamond sample was taken out, immersed in an acetone solution for 5 minutes, and then peeled off to obtain the designed second gate dielectric layer 12 and the second gate electrode 13 .

[0121] Step 8, depositing a first source electrode, a first drain electrode, a first gate dielectric layer and a first gate electrode:

[0122] 8.1) Spin-coat a layer of RN246 photoresist on the surface of the sample in 7.2) above, bake the single crystal diamond sample with the photoresist at 100°C for 90s, perform UV exposure for 5.5s using the designed mask, post-bake at 103°C for 100s, develop for 80s, obtain the source and drain electrode pattern, and use electron beam evaporation to deposit 150nm of Au, with a background vacuum of 5×10 -4 The deposited diamond sample was taken out, immersed in an acetone solution for 5 minutes, and peeled off to obtain a first source electrode 6 and a first drain electrode 7 .

[0123] 8.2) Spin-coat a layer of RN246 photoresist on the sample surface, bake the single crystal diamond sample with the photoresist at 100°C for 90 seconds, use the designed mask to perform UV exposure for 5.5 seconds, post-bake at 103°C for 100 seconds, develop for 80 seconds, obtain the gate electrode pattern, and use electron beam evaporation to deposit 50 / 100nm MoO3 / Mo, with a background vacuum of 5×10 - 4 The deposited diamond sample was taken out, immersed in an acetone solution for 5 minutes, and peeled off to obtain the first gate dielectric layer 10 and the first gate electrode 11 .

[0124] Step 9, metal interconnecting the first drain electrode 7 and the second drain electrode 9, and metal interconnecting the first gate electrode 11 and the second gate electrode 13 to form a logic device:

[0125] Al metal interconnection lines are deposited, and the first drain electrode 7 and the second drain electrode 9 are interconnected through the first interconnection line 14, and the first gate electrode 11 and the second gate electrode 13 are interconnected through the second interconnection line 15, so as to obtain a diamond-based CMOS inverter.

[0126] The diamond-based CMOS inverter of the present invention is prepared by combining p-type hydrogen-terminated diamond (i.e., hydrogen-terminated region 3) and n-type oxide semiconductor together, thereby effectively avoiding the technical difficulty that it is difficult to realize n-type MOS devices with diamond at present, giving full play to the respective advantages of diamond and n-type oxide semiconductor, and realizing a high-performance diamond-based monolithic integrated CMOS inverter; diamond has high carrier mobility, n-type oxide semiconductor has high conductive electron concentration, low resistivity, and monolithic integration reduces device spacing, ensuring that the CMOS inverter has high switching speed, high gain and low loss; diamond has high thermal conductivity and strong radiation resistance, which reduces the junction temperature of the device, and n-type oxide semiconductor has good thermal stability, thereby ensuring that the CMOS inverter can be applied to high-temperature and strong radiation environment applications, proving that diamond has great potential in the application of integrated circuits.

[0127] Obviously, the above embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

Claims

1. A diamond-based CMOS inverter, characterized in that: include: Diamond substrate (1); A single crystal diamond film (2) is disposed on the diamond substrate (1); A hydrogen terminal region (3) is disposed on the single crystal diamond film (2) and serves as a p-type conductive channel; A mesa isolation region (4) is disposed on the single crystal diamond film (2) and is located around the hydrogen terminal region (3); An n-type oxide semiconductor layer (5) is disposed on the mesa isolation region (4) and serves as an n-type conductive channel; A first gate dielectric layer (10) is disposed on the n-type oxide semiconductor layer (5); and a first gate electrode (11) is disposed on the first gate dielectric layer (10); A second gate dielectric layer (12) is disposed on the hydrogen terminal region (3); and a second gate electrode (13) is disposed on the second gate dielectric layer (12); The first source electrode (6) and the first drain electrode (7) are respectively disposed at two ends of the n-type oxide semiconductor layer (5), and the first gate dielectric layer (10) and the first gate electrode (11) are both located between the first source electrode (6) and the first drain electrode (7); the second source electrode (8) and the second drain electrode (9) are respectively disposed at two ends of the hydrogen terminal region (3), and the second gate dielectric layer (12) and the second gate electrode (13) are both located between the second source electrode (8) and the second drain electrode (9); the first drain electrode (7) and the second drain electrode (9) are metal interconnected to serve as the output of a CMOS inverter; and the first gate electrode (11) and the second gate electrode (13) are metal interconnected to serve as the input of the CMOS inverter.

2. The diamond-based CMOS inverter according to claim 1, characterized in that: The single crystal diamond film (2) is obtained by epitaxy on the diamond substrate (1) using a chemical vapor deposition method; the hydrogen terminal region (3) is formed by hydrogenating the surface of the single crystal diamond film (2).

3. The diamond-based CMOS inverter according to claim 1, characterized in that: The surface carrier concentration in the p-type conductive channel of the hydrogen terminal region (3) is 1×10 12 cm -2 ~5×10 14 cm -2 , the mobility is 20cm 2 / V·s~2500cm 2 / V·s, the thickness of the hydrogen terminal region (3) is 1 nm to 20 nm.

4. The diamond-based CMOS inverter according to claim 1, characterized in that: The mesa isolation region (4) is oxygen-terminated diamond.

5. The diamond-based CMOS inverter according to claim 1, characterized in that: The material of the n-type oxide semiconductor layer (5) is any one or more of tin dioxide, zinc oxide, indium oxide, zirconium dioxide, indium tin oxide, aluminum zinc oxide and indium gallium zinc oxide.

6. The diamond-based CMOS inverter according to claim 1, characterized in that: The materials of the first source electrode (6), the first drain electrode (7), the second source electrode (8) and the second drain electrode (9) are all selected from any one or more of Au, Pd, Ir, Pt and Ti.

7. The diamond-based CMOS inverter according to claim 1, characterized in that: The materials of the first gate dielectric layer (10) and the second gate dielectric layer (12) are both selected from Al2O3, SiO2, SiN x , any one or more of HfO2 and MoO3.

8. The diamond-based CMOS inverter according to claim 1, characterized in that: The materials of the first gate electrode (11) and the second gate electrode (13) are selected from any one or more of Al, Zr, Hf and Mo.

9. A method for preparing a diamond-based CMOS inverter according to any one of claims 1 to 8, characterized in that: The following steps are involved: Providing a diamond substrate (1) as a base; epitaxially growing a single crystal diamond layer on the surface of the diamond substrate (1) to form a single crystal diamond thin film (2) on the surface of the diamond substrate (1); Performing a hydrogenation treatment on the single crystal diamond film (2) to form a two-dimensional hole gas conductive layer on the surface of the single crystal diamond film (2); Using photolithography and etching technology, a partial area of ​​the two-dimensional hole gas conductive layer is etched, the unetched area still retains the characteristics of the two-dimensional hole gas conductive layer to form a hydrogen terminal area (3), and the etched area forms a mesa isolation area (4); After depositing a protective layer on the hydrogen terminal region (3) by using a deposition technique, an oxide layer is deposited on the surface of the sample on which the protective layer is deposited, thereby forming an n-type oxide semiconductor layer (5); A first source electrode (6) and a first drain electrode (7) are respectively formed at two ends of the n-type oxide semiconductor layer (5), and a second source electrode (8) and a second drain electrode (9) are respectively deposited at two ends of the hydrogen terminal region (3); A first gate dielectric layer (10) and a first gate electrode (11) are sequentially deposited on the n-type oxide semiconductor layer (5), and a second gate dielectric layer (12) and a second gate electrode (13) are sequentially deposited on the hydrogen terminal region (3); The first drain electrode (7) and the second drain electrode (9) are metal interconnected, and the first gate electrode (11) and the second gate electrode (13) are metal interconnected to form a logic device.

10. The preparation method according to claim 9, wherein the hydrogenation treatment is carried out in a hydrogen plasma or a hydrogen atmosphere; The hydrogen flow rate in the hydrogen plasma or hydrogen atmosphere is 50 sccm to 1000 sccm; The reaction temperature of the hydrogenation treatment is 500°C to 900°C.

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