Laser battery array chip and manufacturing method and application thereof

Abstract

The invention belongs to the field of laser wireless energy transmission. The invention provides a laser battery array chip and a manufacturing method and application thereof, the chip comprises a battery array formed by serially connected sub-batteries, each sub-battery comprises an electrode extension part and an electrode connection part which extend from a metal electrode layer, and the electrode extension parts and the electrode connection parts are electrically connected with buffer layers of adjacent sub-batteries, so that serial connection is realized; the sub-cell further comprises a first insulating passivation layer for isolating the metal electrode from the energy conversion layer and isolating the adjacent sub-cell. The design greatly improves the laser energy output efficiency and conversion efficiency per unit area. The laser energy conversion battery array chip designed by adopting a chip process has extremely high output energy density and smaller volume and weight, so that the laser energy conversion battery array chip is more suitable for being applied to the fields of wireless charging of unmanned aerial vehicles in the future and the like.

Description

Technical Field

[0001] The present invention belongs to the field of laser technology and relates to a device for laser wireless energy transmission, and in particular to a laser battery array chip and a manufacturing method and application thereof. Background Art

[0002] With the continuous expansion of the application scenarios of aerospace unmanned aerial vehicles and the rapid development of the aerospace industry, higher requirements are placed on the endurance and payload of aerospace unmanned aerial vehicles. At present, micro-aerospace unmanned aerial vehicles generally use onboard batteries for endurance. Because the energy density and power density of batteries are low, the payload, flight altitude and endurance of the aircraft are very limited. In order to enable micro-unmanned aerial vehicles to have long flight time, large payload and high-altitude flight, the use of remote wireless energy transmission to charge them is considered to be the most feasible solution in the future.

[0003] Lasers have the advantages of high power density, long transmission distance, strong resistance to electromagnetic interference, and good directionality, and are considered to be the most promising carrier for wireless energy transmission. In addition, high-energy laser wireless energy transmission technology is not only expected to provide wireless power transmission for aerospace equipment (such as aerospace drones, in-orbit satellites, deep space probes, lunar base stations, space elevators, etc.), but also can provide effective solutions to major engineering problems such as power supply in extremely harsh scenarios such as deep sea, fire, explosion, ultra-high voltage and strong magnetism.

[0004] The key to achieving high energy density laser wireless energy transmission is efficient laser energy conversion materials and devices. As a highly localized light source and heat source, laser can not only convert light into electrical energy through the photoelectric conversion effect when interacting with materials, but the deposited energy can also cause the temperature of the material to rise. Therefore, the current laser wireless energy transmission can be carried out in two main ways: thermoelectric energy conversion and photoelectric energy conversion.

[0005] Among them, thermoelectric energy conversion mainly converts laser irradiation photothermal energy directly into electrical energy through thermoelectric conversion materials. However, laser thermoelectric conversion is limited by the low conversion efficiency of thermoelectric materials, poor high temperature resistance, poor resistance to high-energy laser irradiation, and the limited temperature difference provided by the device, resulting in low conversion efficiency of this method, especially it cannot be used for high-energy and high-power laser wireless energy transmission applications. Compared with laser thermoelectric conversion, directly converting laser irradiation into electrical energy through photoelectric energy conversion materials has higher conversion efficiency, but its energy conversion density per unit area is lower. The main reason is that its laser photoelectric energy receiving conversion unit usually adopts an external physical series design, which leads to low laser energy conversion efficiency per unit area. At the same time, especially because it is subjected to a large light receiving area, it is easy for the structure to be greatly affected by the uneven distribution of laser beam energy.

[0006] Therefore, there is still a need to develop and research solutions based on laser photoelectric energy reception and conversion. Summary of the invention

[0007] In view of the problems existing in the prior art, the purpose of the present invention is to provide a laser battery array chip and its manufacturing method and application. The laser battery array chip adopts integrated circuit process design, and integrates multiple laser photoelectric conversion devices (sub-batteries) through a semi-insulating substrate and a buffer layer. The lateral series connection between the sub-batteries is realized through the semi-insulating substrate at the bottom of the chip and the metal electrodes on the chip. This design greatly improves the laser energy conversion efficiency per unit area. The laser energy conversion battery array chip designed by chip process has extremely high output energy density, smaller volume and weight, and is therefore more suitable for applications in the future fields of wireless charging of drones.

[0008] To achieve this object, the present invention adopts the following technical solutions:

[0009] In a first aspect, the present invention provides a laser battery array chip, comprising a semi-insulating substrate and a battery array arranged on its surface; the battery array comprises sub-batteries connected in series end to end; the sub-batteries comprise a buffer layer, an energy conversion layer and a metal electrode layer stacked in sequence;

[0010] The sub-cell further includes a first insulating passivation layer, wherein the first insulating passivation layer has a side surface covering the energy conversion layer and the buffer layer in a thickness direction, and the first insulating passivation layer isolates adjacent sub-cells;

[0011] The sub-cell further includes an electrode extension portion connected to the metal electrode layer and covering the first insulating passivation layer, and an electrode connection portion connected to the electrode extension portion and in contact with and electrically connected to a buffer layer of an adjacent sub-cell.

[0012] Different from the external series connection methods such as lead series connection commonly used in existing laser batteries, the present invention adopts integrated circuit process design and manufacturing, and connects the energy conversion battery devices (sub-batteries) in series horizontally in the chip through a semi-insulating substrate and a buffer layer, thereby forming a chip with a battery array arrangement, which is convenient for increasing the number of sub-batteries and enlarging the overall size of the chip, and is very suitable for energy transmission and conversion applications of large-size and large-spot laser light sources. This structural design can provide extremely high energy conversion per unit area. At the same time, the present invention sets a first insulating passivation layer to passivate the side of the energy conversion layer and the buffer layer, so that the metal electrode layer of the sub-battery can extend to the buffer layer of the adjacent sub-battery on the first insulating passivation layer (i.e., the electrode extension part), so that the buffer layer of the adjacent sub-battery can be isolated and insulated from the electrode extension part extending from the metal electrode layer as a part of the electrode connection, effectively solving the battery leakage problem and enhancing the electrical insulation effect of the entire chip, and can also form effective contact and electrical connection through the electrode connection part extending from the electrode extension part, completing the series connection of the sub-batteries. The laser battery array chip obtained by the present invention has a small volume and a light weight, and is more suitable for realizing laser wireless energy transmission in mobile devices and small mobile devices.

[0013] The following are preferred technical solutions of the present invention, but are not intended to be limitations of the technical solutions provided by the present invention. Through the following technical solutions, the technical objectives and beneficial effects of the present invention can be better achieved and realized.

[0014] As a preferred technical solution of the present invention, the sub-battery includes a GaAs battery.

[0015] Preferably, the energy conversion layer includes a back field layer, a base layer, an emission layer and a window layer which are arranged in sequence from bottom to top.

[0016] Preferably, the energy conversion layer comprises at least one of GaAs, GaInAs, GaAlAs, GaAlInAs, GaInP or AlInP.

[0017] Preferably, the back field layer comprises GaInP, the base layer comprises p-GaInAs, the emission layer comprises GaInAs, and the window layer comprises AlInP.

[0018] Preferably, the In doping concentration of the back field layer is less than 30% (referring to the molar doping concentration), for example, it can be 28%, 25%, 22%, 20%, 18%, 15%, 12%, 10%, 8%, 5%, 3% or 1%, etc., and the thickness of the back field layer is 50~100nm, for example, 50nm, 60nm, 70nm, 80nm, 90nm or 100nm, etc.

[0019] Preferably, the In doping concentration of the base layer is less than 30%, for example, it can be 28%, 25%, 22%, 20%, 18%, 15%, 12%, 10%, 8%, 5%, 3% or 1%, and the thickness of the base layer is 3~4μm, for example, 3μm, 3.1μm, 3.2μm, 3.3μm, 3.4μm, 3.5μm, 3.6μm, 3.7μm, 3.8μm, 3.9μm or 4μm, etc.

[0020] Preferably, the In doping concentration of the emission layer is less than 30%, for example, it can be 28%, 25%, 22%, 20%, 18%, 15%, 12%, 10%, 8%, 5%, 3% or 1%, and the thickness of the emission layer is 150~200nm, for example, 150nm, 160nm, 170nm, 180nm, 190nm or 200nm, etc.

[0021] Preferably, the In doping concentration of the window layer is less than 30%, for example, it can be 28%, 25%, 22%, 20%, 18%, 15%, 12%, 10%, 8%, 5%, 3% or 1%, and the thickness of the window layer is 400~500nm, for example, 400nm, 410nm, 420nm, 430nm, 440nm, 450nm, 460nm, 470nm, 480nm, 490nm or 500nm, etc.

[0022] Preferably, the semi-insulating substrate comprises GaAs.

[0023] Preferably, the buffer layer comprises n-GaAs, and the thickness of the buffer layer is 0.5-0.8 μm, for example, 0.5 μm, 0.55 μm, 0.6 μm, 0.65 μm, 0.7 μm, 0.75 μm or 0.8 μm.

[0024] Preferably, the metal electrode layer, the electrode extension portion and the electrode connection portion include at least one of Ag, Au, Ti or Pt.

[0025] As a preferred technical solution of the present invention, the sub-battery also includes an ultra-thin heavily doped tunnel layer, which is arranged between the stacked buffer layer and the energy conversion layer, and one side of the ultra-thin heavily doped tunnel layer in the thickness direction is covered by the first insulating passivation layer.

[0026] In the present invention, an ultra-thin heavily doped tunnel layer is added to the battery structure. The introduction of this layer can increase the longitudinal electrical contact of the battery to achieve high tunneling current density and low tunneling voltage drop, which is more conducive to the series connection of multiple batteries. The design of this large tunnel current density tunnel junction can be further adjusted to a specific thickness, a specific band gap, a specific degree of heavy doping, etc. to further prepare a large tunnel current density tunnel junction with low series resistance and high performance. The ultra-thin design of the heavily doped tunnel layer is mainly to achieve high transmittance, high tunneling current density, and low tunneling voltage drop, and ultimately achieve low series resistance and high performance output of the battery chip. Therefore, too thick a thickness will not achieve the effect of electrical contact, and it also needs to be adjusted according to the lattice parameters of the buffer layer to achieve the optimal lattice matching.

[0027] The doping elements of the ultra-thin heavily doped tunnel layer should be selected from doping elements with small diffusion coefficient, small memory effect, small delay effect and high doping concentration, so as to reduce the influence of N++ / P++ mutual diffusion on performance, reduce the influence of memory effect on subsequent epitaxial layer growth, and reduce the influence of delay effect on doping continuity; suitable growth conditions should be adopted during its preparation, so as to obtain highly doped materials with good crystal quality, and further optimize the thickness and doping degree of N++ / P++ during the epitaxial growth process.

[0028] Preferably, the ultra-thin heavily-doped tunnel layer comprises GaAs and / or AlGaAs.

[0029] Preferably, the total thickness of the ultra-thin heavily-doped tunnel layer is 10-20 nm, for example, 10 nm, 11 nm, 12 nm, 13 nm, 14 nm, 15 nm, 16 nm, 17 nm, 18 nm, 19 nm or 20 nm.

[0030] As a preferred technical solution of the present invention, the sub-battery further includes a contact layer, which is arranged between the stacked energy conversion layer and the metal electrode layer, and one side of the contact layer in the thickness direction is covered by the first insulating passivation layer.

[0031] Preferably, the contact layer comprises n-GaAs.

[0032] Preferably, the maximum thickness of the contact layer is 500-600 nm, for example, 500 nm, 510 nm, 520 nm, 530 nm, 540 nm, 550 nm, 560 nm, 570 nm, 580 nm, 590 nm or 600 nm.

[0033] In the present invention, the contact condition is improved by adding a contact layer to form an ohmic contact with the metal electrode layer.

[0034] In the present invention, when the sub-cell is of p-type structure, the base layer is p-type doped, the buffer layer is n-type doped, and the contact layer is n-type doped; when the sub-cell is of n-type structure, the base layer is n-type doped, the buffer layer is p-type doped, and the contact layer is p-type doped.

[0035] As a preferred technical solution of the present invention, the sub-cell further includes an anti-reflection layer, which is disposed on the surface of the energy conversion layer, and a side of the anti-reflection layer away from the energy conversion layer is not covered.

[0036] Preferably, the anti-reflection layer includes at least one of MgF2, TiO2 or SiO2.

[0037] Preferably, the thickness of the anti-reflection layer is 100-150 nm, for example, 100 nm, 110 nm, 120 nm, 130 nm, 140 nm or 150 nm.

[0038] In the present invention, the anti-reflection layer can effectively reduce the reflection of light and increase the absorption of incident light. Further, when the contact layer is provided on the energy conversion layer, the anti-reflection layer can be provided on the contact layer or in the window or groove of the contact layer, so that one side of the anti-reflection layer is exposed to the outside.

[0039] As a preferred technical solution of the present invention, the sub-cell also includes a second insulating passivation layer, which covers the side surface not covered by the first insulating passivation layer in the thickness direction of the layer structure between the metal electrode layer and the buffer layer, so as to be isolated from the metal electrode layer of the adjacent sub-cell.

[0040] Preferably, the first insulating passivation layer and the second insulating passivation layer include at least one of SiO2, Si3N4 or PI.

[0041] As a preferred technical solution of the present invention, in the laser battery array chip, the number of sub-batteries is 4 to 42, for example, 4, 9, 12, 16, 20, 25, 28, 30, 32, 34, 36, 38, 40 or 42, etc.

[0042] Preferably, the output voltage of the laser battery array chip is 5~45V, for example, 5V, 10V, 13V, 17V, 21V, 26V, 28V, 30V, 32V, 34V, 36V, 38V, 40V, 43V or 45V, etc.

[0043] Preferably, the effective area of ​​the sub-cell is 0.225~2.5cm 2 , for example 0.225cm 2 、0.23cm2 、0.25cm 2 、0.27cm 2 、0.3cm 2 、0.32cm 2 、0.35cm 2 、0.38cm 2 、0.4cm 2 、0.5cm 2 、0.6cm 2 、0.7cm 2 、0.8cm 2 、0.9cm 2 , 1.0 cm 2 、1.2cm 2 , 1.5 cm 2 、1.8cm 2 , 2.0 cm 2 、2.3cm 2或 2.5cm 2 wait.

[0044] Preferably, the number of grid electrodes in the sub-cell is 6 to 10, for example, 6, 7, 8, 9 or 10.

[0045] Preferably, the width of the gate is 0.1-0.5 μm, for example, 0.1 μm, 0.15 μm, 0.2 μm, 0.25 μm, 0.3 μm, 0.35 μm, 0.4 μm, 0.45 μm or 0.5 μm.

[0046] In a second aspect, the present invention provides a method for manufacturing the laser battery array chip according to the first aspect, the manufacturing method comprising:

[0047] S1. A buffer layer and an energy conversion layer are sequentially stacked on the surface of a semi-insulating substrate;

[0048] S2. performing a first photolithography, wherein the first photolithography starts from the top surface of the energy conversion layer, and the etching depth reaches at least the bottom surface of the buffer layer to form a first photolithography groove, wherein the first photolithography groove includes an isolation groove formed in the buffer layer, and an extension groove formed in the energy conversion layer and connected to the isolation groove;

[0049] S3. Depositing an insulating material to fill the first photolithographic groove and cover the top surface of the energy conversion layer;

[0050] S4. performing a second photolithography to remove the insulating material covering the top surface of the energy conversion layer and forming a second photolithography groove in the extension groove, wherein the second photolithography groove forms a first insulating passivation layer with the insulating material in the first photolithography groove and exposes the buffer layer;

[0051] S5. depositing a metal electrode material to fill the second photolithographic groove and cover the top surface of the energy conversion layer, so that the metal electrode material in the second photolithographic groove is in contact with and electrically connected to the exposed buffer layer;

[0052] S6. performing a third photolithography process, wherein the third photolithography process opens a window on the metal electrode material covering the top surface of the energy conversion layer, and forms a third photolithography groove in the second photolithography groove to form a metal electrode layer, wherein the third photolithography groove cuts off the metal electrode layers of adjacent sub-cells, and forms the metal electrode material in the second photolithography groove into an electrode extension portion and an electrode connection portion;

[0053] S7. Perform annealing to obtain a laser battery array chip.

[0054] It should be noted that, in the present invention, the first insulating passivation layer can be further divided into a first part and a second part, the first part covers the side surfaces of the contact layer, the energy conversion layer and the ultra-thin heavily doped tunnel layer, and the second part is extended from the first part to cover the side surfaces of the buffer layer. That is, in the manufacturing process, in step S4, the first insulating passivation layer formed by the insulating material of the chromium ions in the second photolithography groove in the first photolithography groove is the second part in the isolation groove, and the part in the extension groove is the first part.

[0055] As a preferred technical solution of the present invention, the manufacturing method further comprises:

[0056] S1. A buffer layer, an ultra-thin heavily doped tunnel layer, an energy conversion layer and a contact layer are sequentially stacked on the surface of the semi-insulating substrate;

[0057] S2. Performing a first photolithography, wherein the first photolithography starts from the top surface of the contact layer and the etching depth reaches at least the bottom surface of the buffer layer to form a first photolithography groove, wherein the first photolithography groove includes an isolation groove formed in the buffer layer, and an extension groove formed in the ultra-thin heavily doped tunnel layer, the energy conversion layer and the contact layer and connected to the isolation groove;

[0058] S3. Depositing an insulating material to fill the first photolithographic groove and cover the top surface of the contact layer;

[0059] S4. performing a second photolithography to remove the insulating material covering the top surface of the contact layer and form an anti-reflection groove in the contact layer, and at the same time, the second photolithography forms a second photolithography groove in the extension groove, wherein the second photolithography groove causes the insulating material in the first photolithography groove to form a first insulating passivation layer and a second insulating passivation layer and exposes the buffer layer;

[0060] S5. depositing a metal electrode material to fill the second photolithography groove and cover the top surface of the contact layer, so that the metal electrode material in the second photolithography groove is in contact with and electrically connected to the exposed buffer layer;

[0061] S6. Performing a third photolithography process, wherein the third photolithography process opens a window on the metal electrode material covering the top surface of the contact layer, so that the anti-reflection groove is exposed and a gate is formed; at the same time, the third photolithography process forms a third photolithography groove in the second photolithography groove to form a metal electrode layer, wherein the third photolithography groove cuts off the metal electrode layers of adjacent sub-cells and forms an electrode extension portion and an electrode connection portion with the metal electrode material in the second photolithography groove;

[0062] S7. Preparing an anti-reflection layer in the anti-reflection groove;

[0063] S8. Annealing is performed at 80-100°C to obtain a laser cell array chip.

[0064] In the present invention, the etching depth of the first photolithography needs to reach at least the bottom surface of the buffer layer so that the isolation groove can completely isolate the two sub-cells after being filled with insulating material (i.e., the second part), thereby avoiding internal conduction between the sub-cells and causing leakage.

[0065] In the present invention, the annealing temperature is 80-100°C, for example, it can be 80°C, 85°C, 90°C, 95°C or 100°C.

[0066] Preferably, the method for preparing the buffer layer, the energy conversion layer and the contact layer comprises metal organic chemical vapor deposition.

[0067] Preferably, the method of depositing the insulating material comprises chemical vapor deposition or atomic layer deposition.

[0068] Preferably, the method of depositing the metal electrode material comprises electron beam evaporation or sputtering.

[0069] Preferably, the method for preparing the anti-reflection layer comprises chemical vapor deposition or atomic layer deposition.

[0070] Preferably, the first photolithography, the second photolithography and the third photolithography methods all include positive photolithography.

[0071] It should be noted that the shapes of the photolithography grooves formed by the first photolithography, the second photolithography and the third photolithography in the present invention, as well as the overall shape of the layer structure such as the energy conversion layer after photolithography are not specifically limited. As long as the insulating passivation layer can ultimately support the metal electrode and the buffer layer to form a leakage-free series connection, so that each sub-battery can be horizontally connected end to end and connected in series in sequence, the purpose of the present invention is met.

[0072] In a third aspect, the present invention provides an application of the laser battery array chip described in the second aspect, wherein the application includes wireless charging of drones.

[0073] Due to space limitations and to avoid redundancy, the present invention does not exhaustively list all point values ​​within the above numerical range, but is not limited to the listed values, and other unlisted values ​​within the above numerical range are also applicable.

[0074] Compared with the prior art solutions, the present invention has at least the following beneficial effects:

[0075] (1) The present invention realizes lateral series connection between sub-batteries through the semi-insulating substrate at the bottom of the chip and the metal electrode on the chip. This design greatly improves the laser energy conversion efficiency per unit area. The side of the energy conversion layer and the buffer layer is passivated by the first insulating passivation layer to isolate and insulate them from the metal electrode layer and the electrode extension part extending therefrom, effectively solving the battery leakage problem, and can form an electrical connection with the buffer layer of the adjacent sub-battery through the electrode connecting part further extending from the electrode extension part. The laser energy conversion battery array chip designed using this chip process has extremely high output energy density, smaller volume and weight, and is therefore more suitable for future applications in fields such as wireless charging of drones.

[0076] (2) The present invention adds an ultra-thin heavily doped tunnel layer to the battery structure, thereby increasing the longitudinal electrical contact of the battery to achieve high tunneling current density and low tunneling voltage drop, which is more conducive to the series connection of multiple batteries and realizes the design of a tunnel junction with a large tunneling current density; by adding a contact layer to form an ohmic contact with the metal electrode layer, the contact condition is effectively improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0077] Figure 1 is a top view schematic diagram of the laser battery array chip described in Example 1;

[0078] Figure 2 yes Figure 1 Schematic diagram of the cross section along the AA direction;

[0079] Figure 3 is a manufacturing flow chart of the laser battery array chip described in Example 1, corresponding to steps S1 to S7 in the manufacturing method;

[0080] Figure 4 is a top view schematic diagram of the laser cell array chip described in Example 2;

[0081] Figure 5 is a top view schematic diagram of the laser battery array chip described in Example 3;

[0082] Figure 6 is a top view schematic diagram of the laser battery array chip described in Example 4;

[0083] Figure 1-6 In: 1-semi-insulating substrate, 2-buffer layer, 3-ultra-thin heavily doped tunnel layer, 4-back field layer, 5-base layer, 6-emitter layer, 7-window layer, 8-contact layer, 9-anti-reflection layer, 10-metal electrode layer, 11-electrode extension portion, 12-electrode connection portion, 20-first insulating passivation layer, 21-first portion, 22-second portion, 30-second insulating passivation layer, 40-first photolithography groove, 41-extension groove, 42-isolation groove, 50-insulating material, 60-anti-reflection groove, 70-metal electrode material;

[0084] Figure 7 This is a physical picture of the laser battery array chip obtained in Example 4;

[0085] Figure 8 This is a test result diagram of the laser battery array chip obtained in Example 4. DETAILED DESCRIPTION

[0086] The technical solution of the present invention is further illustrated below through specific implementation methods.

[0087] It should be clear to those skilled in the art that the embodiments are only intended to help understand the present invention and should not be considered as specific limitations of the present invention.

[0088] Example 1

[0089] This embodiment provides a laser battery array chip, such as Figure 1 and Figure 2 As shown, it includes a semi-insulating substrate 1 and a 5*6 (5 rows and 6 columns) battery array arranged thereon; the battery array includes 30 sub-batteries connected in series in sequence from head to tail; each of the sub-batteries includes a buffer layer 2, an ultra-thin heavily doped tunnel layer 3, an energy conversion layer (including a back field layer 4, a base layer 5, an emission layer 6 and a window layer 7 from bottom to top), a contact layer 8 and a metal electrode layer 10 arranged in sequence from bottom to top; the sub-battery also includes an anti-reflection layer 9, which is arranged in the contact layer 8 and is not covered on a side away from the energy conversion layer;

[0090] The subcell is a GaAs cell; the semi-insulating substrate 1 is GaAs; the buffer layer 2 is n-GaAs with a thickness of 0.5 μm; the ultra-thin heavily doped tunnel layer 3 is AlGaAs with a thickness of 10 nm; the back field layer 4 is GaAs with an ln doping concentration of 51% (calculated by In molar amount / (In molar amount + Ga molar amount)) and a thickness of 50 nm. x In 1-x The base layer 5 is a p-Ga with an In doping concentration of 1% and a thickness of 3.0 μm. x In 1-xAs; the emission layer 6 is GaAs with an In doping concentration of 2% and a thickness of 150nm x In 1-x As; the window layer 7 is ln doping concentration of 52% (calculated by In molar amount / (In molar amount + Al molar amount)), the thickness of Al is 500nm x In 1-x P; the contact layer 8 is n-GaAs, and the maximum thickness of the contact layer 8 (the portion not embedded in the anti-reflection layer 9 and in contact with the metal electrode layer 10) is 500nm; the anti-reflection layer 9 is MgF2 with a thickness of 140nm;

[0091] The sub-cell further includes a first insulating passivation layer 20 and a second insulating passivation layer 30, wherein the first insulating passivation layer 20 has a first portion 21 covering one side of the ultra-thin heavily doped tunnel layer 3, the energy conversion layer and the contact layer 8, and a second portion 22 extending from the first portion 21 to cover one side of the buffer layer 2, and the second portion 22 extends into the semi-insulating substrate 1; the second insulating passivation layer 30 covers the side of the layer structure between the metal electrode layer 10 and the buffer layer 2 that is not covered by the first insulating passivation layer 20, and the first insulating passivation layer 20 and the second insulating passivation layer 30 isolate adjacent sub-cells; the first insulating passivation layer 20 and the second insulating passivation layer 30 are both SiO2;

[0092] The sub-cell further comprises an electrode extension portion 11 connected to the metal electrode layer 10 and extending on and covering the first insulating passivation layer 20, and an electrode connection portion 12 extending from the electrode extension portion 11 to contact and electrically connect with the buffer layer 2 of the adjacent sub-cell; the electrode extension portion 11 and the electrode connection portion 12 are located between the first insulating passivation layer 20 and the second insulating passivation layer 30 of the adjacent sub-cell; the metal electrode layer 10, the electrode extension portion 11 and the electrode connection portion 12 are Ag;

[0093] The effective area of ​​each subcell is 0.32cm 2 , the number of gates in the sub-cell is 6, each with a width of 0.1μm; the minimum spacing between the energy conversion layers of two adjacent sub-cells connected in series ( Figure 1 The S shown in the enlarged area of ​​the dashed box is 0.5 μm, and the size of the laser battery array chip is ( Figure 1 Medium L) is 3.5cm, width ( Figure 1 Middle W) is 3.25cm.

[0094] Figure 1 The direction of current flow (red arrow) and the circuit route (black curve where the red arrow is located) are also indicated.

[0095] like Figure 3 As shown, the manufacturing method of the laser battery array chip includes:

[0096] S1. Using MOCVD method, a buffer layer 2, an ultra-thin heavily doped tunnel layer 3, an energy conversion layer (a back field layer 4, a base layer 5, an emission layer 6 and a window layer 7) and a contact layer 8 are sequentially stacked on the surface of the semi-insulating substrate 1;

[0097] S2. Performing a first photolithography using RD-2900 positive photoresist, wherein the first photolithography starts from the top surface of the contact layer 8 and the etching depth reaches at least the bottom surface of the buffer layer 2 to form a first photolithography groove 40, wherein the first photolithography groove 40 includes an isolation groove 42 formed in the buffer layer 2, and an extension groove 41 formed in the ultra-thin heavily doped tunnel layer 3, the energy conversion layer and the contact layer 8 and connected to the isolation groove 42;

[0098] S3. Depositing an insulating material 50 using an ALD method to fill the first photolithographic groove 40 and cover the top surface of the contact layer 8;

[0099] S4. Performing a second photolithography using RD-2900 positive photoresist to remove the insulating material 50 covering the top surface of the contact layer 8 and form an anti-reflection groove 60 in the contact layer 8, and at the same time, the second photolithography forms a second photolithography groove in the extension groove 41, wherein the second photolithography groove causes the insulating material 50 in the extension groove 41 to form a first portion 21 of the first insulating passivation layer 20 and a second insulating passivation layer 30 and exposes the buffer layer 2, and the insulating material 50 filled in the isolation groove 42 forms a second portion 22 of the first insulating passivation layer 20;

[0100] S5. Depositing a metal electrode material 70 by electron beam evaporation to fill the second photolithography groove and cover the top surface of the contact layer 8, so that the metal electrode material 70 in the second photolithography groove is in contact with the exposed buffer layer 2 and is electrically connected;

[0101] S6. Performing a third photolithography process using RD-2900 positive photoresist, wherein the third photolithography process opens a window on the metal electrode material 70 covering the top surface of the contact layer 8, so that the anti-reflection groove 60 is exposed and a gate electrode is formed; at the same time, the third photolithography process forms a third photolithography groove in the second photolithography groove to form a metal electrode layer 10, wherein the third photolithography groove cuts off the metal electrode layers 10 of adjacent sub-cells and forms the metal electrode material 70 in the second photolithography groove into an electrode extension portion 11 and an electrode connection portion 12; the electrode connection portion 12 is isolated from the adjacent sub-cell by a second insulating passivation layer 30;

[0102] S7. Preparing an anti-reflection layer 9 in the anti-reflection groove 60 using a CVD method;

[0103] S8. Annealing is performed at 95°C to obtain a laser cell array chip.

[0104] Example 2

[0105] This embodiment provides a laser battery array chip, such as Figure 4 As shown, it includes a semi-insulating substrate 1 and a 5*5 (5 rows and 5 columns) battery array arranged thereon; the battery array includes 25 sub-batteries connected in series in sequence from head to tail; the effective area of ​​each sub-battery is 0.4cm 2 The number of grid lines in the sub-cell is 6, and the width of each grid line is 0.1 μm; the minimum spacing between the energy conversion layers of two adjacent sub-cells connected in series is 0.5 μm. The size of the obtained laser battery array chip is 3.5 cm in length and 3.25 cm in width. Except for the above, other conditions are exactly the same as those in Example 1.

[0106] Example 3

[0107] This embodiment provides a laser battery array chip, such as Figure 5 As shown, it includes a semi-insulating substrate 1 and a 6*6 (6 rows and 6 columns) battery array arranged thereon; the battery array includes 36 sub-batteries connected in series in sequence from head to tail; the effective area of ​​each sub-battery is 0.27cm 2 The number of grid lines in the sub-cell is 6, and the width of each grid line is 0.1 μm; the minimum spacing between the energy conversion layers of two adjacent sub-cells connected in series is 0.5 μm. The size of the obtained laser battery array chip is 3.5 cm in length and 3.25 cm in width. Except for the above, other conditions are exactly the same as those in Example 1.

[0108] Example 4

[0109] This embodiment provides a laser battery array chip, such as Figure 6 and Figure 7 As shown, it includes a semi-insulating substrate 1 and a 6*7 (6 rows and 7 columns) battery array arranged thereon; the battery array includes 42 sub-batteries connected in series in sequence from head to tail; the effective area of ​​each sub-battery is 0.225cm 2 The number of grid lines in the sub-cell is 6, and the width of each grid line is 0.1 μm; the minimum spacing between the energy conversion layers of two adjacent sub-cells connected in series is 0.5 μm. The size of the obtained laser battery array chip is 3.5 cm in length and 3.25 cm in width. Except for the above, other conditions are exactly the same as those in Example 1.

[0110] The laser battery array chip obtained in Examples 1-4 can be used for laser energy conversion for 808nm laser, wherein, Figure 8As shown in the figure, the performance test diagram of the laser battery array chip obtained in Example 4 is as follows. It can be seen from the figure that the laser battery array chip obtained in Example 4 has a high power consumption of 1000W / m 2 Under 808nm laser irradiation, the chip open circuit voltage is 45V and the current density is 72mA / cm 2 , filling factor 67%, energy conversion efficiency 51%, and the results of other embodiments are recorded in Table 1.

[0111] Table 1

[0112] Group Open circuit voltage(V) <![CDATA[Current density (mA / cm 2 )]]> Fill factor(%) Energy conversion efficiency (%) Example 1 31 70 65 47 Example 2 26 71 70 52 Example 3 38 69 73 53 Example 4 45 72 67 51

[0113] From the above, it can be seen that the present invention realizes the lateral series connection between sub-batteries through the semi-insulating substrate 1 at the bottom of the chip and the metal electrode on the chip. This design greatly improves the laser energy conversion efficiency per unit area. The energy conversion layer and the side of the buffer layer 2 are passivated by the first insulating passivation layer 20 to isolate and insulate them from the electrode extension 11 of the metal electrode layer 10, effectively improving the leakage problem of the battery. An ultra-thin heavily doped tunnel layer 3 is further added to the battery structure to increase the longitudinal electrical contact of the battery to achieve high tunneling current density and low tunneling voltage drop, which is more conducive to the series connection of multiple batteries and the design of a tunnel junction with a large tunnel current density; by adding a contact layer 8 to form an ohmic contact with the metal electrode, the contact condition is effectively improved. The laser energy conversion battery array chip designed using this chip process has an extremely high output energy density, a smaller volume and weight, and is therefore more suitable for future applications in fields such as wireless charging of drones.

[0114] The preferred embodiments of the present invention are described in detail above. However, the present invention is not limited to the specific details in the above embodiments. Within the technical concept of the present invention, a variety of simple modifications can be made to the technical solution of the present invention, and these simple modifications all belong to the protection scope of the present invention.

[0115] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, the present invention will not further describe various possible combinations.

[0116] In addition, various embodiments of the present invention may be arbitrarily combined, and as long as they do not violate the concept of the present invention, they should also be regarded as the contents disclosed by the present invention.

Claims

1. A laser battery array chip, characterized in that: It comprises a semi-insulating substrate (1) and a battery array arranged on its surface; the battery array comprises sub-batteries connected in series end to end; the sub-batteries comprise a buffer layer (2), an energy conversion layer and a metal electrode layer (10) which are stacked in sequence; The sub-cell further comprises a first insulating passivation layer (20), the first insulating passivation layer (20) covering the energy conversion layer and one side surface of the buffer layer (2) in the thickness direction, the first insulating passivation layer (20) isolating adjacent sub-cells; The sub-cell further comprises an electrode extension portion (11) connected to the metal electrode layer (10) and covering the first insulating passivation layer (20), and an electrode connection portion (12) connected to the electrode extension portion (11) and in contact with and electrically connected to the buffer layer (2) of an adjacent sub-cell.

2. The laser cell array chip according to claim 1, characterized in that: The subcell includes a GaAs cell; The energy conversion layer comprises a back field layer (4), a base layer (5), an emission layer (6) and a window layer (7) which are arranged in sequence from bottom to top; The energy conversion layer comprises at least one of GaAs, GaInAs, GaAlAs, GaAlInAs, GaInP or AlInP; The In doping concentration of the back field layer (4) is less than 30%, and the thickness of the back field layer (4) is 50-100 nm; The In doping concentration of the base layer (5) is less than 30%, and the thickness of the base layer (5) is 3-4 μm; The In doping concentration of the emission layer (6) is less than 30%, and the thickness of the emission layer (6) is 150-200 nm; The In doping concentration of the window layer (7) is less than 30%, and the thickness of the window layer (7) is 400-500 nm; The semi-insulating substrate (1) comprises GaAs; The buffer layer (2) comprises n-GaAs, and the thickness of the buffer layer (2) is 0.5-0.8 μm; The metal electrode layer (10), the electrode extension portion (11) and the electrode connection portion (12) include at least one of Ag, Au, Ti or Pt.

3. The laser cell array chip according to claim 1, characterized in that: The sub-cell further comprises an ultra-thin heavily doped tunnel layer (3), the ultra-thin heavily doped tunnel layer (3) being arranged between the buffer layer (2) and the energy conversion layer which are stacked, and one side surface of the ultra-thin heavily doped tunnel layer (3) in the thickness direction is covered by the first insulating passivation layer (20); The ultra-thin heavily doped tunnel layer (3) comprises GaAs and / or AlGaAs; The total thickness of the ultra-thin heavily-doped tunnel layer (3) is 10-20 nm.

4. The laser cell array chip according to claim 1, characterized in that: The sub-cell further comprises a contact layer (8), the contact layer (8) being arranged between the stacked energy conversion layer and the metal electrode layer (10), and one side surface of the contact layer (8) in the thickness direction being covered by the first insulating passivation layer (20); The contact layer (8) comprises n-GaAs; The maximum thickness of the contact layer (8) is 500-600 nm.

5. The laser cell array chip according to claim 1, characterized in that: The subcell further comprises an anti-reflection layer (9), wherein the anti-reflection layer (9) is arranged on the surface of the energy conversion layer, and a side of the anti-reflection layer (9) away from the energy conversion layer is not covered; The anti-reflection layer (9) comprises at least one of MgF2, TiO2 or SiO2, and has a thickness of 100-150 nm.

6. The laser cell array chip according to claim 1, characterized in that: The sub-cell further comprises a second insulating passivation layer (30), the second insulating passivation layer (30) covering the side surface of the layer structure between the metal electrode layer (10) and the buffer layer (2) that is not covered by the first insulating passivation layer (20) in the thickness direction, so as to be isolated from an adjacent sub-cell; The first insulating passivation layer (20) and the second insulating passivation layer (30) include at least one of SiO2, Si3N4 or PI.

7. The laser cell array chip according to claim 1, characterized in that: In the laser battery array chip, the number of sub-batteries is 4 to 42; The output voltage of the laser battery array chip is 5~45V; The effective active area of ​​the subcell is 0.225~2.5cm 2 ; The number of grids in the sub-cell is 6 to 10, and the width of the grid is 0.1 to 0.5 μm; The minimum spacing between the energy conversion layers of two adjacent sub-cells connected in series is 0.5~1μm.

8. A method for manufacturing a laser battery array chip according to any one of claims 1 to 7, characterized in that: The manufacturing method comprises: S1. A buffer layer (2) and an energy conversion layer are sequentially stacked on the surface of a semi-insulating substrate (1); S2. performing a first photolithography, wherein the first photolithography starts from the top surface of the energy conversion layer and the etching depth reaches at least the bottom surface of the buffer layer (2), thereby forming a first photolithography groove (40), wherein the first photolithography groove (40) comprises an isolation groove (42) formed in the buffer layer (2), and an extension groove (41) formed in the energy conversion layer and connected to the isolation groove (42); S3. depositing an insulating material (50) to fill the first photolithography groove (40) and cover the top surface of the energy conversion layer; S4. performing a second photolithography to remove the insulating material (50) covering the top surface of the energy conversion layer, and forming a second photolithography groove in the extension groove (41), wherein the second photolithography groove causes the insulating material (50) in the first photolithography groove (40) to form a first insulating passivation layer (20) and exposes the buffer layer (2); S5. depositing a metal electrode material (70) to fill the second photolithography groove and cover the top surface of the energy conversion layer, so that the metal electrode material (70) in the second photolithography groove is in contact with and electrically connected to the exposed buffer layer (2); S6. performing a third photolithography, wherein the third photolithography opens a window on the metal electrode material (70) covering the top surface of the energy conversion layer, and forms a third photolithography groove in the second photolithography groove to form a metal electrode layer (10), wherein the third photolithography groove cuts off the metal electrode layers (10) of adjacent sub-cells, and forms the metal electrode material (70) in the second photolithography groove into an electrode extension portion (11) and an electrode connection portion (12); S7. Perform annealing to obtain a laser battery array chip.

9. The method for manufacturing a laser battery array chip according to claim 8, characterized in that: The manufacturing method further comprises: S1. On the surface of the semi-insulating substrate (1), a buffer layer (2), an ultra-thin heavily doped tunnel layer (3), an energy conversion layer and a contact layer (8) are sequentially stacked; S2. performing a first photolithography, wherein the first photolithography starts from the top surface of the contact layer (8) and the etching depth reaches at least the bottom surface of the buffer layer (2), thereby forming a first photolithography groove (40), wherein the first photolithography groove (40) comprises an isolation groove (42) formed in the buffer layer (2), and an extension groove (41) formed in the ultra-thin heavily doped tunnel layer (3), the energy conversion layer and the contact layer (8) and connected to the isolation groove (42); S3. depositing an insulating material (50) to fill the first photolithography groove (40) and cover the top surface of the contact layer (8); S4. performing a second photolithography to remove the insulating material (50) covering the top surface of the contact layer (8) and form an anti-reflection groove (60) in the contact layer (8); and at the same time, the second photolithography forms a second photolithography groove in the extension groove (41), wherein the second photolithography groove causes the insulating material (50) in the first photolithography groove (40) to form a first insulating passivation layer (20) and a second insulating passivation layer (30) and exposes the buffer layer (2); S5. depositing a metal electrode material (70) to fill the second photolithography groove and cover the top surface of the contact layer (8), so that the metal electrode material (70) in the second photolithography groove is in contact with and electrically connected to the exposed buffer layer (2); S6. performing a third photolithography process, wherein the third photolithography process opens a window on the metal electrode material (70) covering the top surface of the contact layer (8), so that the anti-reflection groove (60) is exposed and a gate is formed; at the same time, the third photolithography process forms a third photolithography groove in the second photolithography groove to form a metal electrode layer (10), wherein the third photolithography groove cuts off the metal electrode layers (10) of adjacent sub-cells and forms the metal electrode material (70) in the second photolithography groove into an electrode extension portion (11) and an electrode connection portion (12); S7. Preparing an anti-reflection layer (9) in the anti-reflection groove (60); S8. Annealing is performed at 80-100°C to obtain a laser cell array chip.

10. An application of the laser battery array chip according to any one of claims 1 to 7, characterized in that: The applications include wireless charging of drones.

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