Industrial network controller architecture for realizing TTP protocol based on programmable logic

Abstract

The invention discloses an industrial network controller architecture for realizing a TTP protocol based on programmable logic, the architecture is formed by connecting at least two controllers, and each controller comprises a network data processing module based on an FPGA, a data interface module, a storage module, a clock module and a power supply module. According to the invention, high-security control and scheduling can be provided for the distributed industrial network. According to the invention, on the basis of an FPGA (Field Programmable Gate Array) chip XC7K325T-1FFG900I and a PHY (Physical Layer) chip RTL8211E-VB, a clock module is provided with a clock frequency multiplication chip HMC7044. An RJ45 socket and a 10G SFP + optical port in the data interface module can realize high-speed and high-throughput network data transceiving and processing functions, and an FPGA chip can realize TTP protocol processing and high-speed signal data analysis, calculation and forwarding functions, so that high efficiency of operation is ensured; and the PHY chip realizes data packet decoding of a network physical layer, so that the reliability of data is ensured. Compared with a traditional industrial network controller, the industrial network controller has the advantages of customizable development, low time delay, high safety, high throughput rate and the like.

Description

Technical Field

[0001] The invention belongs to the field of network communication and network information processing, and is an industrial network controller architecture for implementing a TTP protocol (time triggered protocol) based on programmable logic. Background Art

[0002] Faced with the continuous expansion and deepening of digital application scenarios, the delay of traditional general-purpose industrial network controllers can only be controlled at the millisecond level, which cannot meet the needs of new intelligent production and manufacturing. In addition, due to the explosive growth of data, the traditional industrial network control mode has defects such as high operation and maintenance costs, low real-time performance, and poor data privacy.

[0003] The security issues of the Industrial Internet are prominent, privacy and data protection are facing challenges, security protection capabilities are insufficient, and equipment security is lacking. These problems have affected the development and application of the Industrial Internet and require a more complete network architecture and security assurance system to solve them. The Time-triggered Protocol (Time-triggered protocol, protocol number: SAE AS6003, hereinafter referred to as TTP) is a real-time communication protocol based on time triggering, which can be used to build distributed systems with hard real-time requirements and improve the security and reliability of the system. Summary of the invention

[0004] The purpose of the present invention is to meet the above needs and provide an industrial network controller architecture based on programmable logic to implement the TTP protocol. The periphery of the FPGA chip in the controller is equipped with a large number of 10 / 100 / 1000M Ethernet interfaces and 10G SFP+ optical network interfaces, which can realize network data transmission, reception and processing functions. The FPGA chip internally follows the TTP protocol and TDMA concept to perform functions such as data frame unpacking, packet assembly, analysis and forwarding.

[0005] The specific technical solution for achieving the purpose of the present invention is:

[0006] An industrial network controller architecture for implementing a TTP protocol based on programmable logic, the architecture is formed by connecting at least two controllers, wherein the controller comprises a network data processing module based on FPGA, a data interface module, a storage module, a clock module and a power module, wherein the network data processing module based on FPGA is connected to the data interface module, the storage module and the clock module, and is used to receive, store, forward and calculate network data according to the TTP protocol; the data interface module is connected to the network data processing module based on FPGA and the clock module, and is responsible for receiving and sending network data packets; the storage module is connected to the network data processing module based on FPGA and the clock module, and is used for caching when the FPGA chip processes data and solidifying and burning the configuration program; the clock module is connected to the network data processing module based on FPGA, the data interface module and the storage module, and provides a reference clock for various chips of each module; the power module is connected to the network data processing module based on FPGA, the data interface module, the storage module and the clock module, and supplies power to each module; the industrial network data stream can be transmitted between the controllers through the data interface module, wherein:

[0007] The FPGA-based network data processing module is inside the FPGA chip, including a data parsing and assembly module and a data calculation and forwarding module. The data parsing and assembly module and the data calculation and forwarding module are connected to each other through a FIFO composed of a G-bit transceiver and a logic unit inside the FPGA chip to realize network data processing that complies with the TTP protocol.

[0008] The data interface module is outside the FPGA chip, including a PHY chip, an RJ45 socket and a 10G SFP+ optical port. The PHY chip is connected to the RJ45 socket and the FPGA-based network data processing module to realize the sending and receiving of 10 / 100 / 1000M network data packets; the 10G SFP+ optical port is connected to the FPGA-based network data processing module to realize the sending and receiving of 10G optical network data packets.

[0009] The storage module is outside the FPGA chip and includes a DDR3 cache module and a FLASH memory. The DDR3 cache module is connected to the FPGA-based network data processing module to provide a cache for the FPGA chip when processing a large amount of high-speed network data; the FLASH memory is connected to the FPGA-based network data processing module to be used for program curing and burning of the FPGA chip.

[0010] The clock module is outside the FPGA chip and is provided with a clock multiplication module for generating a clock source required for the normal operation of the FPGA chip and the TTP protocol.

[0011] The data parsing and assembling module in the FPGA-based network data processing module performs data unpacking and packet assembly according to the TTP frame format; the data calculation and forwarding module can process the unpacked application data information, and forward the data packet to the corresponding node in the specified time slot according to the TTP protocol and TDMA concept.

[0012] The data interface module provides 12 independent 10 / 100 / 1000M Ethernet interfaces consisting of PHY chips and RJ45 sockets; provides 8 independent 10G SFP+ optical ports; the data interface module can provide a total throughput of 133.92Mpps.

[0013] The DDR3 cache module in the storage module uses four 2Gb 16bit DDR3 chips with a maximum rate of 1600MT / s; the FLASH memory is used to configure the TTP protocol related programs of the FPGA chip. The single-chip capacity of the FLASH memory is 1Gb, and the two chips have a total capacity of 2Gb.

[0014] The clock frequency multiplication module in the clock module uses the chip HMC7044, which is used to provide different reference clocks required by the FPGA chip to run the TTP protocol program.

[0015] The present invention uses Vivado provided by Xilinx to compile, synthesize and generate bitstream files for the hardware description language (Verilog / VHDL) used by the FPGA chip. The FPGA chip is rich in 300K logic units, 16Mb of RAM, 16 GTX transceivers, etc., and realizes forwarding of high-speed network data to corresponding nodes within a specified time slot according to the TTP protocol, thereby controlling the collaborative work of equipment under various industrial networks.

[0016] The beneficial effects of the present invention are:

[0017] a. The present invention is an industrial network controller architecture based on programmable logic to implement the TTP protocol. The protocol decomposes large embedded applications into clusters and nodes, and provides a known precision fault-tolerant global time at each node, and uses it to accurately specify the interface between nodes, thereby simplifying communication, establishing state consistency, performing timely error detection, and ensuring the safety and stability of industrial network equipment during operation.

[0018] b. The TTP protocol implemented by the present invention is completely implemented by hardware circuits, and has a rich number of hardware interfaces, which can meet the needs of large-scale industrial scenarios.

[0019] c. The present invention provides different reference clocks required by different nodes in the TTP protocol through a clock multiplication chip, which can be used to adapt to industrial control scenarios with special rate transmission.

[0020] d. The present invention implements TTP protocol processing through FPGA chip, which increases the 4M / 25MHz frequency range originally applicable to the TTP protocol to the GHz level, reduces data transmission and processing delays, and improves the working efficiency of the network controller.

[0021] e. This industrial network controller can be connected via optical fiber, thereby effectively suppressing the impact of electromagnetic interference in the industrial environment. Due to the TDMA concept in the TTP protocol, a fault tolerance threshold can be provided for the information transmission of each controller, thereby achieving efficient, real-time and comprehensive data intercommunication, remote management operation of industrial equipment and real-time data interaction.

[0022] f. The present invention can provide a hardware architecture for large-scale industrial scenarios with functional requirements such as edge data storage, high-speed data communication, high-speed data processing, high-precision drug synthesis control, and AI data analysis, while ensuring the safe and stable operation of the entire system, reducing data processing delays and improving data throughput. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a structural block diagram of the present invention;

[0024] Figure 2 It is a schematic diagram of the workflow of the present invention. DETAILED DESCRIPTION

[0025] The present invention is described in detail below in conjunction with the accompanying drawings.

[0026] See also Figure 1 , the present invention is an industrial network controller architecture for implementing TTP protocol based on programmable logic.

[0027] The present invention is formed by connecting at least two controllers, and the controller includes an FPGA-based network data processing module 1, a data interface module 2, a storage module 3, a clock module 4 and a power module 5. The industrial network data stream is transmitted between the controllers through the data interface module 2.

[0028] The FPGA-based network data processing module 1 is inside the FPGA chip, including a data parsing and assembly module 11 and a data calculation and forwarding module 12. The data parsing and assembly module 11 and the data calculation and forwarding module 12 are connected, and are connected through a 16-bit deep FIFO composed of a GTH transceiver and a logic unit inside the FPGA chip to implement network data processing that complies with the TTP protocol. All controllers read data frames containing status information from the communication network interface (CNI, i.e., data interface module 2) at the sending node at a priori known acquisition time, and transmit it to the CNI of all receiving nodes in the cluster at a priori known transmission time, overwriting the previous version of the frame. The periodic acquisition and transmission times are included in the scheduling table in the communication controller, and the scheduling table is uniformly known to all network controllers in the cluster.

[0029] The data interface module 2 is outside the FPGA chip and provides 12 independent 10 / 100 / 1000M Ethernet interfaces consisting of a PHY chip 21 and an RJ45 socket 22, supporting the GMII / RGMII interface, which provides all the functions required for the transmission of network data packets at the physical layer; 8 independent 10G SFP+ optical ports 23, which comply with the "SFP+10Gbs and Low Speed ​​Electrical Interface (SFF-8431)" standard, and the differential pair rates of the transceiver interfaces are both 10.3125Gb / s, which is consistent with the GTX maximum rate of the FPGA chip.

[0030] The storage module 3 is outside the FPGA chip and provides data cache for the FPGA chip to perform high-speed signal processing according to the TTP protocol through the DDR3 cache module 31; the FLASH memory 32 is used to configure and solidify the TTP protocol, node number, time slot allocation and other configuration programs of the FPGA chip.

[0031] The clock module 4 is outside the FPGA chip and selects a reference and generates a frequency with ultra-low phase noise through a clock multiplication module 41. It supports high-speed data converters with parallel or serial interfaces. The module has two integer mode PLLs and overlapping on-chip VCOs that can be selected through SPI, with tuning ranges of 2.5 GHz and 3 GHz respectively.

[0032] The power module 5 is produced by combining TPS62130, TPS53355, TPS51200 and MAX8556 to supply power to the FPGA chip (including the FPGA-based network data processing module 1 ), the PHY chip 21 , the DDR3 cache module 31 , the FLASH memory 32 and the clock multiplication module 41 .

[0033] See also Figure 1,In the figure, the black arrows represent circuit connections, and the red arrows represent ,industrial network data flows.

[0034] The connection methods of each module are as follows:

[0035] The FPGA-based network data processing module 1 is connected to the data interface module 2, the storage module 3 and the clock module 4, the data interface module 2 is connected to the FPGA-based network data processing module 1 and the clock module 4, the storage module 3 is connected to the FPGA-based network data processing module 1 and the clock module 4, and the power module 5 is connected to the FPGA-based network data processing module 1, the data interface module 2, the storage module 3 and the clock module 4. The industrial network data stream is transmitted between the controllers through the data interface module 2.

[0036] In the FPGA chip of the present invention, the information that needs to be configured is as follows:

[0037] The number of nodes and the upper limit of allocatable time slots in the TTP protocol of the present invention.

[0038] The frame structure types and processing methods that the TTP protocol can support in the data storage configuration of the present invention.

[0039] The clock multiplication module of the present invention needs to provide a reference clock for each node communication.

[0040] In the interface configuration of the present invention, the 10 / 100 / 1000M Ethernet interface and 10G SFP+ optical port number to be enabled are input.

[0041] The configuration is now complete.

[0042] The present invention completes the sending, receiving, storing and processing of network data packets following the TTP protocol format through an FPGA chip, completes the caching of application data through a DDR3 cache module, completes the solidification and burning of FPGA chip programs through a FLASH memory, and provides the reference clock required for the operation of the FPGA chip and each node executing the TTP protocol through a clock multiplication module.

[0043] See also Figure 2 , the present invention works like this:

[0044] The user first configures the topology of each node or cluster on the FPGA chip, the send and receive time slot allocation of each node, the number of controllers connected, and solidifies the data processing program in the FLASH memory. Then power on all controllers, and after powering on, start receiving network data that follows the TTP protocol format. Here, take the first controller transmitting network data to the second controller as an example:

[0045] There are two ways to input network data packets: the first is to receive them through the RJ45 socket, and then the PHY chip translates them and transmits them to the FPGA chip for processing; the second is to transmit them directly to the FPGA chip for processing through the 10G SFP+ optical port. At the same time, the frequency multiplier chip of the clock module starts to provide a reference clock of the corresponding frequency according to the reference clock specified in the configuration information. If the configuration program is not completed when the network data is received, the second controller will directly discard the data information; when the configuration is completed and the current time slot is the receiving time slot of the second controller, the second controller will start to monitor and receive network data, and parse and classify it.

[0046] The classification method is based on the frame format of the TTP protocol. First, the explicit or implicit control state of the frame header is determined. If it is implicit, it means that this frame only has application data and is an N frame (general frame), which is processed as an N frame. If it is an explicit control state, it is classified according to whether the value of the cluster mode in the frame is greater than 0. If the cluster mode is equal to 0, it is a Cold Start frame and is processed as a Cold Start frame. After the value of the cluster mode is greater than 0, it is classified according to whether the frame carries application data. If not, it is an I frame (initialization frame), otherwise it is an X frame (extended frame). Then, data is parsed and processed according to the corresponding frame format. During the data processing process, the DDR3 cache module is used to cache some configuration information that has not been processed in time. After all types of frames are processed, the configuration information carried by each frame is extracted, including which time slot the frame is to be forwarded, the target node or cluster to be forwarded, the number of forwardings, and whether mode switching is required.

[0047] Finally, the data is repacked according to the configuration information requirements, and then output through the RJ45 socket or 10G SFP+ optical port, so that the data is sent to the specified controller node in the specified time slot. For example, if it is sent to the third controller in the next time slot, the third controller will start monitoring and receiving the data packet in the next time slot. And so on, so as to achieve the collaborative work of 1, 2, or n controllers.

Claims

1. An industrial network controller architecture for implementing the TTP protocol based on programmable logic, characterized in that: The architecture is formed by connecting at least two controllers, wherein the controller comprises an FPGA-based network data processing module (1), a data interface module (2), a storage module (3), a clock module (4) and a power module (5); the FPGA-based network data processing module (1) is connected to the data interface module (2), the storage module (3), the clock module (4) and the power module (5) and is used for receiving, storing, forwarding and calculating network data; the data interface module (2) is connected to the FPGA-based network data processing module (1) and the clock module (4) and is responsible for receiving and sending network data packets; the storage module (3) is connected to the FPGA-based network data processing module (1) and the clock module (4) and is responsible for storing various configuration programs of the FPGA chip and providing a cache during the data processing process; The clock module (4) is connected to the FPGA-based network data processing module (1), the data interface module (2) and the storage module (3) to provide reference clocks for various chips in each module; the power supply module (5) is connected to the FPGA-based network data processing module (1), the data interface module (2), the storage module (3) and the clock module (4) to supply power to each module. The industrial network data stream can be transmitted between the controllers through the data interface module (2), wherein: The FPGA-based network data processing module (1) is inside the FPGA chip and comprises a data analysis and assembly module (11) and a data calculation and forwarding module (12). The data analysis and assembly module (11) and the data calculation and forwarding module (12) are connected to each other through a FIFO formed by a G-bit transceiver and a logic unit inside the FPGA chip, thereby realizing network data processing in accordance with the TTP protocol; The data interface module (2) is outside the FPGA chip and comprises a PHY chip (21), an RJ45 socket (22) and a 10G SFP+ optical port (23); the PHY chip (21) is connected to the RJ45 socket (22) and the FPGA-based network data processing module (1) to realize the transmission and reception of 10 / 100 / 1000M network data packets; the 10G SFP+ optical port (23) is connected to the FPGA-based network data processing module (1) to realize the transmission and reception of 10G optical network data packets; The storage module (3) is outside the FPGA chip and includes a DDR3 cache module (31) and a FLASH memory (32); the DDR3 cache module (31) is connected to the FPGA-based network data processing module (1) to provide a cache for the FPGA chip when processing a large amount of high-speed network data; the FLASH memory (32) is connected to the FPGA-based network data processing module (1) to be used for program curing and burning of the FPGA chip; The clock module (4) is outside the FPGA chip and is provided with a clock frequency multiplication module (41) for generating a clock source required for the normal operation of the FPGA chip and the TTP protocol.

2. The industrial network controller architecture for implementing the TTP protocol based on programmable logic according to claim 1, characterized in that: The data analysis and assembly module (11) in the FPGA-based network data processing module (1) performs data unpacking and packet assembly according to the TTP frame format; the data calculation and forwarding module (12) can process the unpacked application data information and forward the data packet to the corresponding node in a specified time slot according to the TTP protocol and TDMA concept.

3. The industrial network controller architecture for implementing the TTP protocol based on programmable logic according to claim 1, characterized in that: The data interface module (2) provides 12 independent 10 / 100 / 1000M Ethernet interfaces consisting of a PHY chip (21) and an RJ45 socket (22); and provides 8 independent 10G SFP+ optical ports (23); the data interface module can provide a total throughput of 133.92Mpps.

4. The industrial network controller architecture for implementing the TTP protocol based on programmable logic according to claim 1, characterized in that: The DDR3 cache module (31) in the storage module (3) uses four 2Gb 16bit DDR3 chips with a maximum rate of 1600MT / s; the FLASH memory (32) is used to configure the TTP protocol corresponding program of the FPGA chip. The single-chip capacity of the FLASH memory is 1Gb, and the total capacity of two chips is 2Gb.

5. The industrial network controller architecture for implementing the TTP protocol based on programmable logic according to claim 1, characterized in that: The clock frequency multiplication module (41) in the clock module (4) uses a chip HMC7044, which is used to provide different reference clocks required for the FPGA chip to run the TTP protocol program.

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