Groove type SiC MOSFET device based on symmetrical split gate structure and preparation method

Abstract

The invention discloses a groove type SiC MOSFET device based on a symmetrical split gate structure and a preparation method, in the groove type SiC MOSFET device designed by the invention, an inverted T type P + shielding layer is designed to realize direct contact between the P + shielding layer and a source electrode, and meanwhile, split gate structures which are symmetrical up and down and left and right are designed, so that the overlapping area of a grid electrode and a drain electrode is reduced, the coupling effect between the grid electrode and the drain electrode is reduced, and the reliability of the device is improved. And device switching loss is reduced. In addition, a multi-stage step type current expansion layer is introduced into the groove type SiC MOSFET device, so that the conduction path of electrons is expanded, the electron concentration is increased, and the thermal performance and reliability of the device are improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a trench SiC MOSFET device based on a symmetrical split-gate structure and a preparation method thereof. Background Art

[0002] Compared with silicon materials, silicon carbide (SiC) materials have wider bandgap, higher critical electric field, faster carrier saturation drift velocity and higher thermal conductivity. These superior properties make SiC an ideal material for preparing high-voltage power electronic devices. It is widely used in power electronics fields such as high power, high temperature, high voltage and radiation resistance, showing broad application prospects.

[0003] SiC MOSFET is a gate-controlled device with the characteristics of unipolar transport working mechanism and no charge storage effect. Compared with bipolar devices, it can achieve lower switching losses and higher frequency characteristics. Its low on-resistance and excellent high-temperature characteristics make SiC MOSFET a highly competitive choice in the new generation of low-loss power devices.

[0004] However, the development of trench SiC MOSFET is limited by the process level and gate oxide reliability issues. The formation of the trench has extremely high requirements for the etching process: on the one hand, the etching method affects the roughness of the sidewall surface; on the other hand, the etching angle determines the shape of the channel crystal plane and the gate groove corner, which in turn affects the channel mobility and gate oxide reliability. In the trench SiC MOSFET, the gate groove is located in the withstand voltage drift region. In the blocking state, the electric field concentration phenomenon is prone to occur at the trench corner, making the gate oxide electric field peak far exceed the critical breakdown electric field of the SiO2 material, increasing the risk of premature gate oxide breakdown.

[0005] In order to alleviate the electric field concentration effect at the corner of the trench, a P-type shielding layer is usually introduced at the bottom of the trench after the gate trench is etched. Through this design, the electric field peak is transferred from the gate oxide layer to the PN junction composed of the P-type shielding layer and the N-type drift region when the device breaks down, thereby improving the reliability of the gate oxide. The P-type shielding layer can be floating or grounded. The grounding method can more effectively improve the reliability of the gate oxide, but its process implementation is more difficult. Therefore, how to design a SiC MOSFET structure that can optimize the P-type shielding layer grounding process and ensure high reliability has become an important issue that needs to be solved urgently. Summary of the invention

[0006] In view of the above technical problems, the present invention proposes a trench SiC MOSFET device and a preparation method based on a symmetrical split-gate structure. An inverted T-shaped P+ shielding layer is designed in the MOSFET device to achieve direct contact between the P+ shielding layer and the source. At the same time, a split-gate structure that is symmetrical in both directions is designed to reduce the overlapping area between the gate and the drain, reduce the coupling effect between the two, and reduce the switching loss of the device. In addition, a multi-level current expansion layer is introduced to expand the conduction path of electrons, increase the electron concentration, and improve the thermal performance and reliability of the device.

[0007] To achieve the above object, the technical solution adopted by the present invention is as follows: In a first aspect, the present invention provides a method for preparing a trench SiC MOSFET device based on a symmetrical split-gate structure, comprising: S1. preparing a SiC substrate, growing an epitaxial layer on the surface of the SiC substrate, and forming a P+ shielding layer and a symmetrical current spreading layer in the epitaxial layer; S2, continuing to grow a SiC epitaxial layer on the surface of the epitaxial layer treated by S1, extending the P+ shielding layer by high-energy ion implantation, and generating symmetrical P-well regions, N+ regions and P+ regions on the surface of the current extension layer; S3, etching the P+ shielding layer to form an inverted T structure; S4, depositing oxide and polysilicon in the trench etched in S3 to form a symmetrical split gate and gate; S5. Generate source and drain.

[0008] Preferably, the specific implementation process of S1 includes: Selecting an N-type doped 4H-SiC substrate, and growing an epitaxial layer on the 4H-SiC substrate by MOCVD homoepitaxial growth; After the epitaxial layer is cleaned, coated, photolithographically and developed, high-energy ion implantation is performed symmetrically on the surface of the epitaxial layer to form a symmetrical current spreading layer, and high-energy ion implantation is performed at the center of the surface of the epitaxial layer to form a P+ shielding layer between the symmetrical current spreading layers; The 4H-SiC substrate is doped with nitrogen or phosphorus at a doping concentration of 1×10 18 ~1×10 20 cm -3 , thickness is 10-12 um, width is 2-6 um; The epitaxial layer is N-type doped, the doping element is nitrogen or phosphorus, and the doping concentration is 1×10 15 ~1×10 16 cm -3 , thickness is 6-15 um, width is 2-6 um; The P+ shielding layer is P-type doped, the doping element is aluminum or boron, and the doping concentration is 1×10 19 ~1×10 20 cm -3 , thickness is 0.2-1.5 um, width is 0.2-1.5 um; The current spreading layer is N-type doped, the doping element is nitrogen or phosphorus, and the doping concentration is 1×10 15 ~1×10 17 cm -3 .

[0009] Preferably, the current spreading layer is a step-type current spreading layer, comprising five layers, all of which are N-type doped; The injection method of the current spreading layer is: High-energy ions are symmetrically implanted from the leftmost and rightmost sides of the epitaxial layer surface, and the doping element is nitrogen or phosphorus with a doping concentration of 1×10 15 ~1×10 17 cm -3 , each layer has a thickness of 0.1-0.4 um and a width of 0.1-1 um; During the injection process, from top to bottom, each layer has the same thickness and doping elements, the doping concentration decreases layer by layer, and the width decreases layer by layer, eventually forming a stepped structure.

[0010] Preferably, the specific implementation process of S2 includes: Continue to grow a SiC epitaxial layer by depositing SiC material on the surface of the epitaxial layer treated by S1; Perform cleaning, glue coating, photolithography and development processes, perform high-energy ion implantation from the center point of the surface of the SiC epitaxial layer, and continue to grow a P+ shielding layer; Injecting high-energy ions symmetrically from the leftmost and rightmost sides of the surface of the SiC epitaxial layer to form a P-well region of equal width on the surface of the current spreading layer; Injecting high-energy ions symmetrically from the leftmost and rightmost sides of the surface of the SiC epitaxial layer to form a P+ region on the surface of the P-well region; High-energy ions are symmetrically injected from the edge of the P+ region on the surface of the SiC epitaxial layer to form an N+ region on the surface of the P-well region and adjacent to the P+ region, and the total width of the P+ region and the N+ region is the same as the width of the P-well region; The SiC epitaxial layer is doped with nitrogen or phosphorus, and the doping concentration is 1×10 15 ~1×10 16 cm -3 , thickness is 1-3um, width is 2-6 um; The P+ shielding layer that continues to grow is doped with aluminum or boron, with a doping concentration of 1×10 19 ~1×1020 cm -3 , thickness is 0.2-0.5 um; The P-well region is P-type doped, the doping element is aluminum or boron, and the doping concentration is 1×10 18 ~1×10 20 cm -3 , thickness is 0.2-1 um; The P+ region is P-type doped, the doping element is aluminum or boron, and the doping concentration is 1×10 18 ~1×10 20 cm -3 , thickness is 0.2-0.4 um, width is 0.3-0.5 um; The N+ region is N-type doped, the doping element is nitrogen or phosphorus, and the doping concentration is 1×10 18 ~1×10 20 cm -3 , the thickness is consistent with the P+ region, and the width is 0.4-0.7 um.

[0011] Preferably, the specific implementation process of S3 includes: Cleaning, gluing, photolithography and developing the SiC epitaxial layer after S2 treatment, protecting the P+ region, N+ region and the P+ shielding layer that does not need to be etched with photoresist, and then etching the SiC epitaxial layer to form a groove; The groove is etched downward from the surface of the SiC epitaxial layer and located on one side of the N+ region, and the two sides are symmetrical, so that the etched P+ shielding layer forms an inverted T shape; The etched groove width is 0.2-0.4 um and the thickness is 1-2 um.

[0012] Preferably, the specific implementation process of S4 includes: Cleaning, gluing, photolithography and developing the SiC epitaxial layer after S3 treatment; Depositing oxide at the bottom of the groove with a thickness of 0.05-0.1 um; Depositing oxide on the sidewall of the trench with a thickness of 0.05-0.1 um; Depositing polysilicon in the trench with a thickness of 0.3-1 um to form a split gate; Continue to deposit oxide in the groove, with a deposition thickness of 0.05-0.1 um; Performing a second polysilicon deposition in the trench to form a gate with a deposition thickness of 0.6-1 um; Oxide deposition is performed on the gate so that the deposited oxide layer is flush with the surface of the SiC epitaxial layer.

[0013] Preferably, the specific implementation process of S5 includes: Etching the P+ shielding layer to form a source trench; the etching thickness is 0.6-1 um; Depositing a metal layer in the source trench and on the top of the SiC epitaxial layer to form a source; the deposited metal layer has a thickness of 2 um and a size of 2 um×3 um; Metal is deposited on the back side of the SiC substrate to form a drain.

[0014] In a second aspect, the present invention provides a trench SiC MOSFET device based on a symmetrical split-gate structure, which is prepared by using the above-mentioned method for preparing a trench SiC MOSFET device based on a symmetrical split-gate structure.

[0015] The beneficial effects of the present invention are: (1) The present invention provides a trench SiC MOSFET device based on a symmetrical split-gate structure, and designs an inverted T-shaped P+ shielding layer to achieve direct contact between the P+ shielding layer and the source. The grounded P+ shielding layer can promote the expansion of the depletion layer, making the electric field more evenly distributed in the depletion layer, effectively alleviating the electric field concentration effect, and avoiding premature breakdown of the device.

[0016] (2) The trench SiC MOSFET device based on the symmetrical split-gate structure provided by the present invention is designed with a split-gate structure that is symmetrical in both the top and bottom and the left and right directions, thereby reducing the overlapping area between the gate and the drain and reducing the coupling effect between the two, thereby improving the switching speed of the device.

[0017] (3) The trench SiC MOSFET device based on the symmetrical split-gate structure provided by the present invention introduces a multi-level current expansion layer to expand the conduction path of electrons and increase the electron concentration. The current expansion layer can effectively disperse the current, prevent it from concentrating in a specific area, reduce the formation of hot spots, and thus improve the thermal performance and reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a flow chart of manufacturing a trench SiC MOSFET device based on a symmetrical split-gate structure provided by the present invention; Figure 2 It is a schematic structural diagram of a trench SiC MOSFET device based on a symmetrical split-gate structure provided by the present invention after a current spreading layer and a P+ shielding layer are prepared; Figure 3 It is a schematic structural diagram of a trench SiC MOSFET device based on a symmetrical split-gate structure provided by the present invention after preparing a P-well region, an N+ region and a P+ region; Figure 4It is a schematic structural diagram of a trench SiC MOSFET device based on a symmetrical split-gate structure provided by the present invention after preparing an inverted T-shaped P+ shielding layer; Figure 5 It is a schematic structural diagram of a trench SiC MOSFET device based on a symmetrical split-gate structure provided by the present invention after preparing a split-gate; Figure 6 It is a schematic structural diagram of a trench SiC MOSFET device based on a symmetrical split-gate structure provided by the present invention after preparing a gate; Figure 7 It is a schematic structural diagram of a trench SiC MOSFET device based on a symmetrical split-gate structure provided by the present invention after preparing a source electrode; Figure 8 It is a schematic structural diagram of a trench SiC MOSFET device based on a symmetrical split-gate structure provided by the present invention after preparing a drain electrode; Fig. 9 It is a transfer characteristic curve of a trench SiC MOSFET device based on a symmetrical split-gate structure prepared by the present invention; Fig.10 It is the output characteristic curve of the trench SiC MOSFET device based on the symmetrical split-gate structure prepared by the present invention; Fig.11 It is a breakdown characteristic curve of a trench SiC MOSFET device based on a symmetrical split-gate structure prepared by the present invention; Fig.12 It is a capacitance characteristic curve of a trench SiC MOSFET device based on a symmetrical split-gate structure prepared by the present invention. DETAILED DESCRIPTION

[0019] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.

[0020] In the description of the present invention, it should be understood that the terms "upper", "lower", "left", "right", "vertical", "horizontal", etc. indicate positions or positional relationships based on the positions or positional relationships shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific position, be constructed and operated in a specific position, and therefore cannot be understood as limiting the present invention. In the description of the present invention, unless otherwise specified, "plurality" means two or more.

[0021] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0022] Secondly, the term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure or characteristic that may be included in at least one implementation of the present invention. The term "in one embodiment" that appears in different places in this specification does not necessarily refer to the same embodiment, nor does it refer to a separate or selective embodiment that is mutually exclusive with other embodiments.

[0023] The specific embodiments of the present invention are described in further detail below in conjunction with the accompanying drawings. The following examples are used to illustrate the present invention but are not intended to limit the scope of the present invention.

[0024] In a first aspect, the present invention provides a method for preparing a trench SiC MOSFET device based on a symmetrical split-gate structure, see Figure 1 , the method comprising: S100: Prepare a SiC substrate and grow an epitaxial layer on its surface by MOCVD (Metal-organic Chemical Vapor Deposition) homoepitaxial technology; then, form a current spreading layer and a P+ shielding layer in the epitaxial layer by high-energy ion implantation.

[0025] S200: further growing an epitaxial layer by depositing SiC material, extending the P+ shielding layer using high-energy ion implantation technology, and generating a P-well region, an N+ region, and a P+ region.

[0026] S300: etching the P+ shielding layer to form an inverted T structure on the P+ shielding layer.

[0027] S400: depositing an oxide layer on the bottom and sidewall of the etched trench, and filling the trench with polysilicon to form a split gate structure.

[0028] S500: Continue to deposit an oxide layer and polysilicon in the trench, construct a gate, and ensure that the final deposited oxide layer is flush with the surface of the epitaxial layer.

[0029] S600: etching the P+ shielding layer to form a trench, and depositing metal to form a source.

[0030] S700: depositing and connecting a metal layer on the back to form a drain.

[0031] In the present invention, the specific implementation process of step S100 is as follows: S110: Select N-type doped 4H-SiC substrate, the doping element is nitrogen or phosphorus, and the doping concentration is 1×10 18 ~1×10 20 cm -3 The thickness is between 10-12 um and the width is between 2-6 um.

[0032] The epitaxial layer was grown on the 4H-SiC substrate by MOCVD homoepitaxial technology. It should be noted that the epitaxial layer is N-type doped, the doping element is nitrogen or phosphorus, and the doping concentration is 1×10 15 ~1×10 16 cm -3 The thickness of the epitaxial layer is 6-15 um and the width is 2-6 um.

[0033] Preferably, the doping element of the 4H-SiC substrate is nitrogen, and the doping concentration is 1×10 18 cm -3 , the substrate thickness is 10um and the width is 3 um.

[0034] Preferably, the epitaxial layer is doped with nitrogen, and the doping concentration is 6.5×10 15 cm -3 , the epitaxial layer thickness is 11 um and the width is 3 um.

[0035] S120: After the epitaxial layer is cleaned, coated, photolithographically processed and developed, a high-energy ion implantation technique is used to form a stepped current spreading layer and a P+ shielding layer.

[0036] See also Figure 2 In the present invention, the current spreading layer includes five layers, all of which are N-type doped. High-energy ion implantation technology is used to symmetrically implant the doping elements from the leftmost and rightmost sides of the epitaxial layer surface. The doping elements are nitrogen or phosphorus, and the doping concentration is 1×10 15 ~1×10 17 cm -3 , thickness is 0.1-0.4 um, width is 0.1-1 um; and from top to bottom, each layer has the same thickness, the same doping elements, the doping concentration decreases layer by layer, the width decreases layer by layer, and finally forms a stepped structure.

[0037] The details of each layer are as follows: The first layer is symmetrically injected from the left and right sides of the epitaxial layer surface, with nitrogen or phosphorus as the doping element and a doping concentration of 1×10 15 ~1×10 17cm -3 , thickness is 0.1-0.4 um, width is 0.1-1 um. Nitrogen doping is preferred, with a doping concentration of 1×10 17 cm -3 , thickness is 0.15 um and width is 1 um.

[0038] The second layer is symmetrically injected from the left and right sides of the epitaxial layer surface, with nitrogen or phosphorus as the doping element and a doping concentration of 1×10 15 ~1×10 17 cm -3 , thickness is 0.1-0.4 um, width is 0.1-1 um. Nitrogen doping is preferred, with a doping concentration of 7×10 16 cm -3 , thickness is 0.15 um and width is 0.9 um.

[0039] The third layer is symmetrically injected from the left and right sides of the epitaxial layer surface, with nitrogen or phosphorus as the doping element and a doping concentration of 1×10 15 ~1×10 17 cm -3 , thickness is 0.1-0.4 um, width is 0.1-1 um. Nitrogen doping is preferred, with a doping concentration of 9×10 15 cm -3 , thickness is 0.15 um and width is 0.8 um.

[0040] The fourth layer is symmetrically injected from the left and right sides of the epitaxial layer surface, with nitrogen or phosphorus doping elements and a doping concentration of 1×10 15 ~1×10 17 cm -3 , thickness is 0.1-0.4 um, width is 0.1-1 um. Nitrogen doping is preferred, with a doping concentration of 8×10 15 cm -3 , thickness is 0.15 um and width is 0.7 um.

[0041] The fifth layer is symmetrically injected from the left and right sides of the epitaxial layer surface, with nitrogen or phosphorus doping elements and a doping concentration of 1×10 15 ~1×10 17 cm -3 , thickness is 0.1-0.4 um, width is 0.1-1 um. Nitrogen doping is preferred, with a doping concentration of 7×10 15 cm -3 , thickness is 0.15 um and width is 0.6 um.

[0042] See also Figure 2In the present invention, the P+ shielding layer is P-type doped, and high-energy ion implantation technology is used to implant from the center of the epitaxial layer surface. The doping element is aluminum or boron, and the doping concentration is 1×10 19 ~1×10 20 cm -3 , with a thickness of 0.2-1.5 um and a width of 0.2-1.5 um. The edge of the P+ shielding layer contacts the first layer of the current spreading layer on the left and right sides.

[0043] Aluminum is preferably doped, with a doping concentration of 2×10 19 cm -3 , thickness is 1 um and width is 1 um.

[0044] In the present invention, the specific implementation process of step S200 is as follows: S210: A SiC epitaxial layer is further grown on the surface of the epitaxial layer treated by S100 by depositing SiC material. The SiC epitaxial layer is doped with nitrogen or phosphorus at a doping concentration of 1×10 15 ~1×10 16 cm -3 , thickness is 1-3 um, width is 2-6 um.

[0045] Preferably, nitrogen is used for doping, and the doping concentration is 6.5×10 15 cm -3 , thickness is 1 um and width is 3 um.

[0046] S220: After the epitaxial wafer is cleaned, coated, photolithographically processed and developed, high-energy ion implantation technology is used to form a P+ shielding layer, a P-well region (P-well), an N+ region and a P+ region. Among them, the P-well region, the N+ region and the P+ region are all implanted symmetrically.

[0047] See also Figure 3 In the present invention, the P+ shielding layer is P-type doped, and the P+ shielding layer is continuously grown by high-energy ion implantation from the center point of the epitaxial layer surface, and the P+ shielding layer in S100 is extended. The doping element is aluminum or boron, and the doping concentration is 1×10 19 ~1×10 20 cm -3 , with a thickness of 0.2-1 um and a width of 0.2-1.5 um. Preferably, nitrogen is doped with a doping concentration of 2×10 19 cm -3 , thickness is 0.9 um and width is 1 um.

[0048] P well area ( Figure 3The Pwell region in the epitaxial layer is P-type doped. Through high-energy ion implantation technology, symmetrical ion implantation is performed from the leftmost and rightmost sides of the epitaxial layer surface to form a P-well region on the surface of the current spreading layer. The doping element is aluminum or boron, and the doping concentration is 1×10 18 ~1×10 20 cm -3 , with a thickness of 0.2-1 um and a width of 0.8-1 um, which is the same as the width of the first layer of the electron extension layer. Preferably, nitrogen is doped with a doping concentration of 1×10 19 cm -3 , thickness is 0.8 um and width is 1 um.

[0049] P+ zone ( Figure 3 The P Plus region in the epitaxial layer is P-type doped. Through high-energy ion implantation technology, symmetrical implantation is performed from the leftmost and rightmost sides of the epitaxial layer surface to form a P+ region on the surface of the P-well region. The doping element is aluminum or boron, and the doping concentration is 1×10 18 ~1×10 20 cm -3 , with a thickness of 0.2-0.4 um and a width of 0.3-0.5 um. Preferably, aluminum is doped with a doping concentration of 1×10 19 cm -3 , thickness is 0.2 um and width is 0.4 um.

[0050] N+ area ( Figure 2 The N Plus region in the epitaxial layer is N-type doped. High-energy ions are injected symmetrically from the surface of the epitaxial layer near the P+ region to form an N+ region on the surface of the P-well region and adjacent to the P+ region. The doping element is nitrogen or phosphorus, and the doping concentration is 1×10 18 ~1×10 20 cm -3 The thickness is 0.2-0.4 um and is consistent with the thickness of the P+ region, and the total width of the P+ region and the N+ region is the same as the width of the P well region, which is 0.4-0.7 um. Preferably, nitrogen doping is used, and the doping concentration is 1×10 19 cm -3 , thickness is 0.2 um and width is 0.6 um.

[0051] It should be noted that the internal structure and preparation process of epitaxial wafers are common industry standards and there are no special requirements.

[0052] In the present invention, the specific implementation process of step S300 is as follows: First, the epitaxial wafer processed in step S200 is cleaned, coated, photolithographically and developed, the P+ region, N+ region and the P+ shielding layer that does not need to be etched are protected with photoresist, and then the epitaxial layer is etched to form a groove.

[0053] In the present invention, the trench etching is performed downward from the side of the epitaxial layer surface close to the N+ region, and the two sides are symmetrical, so that the P+ shielding layer after etching forms an inverted T shape. Figure 4 As shown. The etched groove width is 0.2-0.4 um, and the thickness is 1-2 um. The preferred etching parameters are 0.4 um in width and 1.8 um in thickness.

[0054] In the present invention, the specific implementation process of step S400 is as follows: The epitaxial wafer processed by S300 is cleaned, coated, photolithographically processed and developed, and then oxide and polysilicon are deposited in the trench to form a split gate structure. Figure 5 shown.

[0055] Specifically, an oxide is deposited at the bottom of the trench with a thickness of 0.05-0.1 um, preferably 0.1 um; Depositing oxide on the trench sidewalls with a thickness of 0.05-0.1 um, preferably 0.05 um; Then, polysilicon (Poly Si) is deposited in the trench with a deposition thickness of 0.3-1 um, preferably 0.6 um, to form a split gate structure.

[0056] In the present invention, the specific implementation process of step S500 is as follows: Oxide deposition is continued in the groove after S400 treatment, and the thickness of the deposited oxide is 0.05-0.1 um, preferably 0.1 um.

[0057] Then a second polysilicon (Poly Si) deposition is performed to form a gate, such as Figure 6 The deposition thickness is 0.6-1 um, and the preferred thickness is 0.9 um.

[0058] Finally, oxide is deposited on the gate to make the deposited oxide layer flush with the surface of the epitaxial layer. Figure 6 shown.

[0059] In the present invention, the specific implementation process of step S600 is as follows: The P+ shielding layer flush with the surface of the epitaxial layer is etched to form a source trench, such as Figure 7 As shown. The etching thickness is 0.6-1 um. The preferred etching thickness is 0.8 um.

[0060] Subsequently, a metal layer with a thickness of 2 um and a size of 2 um × 3 um is deposited in the source trench and on top of the epitaxial layer to form the source. Figure 7 shown.

[0061] In the present invention, the specific implementation process of step S700 is as follows: Metal is deposited on the back of the substrate to form a drain. Figure 8 shown.

[0062] It should be noted that the source electrode is provided with a source ohmic contact metal, and the drain electrode is provided with a drain ohmic contact metal.

[0063] In a second aspect, the present invention provides a trench SiC MOSFET device based on a symmetrical split-gate structure, which is prepared by the above-mentioned preparation method.

[0064] The parameters of the prepared trench SiC MOSFET device are simulated and obtained Figures 9 to 12 ,from Fig. 9 From the transfer characteristic curve of the device, we can see that the threshold voltage of the device is 2.8V. Fig.10 From the device output characteristic curve, we know that the on-resistance is R ON =1.88 mΩ·cm², from Fig.11 From the device breakdown characteristic curve, we can see that the breakdown voltage is 1500V. Fig.12 From the capacitance characteristic curve, we know that the output capacitance is C GD = 2.39E-12 (F / cm 2 ). In general, the overall performance of the structure device is better, which makes the symmetrical split-gate trench SiC MOSFET device significantly competitive among trench MOSFET devices.

[0065] It should be noted that the drawings of the embodiments disclosed in the present invention only involve the structures involved in the embodiments disclosed in the present invention, and other structures may refer to the usual design; in the absence of conflict, the embodiments disclosed in the present invention and the features in the embodiments may be combined with each other to obtain new embodiments.

[0066] The above are only specific implementation modes disclosed in the present invention, but the protection scope of the present invention is not limited thereto. The protection scope disclosed in the present invention shall be based on the protection scope of the claims.

Claims

1. A method for preparing a trench SiC MOSFET device based on a symmetrical split-gate structure, characterized in that: include: S1. preparing a SiC substrate, growing an epitaxial layer on the surface of the SiC substrate, and forming a P+ shielding layer and a symmetrical current spreading layer in the epitaxial layer; S2, continuing to grow a SiC epitaxial layer on the surface of the epitaxial layer treated by S1, extending the P+ shielding layer by high-energy ion implantation, and generating symmetrical P-well regions, N+ regions and P+ regions on the surface of the current extension layer; S3, etching the P+ shielding layer to form an inverted T structure; S4, depositing oxide and polysilicon in the trench etched in S3 to form a symmetrical split gate and gate; S5. Generate source and drain.

2. The method for preparing a trench SiC MOSFET device based on a symmetrical split-gate structure according to claim 1, characterized in that: The specific implementation process of S1 includes: Selecting an N-type doped 4H-SiC substrate, and growing an epitaxial layer on the 4H-SiC substrate by MOCVD homoepitaxial growth; After the epitaxial layer is cleaned, coated, photolithographically and developed, high-energy ion implantation is performed symmetrically on the surface of the epitaxial layer to form a symmetrical current spreading layer, and high-energy ion implantation is performed at the center of the surface of the epitaxial layer to form a P+ shielding layer between the symmetrical current spreading layers; The 4H-SiC substrate is doped with nitrogen or phosphorus at a doping concentration of 1×10 18 ~1×10 20 cm -3 , thickness is 10-12um, width is 2-6 um; The epitaxial layer is N-type doped, the doping element is nitrogen or phosphorus, and the doping concentration is 1×10 15 ~1×10 16 cm -3 , thickness is 6-15 um, width is 2-6 um; The P+ shielding layer is P-type doped, the doping element is aluminum or boron, and the doping concentration is 1×10 19 ~1×10 20 cm -3 , thickness is 0.2-1.5 um, width is 0.2-1.5 um; The current spreading layer is N-type doped, the doping element is nitrogen or phosphorus, and the doping concentration is 1×10 15 ~1×10 17 cm -3 .

3. The method for preparing a trench SiC MOSFET device based on a symmetrical split-gate structure according to claim 2, characterized in that: The current spreading layer is a step-type current spreading layer, including five layers, all of which are N-type doped; The injection method of the current spreading layer is: High-energy ions are symmetrically implanted from the leftmost and rightmost sides of the epitaxial layer surface, and the doping element is nitrogen or phosphorus with a doping concentration of 1×10 15 ~1×10 17 cm -3 , each layer has a thickness of 0.1-0.4 um and a width of 0.1-1 um; During the injection process, from top to bottom, each layer has the same thickness and doping elements, the doping concentration decreases layer by layer, and the width decreases layer by layer, eventually forming a stepped structure.

4. The method for preparing a trench SiC MOSFET device based on a symmetrical split-gate structure according to claim 3, characterized in that: The specific implementation process of S2 includes: Continue to grow a SiC epitaxial layer by depositing SiC material on the surface of the epitaxial layer treated by S1; Perform cleaning, glue coating, photolithography and development processes, perform high-energy ion implantation from the center point of the surface of the SiC epitaxial layer, and continue to grow a P+ shielding layer; Injecting high-energy ions symmetrically from the leftmost and rightmost sides of the surface of the SiC epitaxial layer to form a P-well region of equal width on the surface of the current spreading layer; Injecting high-energy ions symmetrically from the leftmost and rightmost sides of the surface of the SiC epitaxial layer to form a P+ region on the surface of the P-well region; High-energy ions are symmetrically injected from the edge of the P+ region on the surface of the SiC epitaxial layer to form an N+ region on the surface of the P-well region and adjacent to the P+ region, and the total width of the P+ region and the N+ region is the same as the width of the P-well region; The SiC epitaxial layer is doped with nitrogen or phosphorus, and the doping concentration is 1×10 15 ~1×10 16 cm -3 , thickness is 1-3 um, width is 2-6 um; The P+ shielding layer that continues to grow is doped with aluminum or boron, with a doping concentration of 1×10 19 ~1×10 20 cm -3 , thickness is 0.2-0.5 um; The P-well region is P-type doped, the doping element is aluminum or boron, and the doping concentration is 1×10 18 ~1×10 20 cm -3 , thickness is 0.2-1 um; The P+ region is P-type doped, the doping element is aluminum or boron, and the doping concentration is 1×10 18 ~1×10 20 cm -3 , thickness is 0.2-0.4 um, width is 0.3-0.5 um; The N+ region is N-type doped, the doping element is nitrogen or phosphorus, and the doping concentration is 1×10 18 ~1×10 20 cm -3 , the thickness is consistent with the P+ region, and the width is 0.4-0.7 um.

5. The method for preparing a trench SiC MOSFET device based on a symmetrical split-gate structure according to claim 4, characterized in that: The specific implementation process of S3 includes: Cleaning, gluing, photolithography and developing the SiC epitaxial layer after S2 treatment, protecting the P+ region, N+ region and the P+ shielding layer that does not need to be etched with photoresist, and then etching the SiC epitaxial layer to form a groove; The groove is etched downward from the surface of the SiC epitaxial layer and located on one side of the N+ region, and the two sides are symmetrical, so that the etched P+ shielding layer forms an inverted T shape; The etched groove width is 0.2-0.4 um and the thickness is 1-2 um.

6. The method for preparing a trench SiC MOSFET device based on a symmetrical split-gate structure according to claim 5, characterized in that: The specific implementation process of S4 includes: Cleaning, gluing, photolithography and developing the SiC epitaxial layer after S3 treatment; Depositing oxide at the bottom of the groove with a thickness of 0.05-0.1 um; Depositing oxide on the sidewall of the trench with a thickness of 0.05-0.1 um; Depositing polysilicon in the trench with a thickness of 0.3-1 um to form a split gate; Continue to deposit oxide in the groove, with a deposition thickness of 0.05-0.1 um; Performing a second polysilicon deposition in the trench to form a gate with a deposition thickness of 0.6-1 um; Oxide deposition is performed on the gate so that the deposited oxide layer is flush with the surface of the SiC epitaxial layer.

7. The method for preparing a trench SiC MOSFET device based on a symmetrical split-gate structure according to claim 6, characterized in that: The specific implementation process of S5 includes: Etching the P+ shielding layer to form a source trench; the etching thickness is 0.6-1 um; Depositing a metal layer in the source trench and on the top of the SiC epitaxial layer to form a source; the deposited metal layer has a thickness of 2 um and a size of 2 um×3 um; Metal is deposited on the back side of the SiC substrate to form a drain.

8. A trench SiC MOSFET device based on a symmetrical split-gate structure, characterized in that: The device is manufactured by the method for manufacturing a trench SiC MOSFET device based on a symmetrical split-gate structure according to any one of claims 1 to 7.

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