Super junction trench MOSFET structure and manufacturing method thereof

Abstract

The invention discloses a super-junction trench MOSFET structure and a manufacturing method thereof, and belongs to the technical field of super-junction MOSFETs, and the super-junction trench MOSFET structure comprises an N + substrate, a first cellular structure and a second cellular structure. Wherein the first cellular structure and the second cellular structure are both in a regular hexagon shape; the first cell structure comprises a first N column region and a first P column region surrounding the first N column region, and a first source groove is formed in the first N column region; the second cellular structure comprises a second N column region and a second P column region surrounding the second N column region, and a second source groove is formed in the second N column region; the plurality of second cellular structures surround the first cellular structures; the second cellular structure further comprises a gate groove, a first channel is formed between the gate groove and the first source groove, a second channel is formed between the gate groove and the second source groove, and the length of the first channel is different from that of the second channel. According to the invention, by arranging the regularly hexagonal densely laid cellular structure and having the asymmetric double channels, the channel density is improved, and a good gate oxide protection effect is also provided.

Description

Technical Field

[0001] The present invention belongs to the technical field of super junction MOSFET, and in particular relates to a super junction trench MOSFET structure and a manufacturing method thereof. Background Art

[0002] In recent years, with the rapid development of new energy technologies and electric vehicles, higher requirements have been put forward for loss control and efficiency improvement of power electronic equipment. As an important component of power electronic equipment, power MOSFET devices have received extensive attention in the industry.

[0003] After long-term research, MOSFET power devices have made great progress, and the performance of conventional devices has approached its one-dimensional theoretical limit. However, how to break this limit and further reduce the device's specific on-resistance and conduction loss is a huge challenge facing current MOSFET power devices.

[0004] Among many technologies, superjunction technology is considered to be one of the mature technologies that breaks through the one-dimensional theoretical performance limit of unipolar devices. Superjunction technology breaks the original shackles of the on-resistance and breakdown voltage of silicon-based devices by optimizing the device structure design, significantly improves the conduction performance of the device, and successfully realizes industrialization and promotion and application.

[0005] For example, the Chinese patent with publication number CN117293181A discloses a floating junction type super junction MOSFET structure and a manufacturing method thereof, which includes: a first dielectric layer, a stacked structure, a sidewall region, a current diffusion region, a channel region, a source contact region, a gate structure and a first connection region; the first dielectric layer has a first doping type; the stacked structure extends into the first dielectric layer, the stacked structure includes a plurality of doping regions stacked in sequence along the extension direction, two adjacent doping regions have different doping types, and the outermost doping region in the stacked structure has a second doping type; the sidewall region extends into the first dielectric layer and is used to separate the dielectric layer and the stacked structure; the current diffusion region, the channel region and the source contact region are stacked in sequence on the first dielectric layer; the first connection region runs through the source contact region, the channel region and the current diffusion region. This type of floating junction type super junction MOSFET structure can obtain a low-cost, high charge balance window super junction device.

[0006] However, although superjunction technology has made significant progress and reduced the epitaxial resistance of MOSFET devices, MOSFET devices still have a large channel resistance and their channel density still has a lot of room for improvement.

[0007] Therefore, it is urgent to develop a super junction trench MOSFET structure and a manufacturing method thereof to solve the problems in the prior art. Summary of the invention

[0008] The present invention aims to provide a super junction trench MOSFET structure and a manufacturing method thereof, which have a higher channel density to solve the problem that the channel density of the super junction MOSFET is not high enough.

[0009] In order to solve the above technical problems, the specific technical solutions of the present invention are as follows:

[0010] A super junction trench MOSFET structure, comprising N + Substrate and densely laid on the N + A first cellular structure and a second cellular structure on a substrate; wherein the first cellular structure and the second cellular structure are both regular hexagonal in shape when viewed from above;

[0011] The first cell structure includes a first N column region and a first P column region surrounding the first N column region, and a first source groove is disposed on the first N column region;

[0012] The second cell structure includes a second N column region and a second P column region surrounding the second N column region, and a second source groove is arranged on the second N column region; the second cell structure is arranged in a plurality, and the plurality of second cell structures surround the first cell structure;

[0013] The second cell structure further includes a gate groove, which surrounds the second source groove, a first channel is formed between the gate groove and the first source groove, a second channel is formed between the gate groove and the second source groove, and the first channel and the second channel have different lengths.

[0014] Furthermore, the super junction trench MOSFET structure includes at least one cell, and one cell includes one cell first structure and six cell second structures; when there are multiple cells, two adjacent cells share two cell second structures.

[0015] Furthermore, when there are a plurality of cells, at least one cell second structure is shared by three cell first structures.

[0016] Furthermore, the length of the first channel is greater than the length of the second channel; one side of the gate groove is disposed on the second P column region, and the other side is disposed on the second N column region.

[0017] Furthermore, the first N column region, the first P column region, the second N column region and the second P column region are arranged in the N + The upper surface of the substrate.

[0018] Furthermore, the N + An N-type epitaxial layer is also disposed on the upper surface of the substrate, and the first N-column region, the first P-column region, the second N-column region and the second P-column region are disposed on the upper surface of the N-type epitaxial layer.

[0019] Further, a first P-well is formed between the first source groove and the gate groove, the first P-well surrounds the first source groove, and the first P-well is a hollow regular hexagon in a top view;

[0020] The first P well is formed with a surface P + Area and First N + , the surface P + The first N + Surrounding the surface P + area, the surface P + The area is a hollow regular hexagon in top view, and the first N + It also appears as a hollow regular hexagon when viewed from above;

[0021] A second P-well is disposed between the second source groove and the gate groove, the second P-well surrounds the second source groove, and the second P-well is a hollow regular hexagon in a top view;

[0022] The upper surface of the second P well is also formed with a second N + , the second N + Surrounding the second source slot, the second N + It also appears as a hollow regular hexagon when viewed from above;

[0023] A gate oxide layer is arranged in the gate groove, and the gate oxide layer is arranged at the bottom of the gate groove, a side close to the first source groove, and a side close to the second source groove.

[0024] A method for manufacturing a super junction trench MOSFET structure comprises the following steps:

[0025] In N + An N-type epitaxial layer and a P-type epitaxial layer are constructed on the substrate to form a P column region and a plurality of N column regions; wherein the shape of the N column region in a top view is a regular hexagon, and the P column region surrounds each of the N column regions;

[0026] constructing a PW channel region and a source contact region on the N column region and the P column region;

[0027] A first source trench, a second source trench and a gate trench are constructed; wherein the N column region includes a first N column region and a second N column region; the first source trench is arranged in the first N column region, and the second source trench is arranged in the second N column region; one side of the gate trench is arranged in the second N column region, and the other side is arranged in the P column region, the gate trench runs through the PW channel region, and the distance between the gate trench and the first source trench is greater than the distance between the second source trench and the gate trench.

[0028] Further, the +An N-type epitaxial layer and a P-type epitaxial layer are constructed on a substrate to form a P column region and a plurality of N column regions, including the following steps:

[0029] In N + An N-type epitaxial layer is constructed on the substrate; the N-type epitaxial layer has electronic type doping;

[0030] Constructing a first trench in the N-type epitaxial layer, wherein the first trench penetrates or does not penetrate the N-type epitaxial layer, so that the N-type epitaxial layer forms a plurality of N column regions having a regular hexagonal shape in top view;

[0031] A P-type epitaxial layer is formed in the first trench, the first trench is filled with the P-type epitaxial layer without voids, and the P-type epitaxial layer has hole-type doping.

[0032] Furthermore, the construction of the first source trench, the second source trench and the gate trench comprises the following steps:

[0033] Selecting the location of the first N column region;

[0034] Selecting a position of a second N column region according to a position of the first N column region;

[0035] According to the position of the first N column region, constructing a first source trench;

[0036] According to the position of the second N column region, construct a second source trench and a gate trench;

[0037] The super junction trench MOSFET structure includes at least one cell; when there are several cells, one cell includes one first N column region and six second N column regions, and two adjacent cells share two second N column regions.

[0038] Furthermore, the construction of the PW channel region and the source contact region on the N column region and the P column region comprises the following steps:

[0039] Through two ion implantation processes, a PW channel region and a source contact region are formed on the P column region and the N column region in sequence, wherein the PW channel region is hole-type doped with a medium concentration, and the source contact region is electron-type doped with a high concentration.

[0040] The present invention has the following advantages:

[0041] 1) In the asymmetric source trench regular hexagonal super junction trench MOSFET structure of the present application, since the projections of the first cell structure and the second cell structure on the top view are regular hexagonal and have asymmetric double channels. Compared with the super junction MOSFET of the traditional strip cell, the present invention has a higher channel density. Based on the calculation of the minimum cell unit of the present design and the reference of the conventional MOSFET design line width, assuming that the side length of the regular hexagonal cell is L, the theoretical calculation shows that the channel length per unit area of ​​the present design is: .

[0042] Under the same process conditions, the equivalent cell width of the conventional strip cell is , the channel length per unit area of ​​the strip cell is: .

[0043] It can be seen that the present invention is expected to increase the channel density of super junction MOSFET by 66.7%.

[0044] 2) In the superjunction trench MOSFET structure of the present application, due to the matching design of the superjunction and MOSFET, and the asymmetric channel design, the peak of the trench gate oxide electric field is located inside the P region of the superjunction. This is conducive to reducing the gate oxide electric field, thereby achieving gate oxide protection, improving the reliability of the gate oxide of the superjunction trench MOSFET device, and solving the gate bias reliability problem of silicon carbide MOSFET devices.

[0045] Other features and advantages of the present invention will be disclosed in detail in the following specific embodiments and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 It is a partial structural cross-sectional view of the first embodiment;

[0047] Figure 2 It is a top view of the cell structure of Example 1;

[0048] Figure 3 It is a cross-sectional view of the AA' structure of the first embodiment;

[0049] Figure 4 This is a cross-sectional view of the structure after the N-type epitaxial layer is constructed in Example 1;

[0050] Figure 5 This is a cross-sectional view of the structure after the first groove is constructed in Embodiment 1;

[0051] Figure 6 This is a cross-sectional view of the structure after constructing the P-type epitaxial layer in Embodiment 1;

[0052] Figure 7 It is a cross-sectional view of the structure after constructing the PW channel region and the source contact region in the first embodiment;

[0053] Figure 8 This is a cross-sectional view of the structure after the groove is constructed in Example 1;

[0054] Fig. 9 A cross-sectional view of the structure after the first source trench and the second source trench are constructed in Embodiment 1;

[0055] Fig.10 This is a cross-sectional view of the structure after the gate trench is constructed in Embodiment 1;

[0056] Fig.11 This is a cross-sectional view of the structure after the first groove is constructed in Example 2.

[0057] Description of symbols in the figure: 1, N + Substrate; 2, second N column region; 3, P column region; 4, first N column region; 51, first P well; 52, second P well; 6, surface P + Area; 71, First N + Area; 72, second N + Region; 8, gate oxide layer; 9, second P + Area; 10, first P + Region; 101, N-type epitaxial layer; 102, PW channel region; 103, source contact region. DETAILED DESCRIPTION

[0058] In order to better understand the purpose, structure and function of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings.

[0059] A superjunction trench MOSFET structure, such as Figures 1 to 3 As shown, including:

[0060] N + Substrate 1;

[0061] The first cellular structure is arranged in the N + On substrate 1;

[0062] The second cellular structure is arranged in the N + On the substrate 1, a plurality of the second cellular structures are arranged;

[0063] The first cellular structure is connected to the second cellular structure; the first cellular structure and the second cellular structure are both regular hexagonal in top view; six second cellular structures surround one first cellular structure. Optionally, at least two second cellular structures are arranged next to one first cellular structure.

[0064] In this embodiment, the first cellular structure includes:

[0065] The first N column region 4 is arranged on the N + On the upper surface of the substrate 1, the first N column region 4 is arranged in the middle of the horizontal cross section of the first structure of the unit cell; the shape of the first N column region 4 in the top view is a regular hexagon;

[0066] A first P column region is disposed in the N +On the upper surface of the substrate 1, the first P column region surrounds the first N column region 4; the shape of the first P column region in a top view is a regular hexagon;

[0067] The first source groove is arranged on the first N column region 4. A groove is opened on the first N column region 4. A first P + Area 10: The shape of the first source groove in top view is a regular hexagon.

[0068] In this embodiment, the second cellular structure includes:

[0069] The second N column region 2 is arranged on the N + On the upper surface of the substrate 1, the second N column region 2 is arranged in the middle of the horizontal cross section of the second structure of the unit cell; the shape of the second N column region 2 in the top view is a regular hexagon;

[0070] A second P column region is disposed on the N + On the upper surface of the substrate 1, the second P column region surrounds the second N column region 2; the shape of the second P column region in a top view is a regular hexagon; in this embodiment, the second P column region and the first P column region are an integrated structure and made of the same material, and the second P column region and the first P column region together constitute a P column region 3;

[0071] The second source groove is arranged on the second N column region 2, a groove is opened on the second N column region 2, and a second P + Area 9; the shape of the second source groove in top view is a regular hexagon;

[0072] A gate groove, the gate groove surrounds the second source groove, a first channel is formed between the gate groove and the first source groove, a second channel is formed between the gate groove and the second source groove, and the first channel and the second channel have different lengths; the gate groove is a regular hexagon in a top view. In this embodiment, the length of the first channel refers to the distance between the first source groove and the gate groove, and the length of the second channel refers to the distance between the second source groove and the gate groove.

[0073] A gate oxide layer 8 is provided in the gate groove, and the gate oxide layer 8 is provided at the bottom of the gate groove, a side close to the first source groove, and a side close to the second source groove. The gate oxide layer 8 covers the bottom of the gate groove, and the second source groove is surrounded by a side wall of the gate oxide layer 8. When six cellular second structures are surrounded by the regular hexagonal cellular first structure, the first source groove is also surrounded by the other side wall of the gate oxide layer 8. In this embodiment, a second N+ region 72, a second P well 52, and a second N column region 2 are provided between the gate oxide layer 8 and the second source groove, and a first N+ region 71, a surface P+ region 6, a first P well 51, a first P column region, and a first N column region 4 are provided between the gate oxide layer 8 and the first source groove.

[0074] A first P well 51 is disposed between the first source groove and the gate groove. The first P well 51 surrounds the first source groove and is a hollow regular hexagon in a top view. Specifically, in this embodiment, the hollow regular hexagon refers to a regular hexagon hollowed out at the center of the regular hexagon. The first P well 51 is used to form a first channel.

[0075] The vertical cross section through the center point of the first P well 51 is a hollow convex shape, and the top view thereof is a hollow regular hexagon. + Zone 6 and the first N + Area 71, the surface P + Region 6 surrounds the upper end of the first P well 51, and the first N + The region 71 surrounds the surface P + Zone 6, the surface P + Area 6 is a hollow regular hexagon in top view, and the first N + The area 71 is also a hollow regular hexagon when viewed from above.

[0076] A second P-well 52 is disposed between the second source groove and the gate groove, the second P-well 52 surrounds the second source groove, and the second P-well 52 is a hollow regular hexagon in a top view. The second P-well 52 is used to form a second channel.

[0077] The second P well 52 also has a second N + Area 72, the second N + Region 72 surrounds the second source groove, the second N + The area 72 is also a hollow regular hexagon when viewed from above.

[0078] The super junction trench MOSFET structure includes at least one cell, and one cell includes one cell first structure and six cell second structures; when there are multiple cells, two adjacent cells share two cell second structures. Preferably, at least one cell second structure is shared by three cell first structures.

[0079] Specifically, the setting to realize at least one cellular second structure being shared by three cellular first structures is as follows:

[0080] Six second cellular structures are densely packed around a first cellular structure; the distance between two adjacent first cellular structures is the side length of a second cellular structure. The present application saves manufacturing costs by sharing the second cellular structure.

[0081] In this embodiment, the first cellular structure is symmetrical about the central axis, and the second cellular structure is also symmetrical about the central axis, so that the second cellular structure can be shared by different first cellular structures.

[0082] A method for manufacturing a super junction trench MOSFET structure, such as Figures 4 to 10 , including the following steps:

[0083] S1: In N + An N-type epitaxial layer 101 and a P-type epitaxial layer are constructed on the substrate 1 to form a P column region 3 and a plurality of N column regions; wherein the shape of the N column region in a top view is a regular hexagon, and the P column region 3 surrounds each of the N column regions;

[0084] S2: constructing a PW channel region 102 and a source contact region 103 on the N column region and the P column region 3;

[0085] S3: construct a first source trench, a second source trench and a gate trench; wherein the N column region includes a first N column region 4 and a second N column region 2; the first source trench is arranged in the first N column region 4, and the second source trench is arranged in the second N column region 2; one side of the gate trench is arranged in the second N column region 2, and the other side is arranged in the P column region 3, and runs through the PW channel region 102, and the distance between the gate trench and the first source trench is greater than the distance between the second source trench and the gate trench, so as to form an asymmetric bilateral channel region and a channel region.

[0086] like Figure 4 , Figure 5 and Figure 6 As shown, in this embodiment, S1 includes the following steps:

[0087] In N + An N-type epitaxial layer 101 is constructed on the substrate 1; the N-type epitaxial layer 101 has electronic doping; the thickness of the N-type epitaxial layer 101 is 5 μm-60 μm;

[0088] constructing a first trench in the N-type epitaxial layer 101, wherein the first trench penetrates the N-type epitaxial layer 101;

[0089] A P-type epitaxial layer is formed in the first trench, and the first trench needs to be filled with the P-type epitaxial layer without voids, and the P-type epitaxial layer has hole-type doping.

[0090] like Figure 7 As shown, in this embodiment, S2 includes the following steps:

[0091] Through two ion implantation processes, a PW channel region 102 and a source contact region 103 are formed successively. The PW channel region 102 is designed to be a medium-concentration hole-type doping according to threshold and mobility requirements; the source contact region 103 is designed to be a high-concentration electron-type doping according to ohmic contact requirements.

[0092] like Figure 8 , Fig. 9 and Fig.10 As shown, in this embodiment, S3 includes the following steps:

[0093] Through the etching process, a first source trench, a second source trench and a gate trench are formed simultaneously, wherein the first source trench and the second source trench are located in the N-type epitaxial layer 101; one side of the gate trench is located in the N-type epitaxial layer 101, and the other side is located in the P column region 3, and the gate trench needs to penetrate the PW channel region 102 to form an asymmetric bilateral channel region and a channel region.

[0094] Through the ion implantation process, the surface P + Region 6, P inside the first source trench and the second source trench + Among them, the surface P + Region 6 realizes the grounding of the super junction P column region 3. The second source trench and the P + The P column region 3 protects the gate oxide at the first channel.

[0095] By thermal oxidation / deposition, etc., a gate oxide layer 8 is filled in the gate trench. According to the requirements of threshold voltage and mobility, the thickness of the gate oxide layer 8 is 30nm-150nm. Optionally, the construction process of the first source trench, the second source trench and the gate trench can all be prior art, and this application will not repeat them.

[0096] Optionally, the preparation of the super junction trench MOSFET structure further comprises the following steps:

[0097] A phosphorus-doped polysilicon layer is filled inside the gate trench to serve as the gate of the MOSFET. An interlayer dielectric is covered on the surface of the phosphorus-doped polysilicon layer to achieve gate-source isolation. A source metal is filled inside the source trench to form a source ohmic contact alloy. A thick metal and passivation layer are formed on the front of the device to complete the front process of the device. Finally, thinning and ohmic contact processes are performed on the back of the device to complete the asymmetric source trench regular hexagonal super junction trench MOSFET structure.

[0098] A regular hexagonal cell superjunction structure in which the N column region is surrounded by the P column region 3 is used. A gate trench is etched on the superjunction P column region 3, and one side of the gate trench is located at the center of the superjunction P column region 3, and the other side is located at the superjunction N column region. A source trench is etched on the top of the superjunction N column region, and ions are implanted in the trench to form a P + Inject surface P into one side of the top gate trench of super junction P column region 3. + Area 6. Where surface P + After forming an ohmic contact, region 6 realizes grounding to the super junction P column region 3, and the gate oxide on one side of the gate trench is protected by the super junction P column region 3, and the other side is protected by the source trench, thereby improving the reliability of the gate oxide of the super junction trench MOSFET device.

[0099] Compared with the prior art, the technical solution provided by the present invention has the following beneficial effects:

[0100] 1) In the asymmetric source trench regular hexagonal super junction trench MOSFET structure, since the cell arrangement is a regular hexagon and has an asymmetric double channel. Compared with the super junction MOSFET of the traditional strip cell, the present invention has a higher channel density. Based on the calculation of the minimum cell unit of this design and the reference of the conventional MOSFET design line width, assuming that the side length of the regular hexagonal cell is L, the theoretical calculation shows that the channel length per unit area of ​​this design is: .

[0101] Under the same process conditions, the equivalent cell width of the conventional strip cell is , the channel length per unit area of ​​the strip cell is: .

[0102] It can be seen that the present invention is expected to increase the channel density of super junction MOSFET by 66.7%.

[0103] 2) In the asymmetric source trench regular hexagonal superjunction trench MOSFET structure, due to the matching design of the superjunction and MOSFET, and the asymmetric channel design, the trench gate oxide electric field peak is located inside the P region of the superjunction. This is conducive to reducing the gate oxide electric field, thereby achieving gate oxide protection and improving the reliability of the gate oxide of the superjunction trench MOSFET device.

[0104] Embodiment 2

[0105] The difference between this embodiment and the first embodiment is that the N + An N-type epitaxial layer is also disposed on the upper surface of the substrate 1 , and the first N-column region 4 , the first P-column region, the second N-column region 2 and the second P-column region are disposed on the upper surface of the N-type epitaxial layer.

[0106] In this embodiment, the preparation of the super junction trench MOSFET structure includes the following steps:

[0107] S1: In N + An N-type epitaxial layer and a P-type epitaxial layer are constructed on the substrate 1 to form a P column region and a plurality of N column regions; wherein the shape of the N column region in a top view is a regular hexagon, and the P column region surrounds each of the N column regions;

[0108] S2: constructing a PW channel region and a source contact region on the N column region and the P column region;

[0109] S3: construct a first source trench, a second source trench and a gate trench; wherein the N column region includes a first N column region 4 and a second N column region 2; the first source trench is arranged in the first N column region 4, and the second source trench is arranged in the second N column region 2; one side of the gate trench is arranged in the second N column region 2, and the other side is arranged in the P column region, and runs through the PW channel region, and the distance between the gate trench and the first source trench is greater than the distance between the second source trench and the gate trench, so as to form an asymmetric bilateral channel region and a channel region.

[0110] Among them, Fig.11 As shown, the S1 includes the following steps:

[0111] In N + An N-type epitaxial layer is constructed on the substrate 1; the N-type epitaxial layer has electronic type doping;

[0112] constructing a first trench in the N-type epitaxial layer, wherein the first trench does not penetrate the N-type epitaxial layer;

[0113] A P-type epitaxial layer is formed in the first trench, and the first trench needs to be filled with the P-type epitaxial layer without voids, and the P-type epitaxial layer has hole-type doping.

[0114] It is to be understood that the present invention is described by some embodiments, and it is known to those skilled in the art that various changes or equivalent substitutions may be made to these features and embodiments without departing from the spirit and scope of the present invention. In addition, under the teachings of the present invention, these features and embodiments may be modified to adapt to specific circumstances and materials without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited by the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are within the scope of protection of the present invention.

[0115] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

Claims

1. A super junction trench MOSFET structure, characterized in that: Including N + The substrate is provided in the N + A first cellular structure and a second cellular structure on a substrate; wherein the first cellular structure and the second cellular structure are both regular hexagonal in shape when viewed from above; The first unit cell structure includes a first N column region and a first P column region surrounding the first N column region, and a first source groove is disposed on the first N column region; The second cellular structure includes a second N column region and a second P column region surrounding the second N column region, and a second source groove is arranged on the second N column region; the second cellular structure is arranged in a plurality, and the plurality of second cellular structures surround the first cellular structure; The second cell structure further includes a gate groove, which surrounds the second source groove, a first channel is formed between the gate groove and the first source groove, a second channel is formed between the gate groove and the second source groove, and the first channel and the second channel have different lengths.

2. The super junction trench MOSFET structure according to claim 1, characterized in that: The super junction trench MOSFET structure includes at least one cell, and one cell includes one cell first structure and six cell second structures; when there are multiple cells, two adjacent cells share two cell second structures.

3. The super junction trench MOSFET structure according to claim 2, characterized in that: When there are a plurality of cells, at least one cell second structure is shared by three cell first structures.

4. The super junction trench MOSFET structure according to any one of claims 1 to 3, characterized in that: The length of the first channel is greater than the length of the second channel; one side of the gate groove is arranged on the second P column region, and the other side is arranged on the second N column region.

5. The super junction trench MOSFET structure according to claim 4, characterized in that: The first N column region, the first P column region, the second N column region and the second P column region are arranged in the N + The upper surface of the substrate.

6. The super junction trench MOSFET structure according to claim 4, characterized in that: The N + An N-type epitaxial layer is also disposed on the upper surface of the substrate, and the first N-column region, the first P-column region, the second N-column region and the second P-column region are disposed on the upper surface of the N-type epitaxial layer.

7. The super junction trench MOSFET structure according to claim 5 or 6, characterized in that: A first P-well is formed between the first source groove and the gate groove, the first P-well surrounds the first source groove, and the first P-well is a hollow regular hexagon in a top view; The first P well is formed with a surface P + Area and First N + , the surface P + The first N + Surrounding the surface P + area, the surface P + The area is a hollow regular hexagon in top view, and the first N + It also appears as a hollow regular hexagon when viewed from above; A second P-well is disposed between the second source groove and the gate groove, the second P-well surrounds the second source groove, and the second P-well is a hollow regular hexagon in a top view; The upper surface of the second P well is also formed with a second N + , the second N + Surrounding the second source slot, the second N + It also appears as a hollow regular hexagon when viewed from above; A gate oxide layer is arranged in the gate groove, and the gate oxide layer is arranged at the bottom of the gate groove, a side close to the first source groove, and a side close to the second source groove.

8. A method for manufacturing a super junction trench MOSFET structure, characterized in that: The steps include: In N + An N-type epitaxial layer and a P-type epitaxial layer are constructed on the substrate to form a P column region and a plurality of N column regions; wherein the shape of the N column region in a top view is a regular hexagon, and the P column region surrounds each of the N column regions; constructing a PW channel region and a source contact region on the N column region and the P column region; A first source trench, a second source trench and a gate trench are constructed; wherein the N column region includes a first N column region and a second N column region; the first source trench is arranged in the first N column region, and the second source trench is arranged in the second N column region; one side of the gate trench is arranged in the second N column region, and the other side is arranged in the P column region, the gate trench runs through the PW channel region, and the distance between the gate trench and the first source trench is greater than the distance between the second source trench and the gate trench.

9. The method for manufacturing a super junction trench MOSFET structure according to claim 8, characterized in that: The N + An N-type epitaxial layer and a P-type epitaxial layer are constructed on a substrate to form a P column region and a plurality of N column regions, including the following steps: In N + An N-type epitaxial layer is constructed on the substrate; the N-type epitaxial layer has electronic type doping; Constructing a first trench in the N-type epitaxial layer, wherein the first trench penetrates or does not penetrate the N-type epitaxial layer, so that the N-type epitaxial layer forms a plurality of N column regions having a regular hexagonal shape in top view; A P-type epitaxial layer is formed in the first trench, the first trench is filled with the P-type epitaxial layer without voids, and the P-type epitaxial layer has hole-type doping.

10. The method for manufacturing a super junction trench MOSFET structure according to claim 8, characterized in that: The construction of the first source trench, the second source trench and the gate trench comprises the following steps: Selecting the location of the first N column region; Selecting a position of a second N column region according to a position of the first N column region; According to the position of the first N column region, constructing a first source trench; According to the position of the second N column region, construct a second source trench and a gate trench; The super junction trench MOSFET structure includes at least one cell; when there are several cells, one cell includes one first N column region and six second N column regions, and two adjacent cells share two second N column regions.

11. The method for manufacturing a super junction trench MOSFET structure according to claim 8, characterized in that: The construction of the PW channel region and the source contact region on the N column region and the P column region comprises the following steps: Through two ion implantation processes, a PW channel region and a source contact region are formed on the P column region and the N column region in sequence, wherein the PW channel region is hole-type doped with a medium concentration, and the source contact region is electron-type doped with a high concentration.

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