Flash memory structure and forming method thereof

Abstract

The invention discloses a flash memory structure and a forming method thereof. The structure comprises a substrate; the two storage gate structures are located on the substrate and are separated from each other, an opening is formed between the two storage structures, each storage gate structure comprises a floating gate, a control gate dielectric layer located on the floating gate and a control gate located on the control gate dielectric layer, each floating gate is provided with a first side wall exposed by the opening, and each control gate is provided with a second side wall exposed by the opening. The first side wall is of a corrugated structure, the corrugated structure comprises a plurality of protruding parts, the protruding parts are arranged in the direction perpendicular to the surface of the substrate, and the bottom size of each protruding part is larger than the top size of each protruding part; the erasing gate structure is positioned in the opening; the word line structures are located on the two sides of the storage gate structure and the erasing gate structure respectively, and the erasing efficiency of the formed flash memory structure is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a flash memory structure and a forming method thereof. Background Art

[0002] Flash memory is a non-volatile memory that can retain data for a long time even without current supply, that is, data will not be lost even when power is off. Floating gate flash memory is widely used in various embedded electronic products such as financial IC cards, automotive electronics, etc. because it helps save chip area and improve storage integration density.

[0003] The existing floating gate flash memory structure usually includes an erase gate, a control gate, and a floating gate. The control gate is located above the floating gate and is isolated by a dielectric layer. The erase gate is located between two pairs of control gates and floating gates and is a common erase gate. The two word lines are located on both sides of the two pairs of control gates and floating gates and are isolated by a dielectric layer. The oxide layer between the erase gate and the floating gate is a tunnel dielectric layer. The floating gate will extend partly under the erase gate to form an overlapping wrap frame structure (Wrap round). This unique structure can improve the ability and efficiency of erasure. The above structure has the advantages of high reliability, good manufacturing process compatibility, low startup voltage, and prevention of over-erasure.

[0004] However, the erasing capability and efficiency of the existing floating gate flash memory structure need to be further improved. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a flash memory structure and a forming method thereof, so as to improve the performance of the formed flash memory structure.

[0006] In order to solve the above technical problems, the technical solution of the present invention provides a flash memory structure, including: a substrate; two separate storage gate structures located on the substrate, an opening is provided between the two storage structures, each storage gate structure includes a floating gate, a control gate dielectric layer located on the floating gate and a control gate located on the control gate dielectric layer, each floating gate has a first side wall exposed by the opening, the first side wall is a corrugated structure, the corrugated structure includes a plurality of protrusions, the plurality of protrusions are arranged in a direction perpendicular to the surface of the substrate, and the bottom size of the protrusion is larger than the top size; an erase gate structure located in the opening; and word line structures located on both sides of the storage gate structure and the erase gate structure, respectively.

[0007] Optionally, each of the floating gates further has a second side wall opposite to the first side wall; the second side wall has the corrugated structure.

[0008] Optionally, the first sidewall has a third dimension protruding from the surface of the control gate sidewall, the second sidewall has a fourth dimension protruding from the surface of the control gate sidewall, and the third dimension is greater than the fourth dimension.

[0009] Optionally, the difference between the third size and the fourth size ranges from 0 angstroms to 250 angstroms.

[0010] Optionally, there is a groove between adjacent protrusions; the groove has a first size along the surface of the substrate, and the size of the first size ranges from 100 angstroms to 250 angstroms; the groove has a second size in a direction perpendicular to the surface of the substrate, and the size of the second size ranges from 30 angstroms to 250 angstroms.

[0011] Accordingly, the technical solution of the present invention also provides a method for forming a flash memory structure, comprising: providing a substrate; forming a floating gate material layer, a control gate dielectric material layer located on the floating gate material layer, and a control gate material layer located on the control gate dielectric material layer on the surface of the substrate; etching the control gate material layer and the control gate dielectric material layer until the floating gate material layer is exposed, forming two control gate structures on the surface of the floating gate material layer, each of the control gate structures comprising a control gate dielectric layer and a control gate on the control gate dielectric layer, forming the control gate with the control gate material layer, and forming the control gate dielectric layer with the control gate dielectric material layer; and etching the control gate material layer and the control gate dielectric layer on the side of the control gate structure. The invention relates to a method for forming a sidewall structure by forming a sidewall structure with a floating gate material layer; after forming the sidewall structure, etching the floating gate material layer by a Bosch process until the substrate surface is exposed, forming a floating gate with the floating gate material layer, and forming a storage gate structure with the floating gate and the control gate structure, wherein an opening is provided between the two storage gate structures, each of the floating gates has a first sidewall exposed by the opening, the first sidewall is in a corrugated structure, the corrugated structure includes a plurality of protrusions, the plurality of protrusions are arranged in a direction perpendicular to the substrate surface, and the bottom size of the protrusions is larger than the top size; forming an erase gate structure in the opening; and forming a word line structure on the substrate at both sides of the storage gate structure and the erase gate structure.

[0012] Optionally, the Bosch process includes several processing steps, each of which includes: etching the exposed floating gate material layer using various isotropic etching processes to form a groove in the floating gate material layer; after the various isotropic etching processes, performing a passivation process on the surface of the groove to form a protective layer on the side wall of the groove.

[0013] Optionally, the number of times of the treatment process in the Bosch process ranges from 2 times to 100 times.

[0014] Optionally, the process parameters of the isotropic etching process include: the etching gas includes SF6, the gas flow range is 10 ml / min to 250 ml / min, and the RF power range is 200 W to 1000 W.

[0015] Optionally, the process parameters of the passivation process include: the passivation gas includes a gas flow range of 40 ml / min to 130 ml / min, and a radio frequency power range of 200 W to 1000 W.

[0016] Optionally, each of the control gate structures includes a third sidewall and a fourth sidewall opposite to each other, and the third sidewalls of the two control gate structures are adjacent to each other; and the sidewall structure includes a first sidewall located between the third sidewall and the fourth sidewall.

[0017] Optionally, the method for forming the spacer structure includes: forming a first spacer material layer on the surface of the floating gate material layer and the control gate structure; and etching back the first spacer material layer until the floating gate material layer is exposed.

[0018] Optionally, the sidewall structure also includes a second sidewall located on the third sidewall, and the first sidewall is located between the third sidewall and the second sidewall; each floating gate also has a second sidewall opposite to the first sidewall, the first sidewall has a third dimension protruding from the surface of the control gate sidewall, the second sidewall has a fourth dimension protruding from the surface of the control gate sidewall, and the third dimension is larger than the fourth dimension.

[0019] Optionally, the difference between the third size and the fourth size ranges from 0 angstroms to 250 angstroms.

[0020] Optionally, the method for forming the sidewall structure includes: forming a first sidewall material layer on the surface of the floating gate material layer and the control gate structure; etching back the first sidewall material layer until the floating gate material layer is exposed, and forming the first sidewall on the sidewall of the control gate structure; after forming the first sidewall, forming a second sidewall material layer on the surface of the floating gate material layer and the control gate structure; etching back the second sidewall material layer until the surface of the floating gate material layer is exposed, and forming a second sidewall on the sidewall surface of the first sidewall; after forming the second sidewall, forming a mask layer on the surface of the floating gate material layer, the mask layer exposing the second sidewall of the second sidewall; and removing the second sidewall of the second sidewall.

[0021] Optionally, there is a groove between adjacent protrusions; the groove has a first size along the surface of the substrate, and the size of the first size ranges from 100 angstroms to 250 angstroms; the groove has a second size in a direction perpendicular to the surface of the substrate, and the size of the second size ranges from 30 angstroms to 250 angstroms.

[0022] Optionally, the erase gate structure includes a tunneling oxide layer and an erase gate located on the surface of the tunneling oxide layer; the word line structure includes a word line oxide layer and a word line located on the surface of the word line oxide layer; the method for forming the erase gate structure and the word line structure includes: after forming the floating gate, forming an oxide material layer on the surface of the substrate and the storage gate structure; forming a gate material layer on the surface of the oxide material layer, the surface of the gate material layer is higher than the top surface of the storage gate structure; planarizing the gate material layer and the oxide material layer until the top surface of the storage gate structure is exposed, forming the tunneling oxide layer and the word line oxide layer with the oxide material layer, and forming the erase gate and the word line with the gate material layer.

[0023] Optionally, the substrate includes a storage area and a peripheral area; the storage gate structure is located in the storage area; the oxide material layer is located in the storage area; the method further includes: after forming the oxide material layer and before forming the gate material layer, forming a peripheral oxide material layer on the surface of the peripheral area; after exposing the top surface of the storage gate structure and before forming the erase gate and the word line, further etching back the gate material layer; after etching back the gate material layer, patterning the gate material layer and the peripheral oxide material layer on the peripheral area to form a peripheral oxide layer with the peripheral oxide material layer, and to form a peripheral gate layer with the gate material layer.

[0024] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0025] In a method for forming a flash memory structure provided by the technical solution of the present invention, the floating gate material layer is etched by a Bosch process until the substrate surface is exposed, the floating gate is formed with the floating gate material layer, and the floating gate and the control gate structure form a storage gate structure, an opening is provided between the two storage gate structures, each floating gate has a first side wall exposed by the opening, the first side wall is in a corrugated structure, the corrugated structure includes a plurality of protrusions, the plurality of protrusions are arranged in a direction perpendicular to the substrate surface, the bottom size of the protrusion is larger than the top size, the pointed morphology of the protrusion makes it an electric field concentration point between the floating gate and the erase gate, the first side wall is in a corrugated structure, the electric field concentration points between the floating gate and the erase gate are increased, and the erasure efficiency of the flash memory structure is improved, and the plurality of electric field concentration points are beneficial to reducing the write and erase voltages, thereby reducing the power consumption of the flash memory.

[0026] Furthermore, the substrate includes a storage area and a peripheral area, the storage gate structure is located in the storage area, and a peripheral oxide material layer is formed on the surface of the storage area after the oxide material layer is formed and before the gate material layer is formed. The oxide material layer is used to form a tunneling oxide layer, and the peripheral oxide material layer is used to form an oxide layer of a peripheral area device. Due to the pointed morphology of the protrusion, during the heat treatment of the peripheral oxide material layer, the oxidation speed of the top of the protrusion is faster, which can be used as a sacrificial point to prevent further oxidation of the floating gate, thereby preventing the tunneling oxide layer between the floating gate and the erase gate from becoming thicker, reducing the probability of reducing the flash memory writing and erasing efficiency due to the thickening of the tunneling oxide layer, and improving the compatibility of the flash memory structure with the peripheral area device process.

[0027] In a flash memory structure provided by the technical solution of the present invention, each floating gate has a first side wall exposed by the opening, the first side wall is in a corrugated structure, the corrugated structure includes a plurality of protrusions, the plurality of protrusions are arranged in a direction perpendicular to the surface of the substrate, the bottom size of the protrusion is larger than the top size, the pointed morphology of the protrusion makes it an electric field focusing point between the floating gate and the erase gate, the first side wall is in a corrugated structure, which increases the electric field focusing points between the floating gate and the erase gate, which is beneficial to improving the erasing efficiency of the flash memory, and at the same time, multiple electric field focusing points are beneficial to reducing the write and erase voltages, thereby reducing the power consumption of the flash memory structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figures 1 to 4 It is a structural schematic diagram of a flash memory structure formation process;

[0029] Figures 5 to 10 is a structural schematic diagram of each step of a method for forming a flash memory structure in an embodiment of the present invention;

[0030] Figures 11 to 13 It is a structural schematic diagram of each step of a method for forming a flash memory structure in another embodiment of the present invention. DETAILED DESCRIPTION

[0031] It should be noted that the terms “surface” and “on” in this specification are used to describe relative positional relationships in space and are not limited to direct contact.

[0032] As described in the background art, the erasing capability and efficiency of the existing floating gate flash memory structure need to be further improved. Now, a flash memory structure is used for explanation and analysis.

[0033] Figures 1 to 4 The present invention is a structural schematic diagram of a flash memory structure formation process.

[0034] Please refer to Figure 1, providing a substrate 101; forming a floating gate oxide material layer 102 on the substrate 101; forming a floating gate material layer 103 on the surface of the floating gate oxide material layer 102; forming a plurality of control gate structures on the surface of part of the floating gate material layer 103, each control gate structure comprising two separate control gates, the control gate comprising a dielectric layer 104, a control gate layer 105 located on the dielectric layer 104, and a hard mask layer 106 located on the control gate layer 105, in each of the control gate structures, each control gate comprises a first side wall adjacent to another control gate (not shown in the figure).

[0035] Please refer to Figure 2 , forming a first sidewall spacer 107 on each control gate sidewall; after forming the first sidewall spacer 107 , forming a second sidewall spacer 108 on the first sidewall of the control gate, the first sidewall spacer 107 is located between the first sidewall and the second sidewall spacer 108 .

[0036] Please refer to Figure 3 , the floating gate material layer 103 is etched using the first spacer 107, the second spacer 108 and the control gate as a mask (eg Figure 2 As shown), until the floating gate oxide material layer 102 is exposed, forming a floating gate 109.

[0037] Please refer to Figure 4 An erase gate structure is formed on the surface of the substrate 101 between adjacent control gate layers 105 in each of the control gate structures, wherein the erase gate structure includes an erase gate dielectric layer 110 and an erase gate 111 located on the surface of the erase gate dielectric layer 110; and a word line 112 is formed on the surface of the substrate 101 on both sides of the control gate structure and the erase gate structure.

[0038] In the flash memory structure formed by the above method, the charge is stored in the floating gate 109. The erasing process requires a strong electric field to be formed between the floating gate 109 and the erase gate 111 to effectively extract the electrons in the floating gate 109. The effective electric field and the electron channel are more concentrated at the corner A of the floating gate 109 (such as Figure 4 As shown), the sharper the corner A is, the stronger the electric field near it is, which is more conducive to electron extraction and improving signal erasing efficiency.

[0039] However, due to the limitation of the etching process, it is difficult to form a sharp corner during the dry etching process of forming the floating gate 109. In addition, during the device processing after forming the floating gate 109 and before forming the erase gate 111, there are usually multiple thermal oxidation processes. Under the influence of the thermal oxidation process, the corner A is also easily passivated into a rounded corner, which is not conducive to forming a high electric field here, thereby seriously affecting the erase efficiency.

[0040] In order to solve the above problems, the present invention provides a flash memory structure and a method for forming the same, wherein the floating gate material layer is etched using a Bosch process until the substrate surface is exposed, the floating gate is formed with the floating gate material layer, and the floating gate and the control gate structure are used to form a storage gate structure, an opening is provided between the two storage gate structures, each floating gate has a first side wall exposed by the opening, the first side wall is in a corrugated structure, the corrugated structure includes a plurality of protrusions, the plurality of protrusions are arranged in a direction perpendicular to the substrate surface, the bottom size of the protrusion is larger than the top size, the pointed morphology of the protrusion makes it an electric field concentration point between the floating gate and the erase gate, the first side wall is in a corrugated structure, which increases the electric field concentration points between the floating gate and the erase gate, which is beneficial to improving the erasure efficiency of the flash memory structure, and at the same time, multiple electric field concentration points are beneficial to reducing the write and erase voltages, thereby reducing the power consumption of the flash memory structure.

[0041] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0042] Figures 5 to 10 It is a structural schematic diagram of each step of a method for forming a flash memory structure in an embodiment of the present invention.

[0043] Please refer to Figure 5 , providing a substrate 200; forming a floating gate material layer 201, a control gate dielectric material layer 202 located on the floating gate material layer 201, and a control gate material layer 203 located on the control gate dielectric material layer 202 on the surface of the substrate 200.

[0044] In this embodiment, the material of the substrate 200 includes silicon. In other embodiments, the material of the substrate includes silicon carbide, silicon germanium, a multinary semiconductor material composed of group III-V elements, silicon on insulator (SOI) or germanium on insulator (GOI). Among them, the multinary semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.

[0045] In this embodiment, before forming the floating gate material layer 201 , a floating gate oxide material layer 204 is further formed on the surface of the substrate 200 .

[0046] In this embodiment, the floating gate oxide material layer 204 is made of silicon oxide.

[0047] In this embodiment, the floating gate material layer 201 is made of polysilicon; the control gate dielectric material layer 202 is made of silicon oxide / silicon nitride / silicon oxide; and the control gate material layer 203 is made of polysilicon.

[0048] In this embodiment, the substrate includes a storage area (not shown in the figure) and a peripheral area (not shown in the figure). Subsequently, a storage gate structure is formed on the storage area, and a peripheral device is formed on the peripheral area.

[0049] Please refer to Figure 6 , etching the control gate material layer 203 (such as Figure 5 As shown) and the control gate dielectric material layer 202 (as shown Figure 5 ), until the floating gate material layer 201 is exposed, two control gate structures are formed on the surface of the floating gate material layer 201, each of the control gate structures includes a control gate dielectric layer 205 and a control gate 206 on the control gate dielectric layer 205, with the control gate material layer 203 (as shown) Figure 5 As shown) to form the control gate 206, the control gate dielectric material layer 202 (as shown) Figure 5 As shown) the control gate dielectric layer 205 is formed.

[0050] In this embodiment, the etching method further comprises: in part of the control gate material layer 203 (such as Figure 5 A patterned hard mask layer 207 is formed on the surface of the control gate material layer 203 (as shown); the hard mask layer 207 is used as a mask to etch the control gate material layer 203 (as shown Figure 5 As shown) and the control gate dielectric material layer 202 (as shown Figure 5 shown).

[0051] In this embodiment, each of the control gate structures includes a third sidewall (not shown in the figure) and a fourth sidewall (not shown in the figure) that are opposite to each other, and the third sidewalls of the two control gate structures are adjacent to each other.

[0052] Please refer to Figure 7 A spacer structure 208 is formed on the sidewall of the control gate structure.

[0053] In this embodiment, the sidewall structure 208 includes a first sidewall.

[0054] In this embodiment, the method for forming the sidewall structure 208 includes: forming a first sidewall material layer (not shown in the figure) on the surface of the floating gate material layer and the control gate structure; etching back the first sidewall material layer until the floating gate material layer 201 is exposed to form the first sidewall.

[0055] In this embodiment, the thickness of the sidewall structure 208 of the third sidewall and the fourth sidewall is the same. In another embodiment, the thickness of the sidewall structure of the third sidewall and the fourth sidewall is different; the sidewall structure further includes a second sidewall located on the third sidewall, and the first sidewall is located between the third sidewall and the second sidewall.

[0056] The material of the spacer structure 208 is a dielectric material, and the dielectric material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbon oxynitride.

[0057] In this embodiment, the first sidewall spacer is a double-layer structure of silicon oxide and silicon nitride. In other embodiments, the first sidewall spacer can be a single-layer or multi-layer structure.

[0058] Please refer to Figure 8 and Fig. 9 , Fig. 9 yes Figure 8 The floating gate 210 is a partially enlarged view of the floating gate 210. After forming the sidewall structure 208, the floating gate material layer 201 is etched using the Bosch process (eg, Figure 7 ), until the surface of the substrate 200 is exposed, with the floating gate material layer 201 (as shown Figure 7 A floating gate 210 is formed (as shown in the figure), and a storage gate structure is formed by the floating gate 210 and the control gate structure. An opening 211 is provided between the two storage gate structures. Each of the floating gates 210 has a first side wall (not shown in the figure) exposed by the opening 211. The first side wall is in a corrugated structure. The corrugated structure includes a plurality of protrusions 212. The plurality of protrusions 212 are arranged in a direction perpendicular to the surface of the substrate 200, and the bottom size of the protrusion 212 is larger than the top size.

[0059] The pointed shape of the protrusion 212 makes it an electric field concentration point between the floating gate 210 and the erase gate. The corrugated structure of the first side wall increases the electric field concentration points between the floating gate 210 and the erase gate, which is beneficial to improving the erasing efficiency of the flash memory structure. At the same time, multiple electric field concentration points are beneficial to reducing the writing and erasing voltages, thereby reducing the power consumption of the flash memory structure.

[0060] In this embodiment, each of the floating gates 210 further has a second side wall (not shown in the figure) opposite to the first side wall; the second side wall has the corrugated structure.

[0061] In this embodiment, there is a groove 213 between adjacent protrusions 212; the groove 213 has a first dimension m along the surface of the substrate 200, and the size of the first dimension m ranges from 100 angstroms to 250 angstroms; the groove 213 has a second dimension n in a direction perpendicular to the surface of the substrate 200, and the size of the second dimension n ranges from 30 angstroms to 250 angstroms.

[0062] In this embodiment, the Bosch process includes several processing steps, each of which includes: using various isotropic etching processes to etch the exposed floating gate material layer 201 to form a groove in the floating gate material layer 201 (not shown in the figure); after the various isotropic etching processes, using a passivation process to perform surface treatment on the groove to form a protective layer on the side wall of the groove (not shown in the figure).

[0063] In this embodiment, the number of times of the treatment process in the Bosch process ranges from 2 to 100. The more times of the treatment process, the more the number of the protrusions 212. The reason for selecting the range of times is to increase the number of electric field concentration points between the floating gate 210 and the erase gate, while avoiding too many protrusions 212 from adversely affecting the electrical properties of the interface between the floating gate 210 and the erase gate.

[0064] In this embodiment, the process parameters of the isotropic etching process include: the etching gas includes SF6, the gas flow rate ranges from 10 ml / min to 250 ml / min, and the RF power ranges from 200 W to 1000 W.

[0065] In this embodiment, the process parameters of the passivation process include: the passivation gas includes C4F8, the gas flow rate ranges from 40 ml / min to 130 ml / min, and the RF power ranges from 200 W to 1000 W.

[0066] Please refer to Fig.10 , forming an erase gate structure in the opening 211 ; and forming a word line structure on the substrate 200 on both sides of the storage gate structure and the erase gate structure.

[0067] In this embodiment, the erase gate structure includes a tunnel oxide layer 214 and an erase gate 215 located on the surface of the tunnel oxide layer 214 .

[0068] In this embodiment, the word line structure includes a word line oxide layer 216 and a word line 217 located on a surface of the word line oxide layer 216 .

[0069] In this embodiment, the method for forming the erase gate structure and the word line structure includes: after forming the floating gate 210, forming an oxide material layer (not shown in the figure) on the surface of the substrate 200 and the storage gate structure; forming a gate material layer (not shown in the figure) on the surface of the oxide material layer, and the surface of the gate material layer is higher than the top surface of the storage gate structure; planarizing the gate material layer and the oxide material layer until the top surface of the storage gate structure is exposed, forming the tunneling oxide layer 214 and the word line oxide layer 216 with the oxide material layer, and forming the erase gate 215 and the word line 217 with the gate material layer.

[0070] In this embodiment, the oxide material layer is located in the storage area.

[0071] In the present embodiment, after forming the oxide material layer and before forming the gate material layer, a peripheral oxide material layer (not shown in the figure) is formed on the surface of the peripheral region; after exposing the top surface of the storage gate structure and before forming the erase gate 215 and the word line 217, the gate material layer is also etched back; after etching back the gate material layer, the gate material layer and the peripheral oxide material layer on the peripheral region are etched until the surface of the substrate 200 is exposed, and a peripheral oxide layer is formed with the peripheral oxide material layer, and a peripheral gate layer is formed with the gate material layer.

[0072] Due to the pointed morphology of the protrusion 212, during the heat treatment of the peripheral oxide material layer, the oxidation speed of the top of the protrusion 212 is faster, and it can serve as a sacrificial point to prevent further oxidation of the floating gate 210, thereby preventing the tunneling oxide layer between the floating gate 210 and the erase gate 215 from thickening, reducing the probability of reducing the flash memory writing and erasing efficiency due to the thickening of the tunneling oxide layer, and improving the compatibility of the flash memory structure with the peripheral area device process.

[0073] Accordingly, the embodiment of the present invention also provides a flash memory structure formed by the above method, please continue to refer to Fig.10 , comprising: a substrate 200; two separate storage gate structures located on the substrate 200, with an opening 211 (such as Figure 7 As shown in the figure), each storage gate structure includes a floating gate 210, a control gate dielectric layer 205 located on the floating gate 210, and a control gate 206 located on the control gate dielectric layer 205, each of the floating gates 210 has a first side wall (not shown in the figure) exposed by the opening 211, the first side wall is a corrugated structure, the corrugated structure includes a plurality of protrusions 212, the plurality of protrusions 212 are arranged in a direction perpendicular to the surface of the substrate 200, and the bottom size of the protrusions 212 is larger than the top size; an erase gate structure located in the opening 211; and word line structures located on both sides of the storage gate structure and the erase gate structure respectively.

[0074] The pointed shape of the protrusion 212 makes it an electric field concentration point between the floating gate 210 and the erase gate. The corrugated structure of the first side wall increases the electric field concentration points between the floating gate 210 and the erase gate, which is beneficial to improving the erasing efficiency of the flash memory structure. At the same time, multiple electric field concentration points are beneficial to reducing the writing and erasing voltages, thereby reducing the power consumption of the flash memory structure.

[0075] In this embodiment, each of the floating gates 210 further has a second side wall (not shown in the figure) opposite to the first side wall; the second side wall has the corrugated structure.

[0076] In this embodiment, the erase gate structure includes a tunnel oxide layer 214 and an erase gate 215 located on the surface of the tunnel oxide layer 214 .

[0077] In this embodiment, the word line structure includes a word line oxide layer 216 and a word line 217 located on a surface of the word line oxide layer 216 .

[0078] In this embodiment, there is a groove 213 between adjacent protrusions 212; the groove 213 has a first dimension m along the surface of the substrate 200, and the size of the first dimension m ranges from 100 angstroms to 250 angstroms; the groove 213 has a second dimension n in a direction perpendicular to the surface of the substrate 200, and the size of the second dimension n ranges from 30 angstroms to 250 angstroms.

[0079] Figures 11 to 13 It is a structural schematic diagram of each step of a method for forming a flash memory structure in another embodiment of the present invention.

[0080] Please Figure 6 Continue to refer to Fig.11 , forming a sidewall structure on the sidewall of the control gate structure.

[0081] The sidewall structure includes a first sidewall 301 located on the third sidewall and the fourth sidewall.

[0082] The difference between this embodiment and the previous embodiment lies in that: in this embodiment, the thickness of the side wall structure of the third side wall and the fourth side wall is different; the side wall structure also includes a second side wall 302 located on the third side wall, and the first side wall 301 is located between the third side wall and the second side wall 302.

[0083] In this embodiment, the method for forming the sidewall structure includes: forming a first sidewall material layer (not shown in the figure) on the surface of the floating gate material layer and the control gate structure; etching back the first sidewall material layer until the floating gate material layer 201 is exposed, and forming the first sidewall 301 on the sidewall of the control gate structure; after forming the first sidewall 301, forming a second sidewall material layer (not shown in the figure) on the surface of the floating gate material layer 201 and the control gate structure; etching back the second sidewall material layer until the surface of the floating gate material layer 201 is exposed, and forming a second sidewall 302 on the sidewall surface of the first sidewall 301; after forming the second sidewall 302, forming a mask layer (not shown in the figure) on the surface of the floating gate material layer 201, and the mask layer exposes the second sidewall 302 of the fourth sidewall; and removing the second sidewall 302 of the fourth sidewall.

[0084] Please refer to Fig.12 After the sidewall structure is formed, the floating gate material layer 201 is etched by a Bosch process until the surface of the substrate 200 is exposed, and a floating gate 303 is formed with the floating gate material layer 201. A storage gate structure is formed with the floating gate 303 and the control gate structure, and an opening 304 is provided between the two storage gate structures. Each of the floating gates 303 has a first sidewall (not shown in the figure) exposed by the opening 304, and the first sidewall is a corrugated structure, and the corrugated structure includes a plurality of protrusions, and the plurality of protrusions are arranged in a direction perpendicular to the surface of the substrate 200, and the bottom size of the protrusion is larger than the top size.

[0085] In this embodiment, each floating gate 303 also has a second side wall (not shown in the figure) opposite to the first side wall, the first side wall has a third dimension d3 protruding from the side wall surface of the control gate 206, and the second side wall has a fourth dimension d4 protruding from the side wall surface of the control gate 206, and the third dimension d3 is greater than the fourth dimension d4.

[0086] In this embodiment, the difference between the third size d3 and the fourth size d4 ranges from 0 angstroms to 250 angstroms. The third size d3 is larger than the fourth size d4, which increases the coupling area between the floating gate 303 and the erase gate, facilitates electrons in the floating gate 303 to tunnel into the erase gate, and improves the erase efficiency of the formed flash memory structure.

[0087] Please refer to Fig.13 , forming an erase gate structure in the opening 304; and forming a word line structure on the substrate 200 on both sides of the storage gate structure and the erase gate structure.

[0088] In this embodiment, the erase gate structure includes a tunnel oxide layer 305 and an erase gate 306 located on the surface of the tunnel oxide layer 305 .

[0089] In this embodiment, the word line structure includes a word line oxide layer 307 and a word line 308 located on the surface of the word line oxide layer 307 .

[0090] Accordingly, the embodiment of the present invention also provides a flash memory structure formed by the above method, please continue to refer to Fig.13 The main difference between this embodiment and the previous embodiment is that:

[0091] In this embodiment, the first sidewall has a third dimension d3 protruding from the sidewall surface of the control gate 206 , and the second sidewall has a fourth dimension d4 protruding from the sidewall surface of the control gate 206 , and the third dimension d3 is greater than the fourth dimension d4.

[0092] In this embodiment, the difference between the third size d3 and the fourth size d4 ranges from 0 angstroms to 250 angstroms.

[0093] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A flash memory structure, characterized in that: include: substrate; Two separate storage gate structures located on the substrate, with an opening between the two storage structures, each storage gate structure comprising a floating gate, a control gate dielectric layer located on the floating gate, and a control gate located on the control gate dielectric layer, each floating gate having a first side wall exposed by the opening, the first side wall being a corrugated structure, the corrugated structure comprising a plurality of protrusions, the plurality of protrusions being arranged in a direction perpendicular to the surface of the substrate, and the bottom size of the protrusion being larger than the top size; an erase gate structure located in the opening; Word line structures are respectively located on both sides of the storage gate structure and the erase gate structure.

2. The flash memory structure according to claim 1, wherein: Each of the floating gates further has a second side wall opposite to the first side wall; the second side wall presents the corrugated structure.

3. The flash memory structure according to claim 2, characterized in that: The first sidewall has a third dimension protruding from the surface of the control gate sidewall, the second sidewall has a fourth dimension protruding from the surface of the control gate sidewall, and the third dimension is greater than the fourth dimension.

4. The flash memory structure according to claim 3, characterized in that: The difference between the third dimension and the fourth dimension ranges from 0 angstroms to 250 angstroms.

5. The flash memory structure according to claim 1, wherein: There are grooves between adjacent protrusions; the grooves have a first size along the surface of the substrate, and the first size ranges from 100 angstroms to 250 angstroms; the grooves have a second size in a direction perpendicular to the surface of the substrate, and the second size ranges from 30 angstroms to 250 angstroms.

6. A method for forming a flash memory structure, characterized in that: include: providing a substrate; Forming a floating gate material layer, a control gate dielectric material layer located on the floating gate material layer, and a control gate material layer located on the control gate dielectric material layer on the surface of the substrate; Etching the control gate material layer and the control gate dielectric material layer until the floating gate material layer is exposed, forming two control gate structures on the surface of the floating gate material layer, each of the control gate structures comprising a control gate dielectric layer and a control gate on the control gate dielectric layer, forming the control gate with the control gate material layer, and forming the control gate dielectric layer with the control gate dielectric material layer; forming a sidewall structure on the sidewall of the control gate structure; After forming the sidewall structure, the floating gate material layer is etched by a Bosch process until the substrate surface is exposed, a floating gate is formed by the floating gate material layer, and a storage gate structure is formed by the floating gate and the control gate structure, an opening is provided between the two storage gate structures, each of the floating gates has a first sidewall exposed by the opening, the first sidewall is a corrugated structure, the corrugated structure includes a plurality of protrusions, the plurality of protrusions are arranged in a direction perpendicular to the substrate surface, and the bottom size of the protrusion is larger than the top size; forming an erase gate structure in the opening; A word line structure is formed on the substrate at both sides of the storage gate structure and the erase gate structure.

7. The method for forming a flash memory structure according to claim 6, wherein: The Bosch process includes several processing steps, each of which includes: using various isotropic etching processes to etch the exposed floating gate material layer to form a groove in the floating gate material layer; after the various isotropic etching processes, using a passivation process to perform surface treatment on the groove to form a protective layer on the side wall of the groove.

8. The method for forming a flash memory structure according to claim 7, wherein: The number of times of the treatment process in the Bosch process ranges from 2 to 100 times.

9. The method for forming a flash memory structure according to claim 7, wherein: The process parameters of the isotropic etching process include: the etching gas includes SF6, the gas flow range is 10 ml / min to 250 ml / min, and the radio frequency power range is 200 watts to 1000 watts.

10. The method for forming a flash memory structure according to claim 7, wherein: The process parameters of the passivation process include: the passivation gas includes a gas flow range of 40 ml / min to 130 ml / min, and a radio frequency power range of 200 watts to 1000 watts.

11. The method for forming a flash memory structure according to claim 6, wherein: Each of the control gate structures includes a third sidewall and a fourth sidewall opposite to each other, and the third sidewalls of the two control gate structures are adjacent to each other; and the sidewall structure includes a first sidewall located at the third sidewall and the fourth sidewall.

12. The method for forming a flash memory structure according to claim 11, wherein: The method for forming the spacer structure comprises: forming a first spacer material layer on the surface of the floating gate material layer and the control gate structure; and etching back the first spacer material layer until the floating gate material layer is exposed.

13. The method for forming a flash memory structure according to claim 11, wherein: The sidewall structure also includes a second sidewall located on the third sidewall, and the first sidewall is located between the third sidewall and the second sidewall; each floating gate also has a second sidewall opposite to the first sidewall, the first sidewall has a third dimension protruding from the surface of the control gate sidewall, the second sidewall has a fourth dimension protruding from the surface of the control gate sidewall, and the third dimension is greater than the fourth dimension.

14. The method for forming a flash memory structure according to claim 13, wherein: The difference between the third dimension and the fourth dimension ranges from 0 angstroms to 250 angstroms.

15. The method for forming a flash memory structure according to claim 13, wherein: The method for forming the sidewall structure includes: forming a first sidewall material layer on the surface of the floating gate material layer and the control gate structure; etching back the first sidewall material layer until the floating gate material layer is exposed, and forming the first sidewall on the sidewall of the control gate structure; after forming the first sidewall, forming a second sidewall material layer on the surface of the floating gate material layer and the control gate structure; etching back the second sidewall material layer until the surface of the floating gate material layer is exposed, and forming a second sidewall on the sidewall surface of the first sidewall; after forming the second sidewall, forming a mask layer on the surface of the floating gate material layer, and the mask layer exposes the second sidewall of the second sidewall; and removing the second sidewall of the second sidewall.

16. The method for forming a flash memory structure according to claim 6, wherein: There are grooves between adjacent protrusions; the grooves have a first size along the surface of the substrate, and the first size ranges from 100 angstroms to 250 angstroms; the grooves have a second size in a direction perpendicular to the surface of the substrate, and the second size ranges from 30 angstroms to 250 angstroms.

17. The method for forming a flash memory structure according to claim 6, wherein: The erase gate structure includes a tunnel oxide layer and an erase gate located on the surface of the tunnel oxide layer; The word line structure includes a word line oxide layer and a word line located on the surface of the word line oxide layer; The method for forming the erase gate structure and the word line structure comprises: after forming the floating gate, forming an oxide material layer on the surface of the substrate and the storage gate structure; forming a gate material layer on the surface of the oxide material layer, wherein the surface of the gate material layer is higher than the top surface of the storage gate structure; planarizing the gate material layer and the oxide material layer until the top surface of the storage gate structure is exposed, forming the tunneling oxide layer and the word line oxide layer with the oxide material layer, and forming the erase gate and the word line with the gate material layer.

18. The method for forming a flash memory structure according to claim 17, wherein: The substrate includes a storage area and a peripheral area; the storage gate structure is located in the storage area; the oxide material layer is located in the storage area; the method also includes: after forming the oxide material layer and before forming the gate material layer, forming a peripheral oxide material layer on the surface of the peripheral area; after exposing the top surface of the storage gate structure and before forming the erase gate and the word line, etching back the gate material layer; after etching back the gate material layer, patterning the gate material layer and the peripheral oxide material layer on the peripheral area, forming a peripheral oxide layer with the peripheral oxide material layer, and forming a peripheral gate layer with the gate material layer.

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