Electronic device and method of manufacturing electronic device

Abstract

The invention relates to an electronic device and a method of manufacturing the electronic device. The electronic device includes: a display panel including a base layer including a first region and a second region surrounding the first region, a pixel overlapping the second region on the base layer, and an encapsulation layer covering the pixel, the encapsulation layer including a first electrode, a second electrode, and a second electrode; and the encapsulation layer is provided with a module hole defined through the encapsulation layer and overlapping the first region; a capping layer including an organic material and on the display panel; an anti-reflection layer on the capping layer; an electronic module overlapping the module hole; and a window on the anti-reflection layer, in which the first region includes a dam region adjacent to the second region and surrounding the module hole, and an edge region between the module hole and the dam region, and the cover layer overlaps the dam region and the second region and the cover layer is spaced apart from the edge region.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0076710 filed in the Korean Intellectual Property Office on June 15, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Aspects of some embodiments of the present disclosure relate to electronic devices and methods of manufacturing electronic devices. Background Art

[0004] The electronic device is activated in response to an electrical signal. The electronic device may include a device configured by various electronic components, such as a display panel configured to display an image, or an input sensor configured to sense an external input. The electronic components may be electrically connected to each other through signal lines arranged in various ways.

[0005] The above information disclosed in this Background section is only for enhancement of understanding of the background technology, and therefore the information discussed in this Background section does not necessarily constitute prior art. Summary of the invention

[0006] Aspects of some embodiments of the present disclosure relate to an electronic device with improved display quality and a method of manufacturing the electronic device.

[0007] Aspects of some embodiments of the present disclosure include electronic devices having relatively improved display quality.

[0008] Aspects of some embodiments of the present disclosure include methods of manufacturing an electronic device.

[0009] Aspects of some embodiments of the present disclosure include an electronic device, the electronic device comprising: a display panel including a base layer, a pixel, and an encapsulation layer, the base layer including a first region and a second region surrounding the first region, the pixel overlapping the second region on the base layer, the encapsulation layer covering the pixel, and the encapsulation layer being provided with a module hole defined through the encapsulation layer and overlapping the first region; a cover layer including an organic material and on the display panel; an anti-reflection layer on the cover layer; an electronic module overlapping the module hole; and a window on the anti-reflection layer. According to some embodiments, the first region includes a dam region adjacent to the second region and surrounding the module hole, and an edge region between the module hole and the dam region, and the cover layer overlaps the dam region and the second region and the cover layer is spaced apart from the edge region.

[0010] According to some embodiments, a portion of the cover layer overlapping the second region has a thickness equal to or greater than about 2 micrometers and equal to or less than about 5 micrometers.

[0011] According to some embodiments, a portion of the cover layer overlapping the dam region of the first region has a thickness greater than a thickness of the cover layer overlapping the second region.

[0012] According to some embodiments, the encapsulation layer includes: a first inorganic layer covering the pixel; a second inorganic layer on the first inorganic layer; and an organic layer between the first inorganic layer and the second inorganic layer.

[0013] According to some embodiments, the capping layer is in contact with the second inorganic layer.

[0014] According to some embodiments, the first inorganic layer and the second inorganic layer contact each other in the edge region.

[0015] According to some embodiments, the display panel further includes an intermediate layer between the second inorganic layer and the cover layer and extending from the second region to the edge region via the dam region, and the intermediate layer includes an inorganic material.

[0016] According to some embodiments, the organic layer overlapping the second region has a thickness equal to or greater than about 5 micrometers and equal to or less than about 10 micrometers.

[0017] According to some embodiments, the electronic device further includes an input sensor, the input sensor including: a first sensing insulating layer on the packaging layer; a second sensing insulating layer on the first sensing insulating layer; a first conductive layer on the second sensing insulating layer; a third sensing insulating layer covering the first conductive layer and on the second sensing insulating layer; and a second conductive layer on the third sensing insulating layer. The covering layer covers the second conductive layer and is on the third sensing insulating layer.

[0018] According to some embodiments, the first sensing insulation layer and the third sensing insulation layer overlap with the second region and the dam region, and the first sensing insulation layer and the third sensing insulation layer are spaced apart from the edge region, and the second sensing insulation layer extends from the second region to the edge region via the dam region.

[0019] According to some embodiments, each of a thickness of the first sensing insulation layer and a thickness of the third sensing insulation layer is greater than a thickness of the cover layer.

[0020] According to some embodiments, the first sensing insulation layer and the third sensing insulation layer include organic materials, and the second sensing insulation layer includes an inorganic material.

[0021] According to some embodiments, the electronic device further includes a plurality of dam patterns in the dam region and surrounding the module hole, and each of the plurality of dam patterns includes a tip portion protruding from a side surface of a corresponding one of the plurality of dam patterns and including a conductive material.

[0022] According to some embodiments, the tip portion is covered by the first inorganic layer.

[0023] According to some embodiments, a boundary of the organic layer in the dam region is defined by one of the plurality of dam patterns.

[0024] According to some embodiments, the electronic device also includes: a first adhesive layer between the covering layer and the anti-reflection layer; and a second adhesive layer between the anti-reflection layer and the window, and the first adhesive layer and the second adhesive layer each include at least one of an optically transparent adhesive, an optically transparent adhesive resin, and a pressure-sensitive adhesive.

[0025] According to some embodiments, the window includes a bezel pattern on a rear surface of the window overlapping the first area, and the bezel pattern is provided with an opening defined through the bezel pattern and overlapping the module hole.

[0026] Aspects of some embodiments of the present disclosure include a method for manufacturing an electronic device. According to some embodiments, the method includes: providing a display panel, the display panel including a base layer, a pixel and an encapsulation layer, a first area including a hole processing area, an edge area surrounding the hole processing area and a dam area surrounding the edge area is defined in the base layer, the pixel is formed on the base layer, and the encapsulation layer covers the pixel; coating an organic material on the display panel to form a covering layer; patterning the covering layer, the covering layer overlaps the hole processing area and the edge area; irradiating a laser beam on the rear surface of the base layer along a boundary between the hole processing area and the edge area; and spraying an etchant on the boundary to form a module hole. According to some embodiments, the patterning of the covering layer is performed by a photoresist process.

[0027] According to some embodiments, the encapsulation layer includes a first inorganic layer, an organic layer on the first inorganic layer, and a second inorganic layer on the organic layer, the first inorganic layer and the second inorganic layer contact each other in the edge region, and in the patterning of the covering layer, the second inorganic layer overlapping the edge region is exposed via an opening formed through the covering layer.

[0028] According to some embodiments, the organic layer has a thickness equal to or greater than about 5 micrometers and equal to or less than about 10 micrometers, and the capping layer has a thickness equal to or greater than about 2 micrometers and equal to or less than about 5 micrometers.

[0029] Some embodiments may be able to adjust the thickness of an organic layer included in an encapsulation layer, and thus, may relatively improve ripples generated in a region in which the thickness of the organic layer varies.

[0030] According to some embodiments, a pre-ablation process is not required to be performed in a process of forming a module hole to remove an organic layer formed by an inkjet process, thereby reducing the manufacturing cost of an electronic device. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The above and other aspects of some embodiments of the present disclosure will become readily apparent by reference to the following detailed description when considered in conjunction with the accompanying drawings, in which:

[0032] Figure 1 is a perspective view showing an electronic device according to some embodiments of the present disclosure;

[0033] Figure 2 is an exploded perspective view showing an electronic device according to some embodiments of the present disclosure;

[0034] Figure 3 is a block diagram illustrating an electronic device according to some embodiments of the present disclosure;

[0035] Figure 4 is a plan view of a display panel at a portion adjacent to a hole according to some embodiments of the present disclosure;

[0036] Figure 5 It is along Figure 2 A cross-sectional view taken along line II';

[0037] Figure 6 is a cross-sectional view showing a display module according to some embodiments of the present disclosure;

[0038] Figure 7 is a cross-sectional view showing a display module according to some embodiments of the present disclosure;

[0039] Figures 8 to 12 is a cross-sectional view illustrating a method of manufacturing an electronic device according to some embodiments of the present disclosure; and

[0040] Figures 13 to 17 is a cross-sectional view illustrating a method of manufacturing an electronic device according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0041] In the present disclosure, it will be understood that when an element or layer is referred to as being "on," "connected to" or "coupled to" another element or layer, the element or layer can be directly on, directly connected to or directly coupled to the other element or layer, or intervening elements or layers may be present.

[0042] The same reference numerals always refer to the same elements. In the accompanying drawings, the thickness, proportion and size of the components are exaggerated for the effective description of the technical content. As used herein, the term "and / or" may include any and all combinations of one or more of the related listed items.

[0043] It will be understood that, although the terms first, second, etc. can be used to describe various elements in this article, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, without departing from the teaching of the present disclosure, the first element discussed below can be referred to as the second element. Unless the context clearly indicates otherwise, as used in this article, the singular form "one", "one (kind / person)" and "the (the)" are also intended to include plural forms.

[0044] For ease of description, spatially relative terms such as “under,” “beneath,” “lower,” “over,” and “upper” may be used herein to describe the relationship of one element or feature to another element or feature shown in the drawings.

[0045] It will also be understood that when used in this specification, the terms “include” and / or “comprises” indicate the presence of stated features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or combinations thereof.

[0046] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will also be understood that, unless explicitly so defined herein, terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formalized sense.

[0047] Hereinafter, aspects of some embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings.

[0048] Figure 1 is a perspective view showing an electronic device 1000 according to some embodiments of the present disclosure. Figure 2 is an exploded perspective view illustrating an electronic device 1000 according to some embodiments of the present disclosure. Figure 3 is a block diagram illustrating an electronic device 1000 according to some embodiments of the present disclosure. Figure 4 is the display panel 110 (refer to Figure 3 )’s floor plan.

[0049] The electronic device 1000 may be a device activated in response to an electrical signal. The electronic device 1000 may include various embodiments. For example, the electronic device 1000 may include a computer (e.g., a tablet computer, a notebook computer) or a smart TV, etc. In the presented embodiments, a smart phone will be described as a representative example of the electronic device 1000, but embodiments according to the present disclosure are not limited thereto.

[0050] Reference Figure 1 and Figure 2 , the electronic device 1000 may display one or more images IM through a display surface FS, which is parallel to a plane defined by the first direction DR1 and the second direction DR2. The image IM may be displayed toward a third direction DR3 that is perpendicular to the plane defined by the first direction DR1 and the second direction DR2. The display surface FS through which the image IM is displayed may correspond to the front surface FS of the electronic device 1000 and the front surface FS of the window 300. Hereinafter, the display surface FS and the front surface FS of the electronic device 1000 and the front surface FS of the window 300 will be assigned the same reference numerals. The image IM may include a static image (e.g., a still image) as well as a dynamic image or a video image. Figure 1 A clock widget and application icons are shown as representative examples of the image IM.

[0051] In the present embodiment, the front (or upper) and rear (or lower) surfaces of each member of the electronic device 1000 may be defined relative to the direction in which the image IM is displayed. The front surface and the rear surface may face away from each other in the third direction DR3, and the normal direction of each of the front surface and the rear surface may be substantially parallel to the third direction DR3. The separation distance between the front surface and the rear surface of the electronic device 1000 may correspond to the thickness of the electronic device 1000 in the third direction DR3.

[0052] According to some embodiments, the electronic device 1000 may sense a user input (or external input) TC applied thereto from the outside. The user input TC may include various types of external inputs such as a part of the user's body, a stylus, light, heat, or pressure. In this embodiment, the user input TC is shown as a user's hand applied to the front surface FS of the electronic device 1000.

[0053] However, this is merely an example, and the electronic device 1000 may sense the user input TC applied to the side surface or the rear surface of the electronic device 1000 depending on its structure, and should not be limited to a specific embodiment.

[0054] According to some embodiments, the electronic device 1000 may include a first area A1 defined in the transmissive area TA. The first area A1 may be an area where the display module 100 described later overlaps with the electronic module 400. The module hole MH of the display module 100 may be defined in the first area A1.

[0055] The electronic device 1000 may receive an external signal required by the electronic module 400 via the first area A1, or may provide a signal output from the electronic module 400 to the outside via the first area A1. According to the present disclosure, when the first area A1 is defined in the transmissive area TA, the size of the bezel area BZA may be reduced compared to when the first area A1 is defined in the bezel area BZA.

[0056] Reference Figure 2 , the electronic device 1000 may include a display module 100, a housing 200, a window 300, and an electronic module 400. The window 300 and the housing 200 may be coupled to each other to provide an external appearance of the electronic device 1000.

[0057] The window 300 may include an insulating panel. For example, the window 300 may include a glass material, a plastic material, or a combination thereof. As described above, the front surface FS of the window 300 may define the front surface FS of the electronic device 1000. The window 300 may include a transmission area TA and a frame area BZA adjacent to the transmission area TA. The transmission area TA may be an optically transparent area. For example, the transmission area TA may be an area having a visible light transmittance of about 90% or more. The frame area BZA may be an area having a relatively low transmittance compared to the transmission area TA. The frame area BZA may define the shape of the transmission area TA.

[0058] The frame area BZA may have a color (eg, a set or predetermined color). The frame area BZA may be defined by a frame layer provided separately from the transparent substrate defining the transmission area TA, or may be defined by an ink layer formed by inserting into the transparent substrate or by printing a color on the transparent substrate.

[0059] The display module 100 may include an electronic panel EP and a driving circuit IC. The electronic panel EP may display an image IM (see Figure 1 ) and can sense user input TC (refer to Figure 1). The electronic panel EP may include a front surface IS in which an active area AA and a peripheral area NAA are defined. The active area AA may be an area activated in response to an electrical signal. The electronic panel EP may be defined as including a display panel 110 (refer to FIG. 1 ) among components included in the display module 100. Figure 3 ) and input sensor 120 (refer to Figure 3 ).

[0060] According to some embodiments, the active area AA may be a region in which an image IM is displayed and an external input TC is sensed. The active area AA may be a region in which a plurality of pixels PX are arranged.

[0061] The active area AA may overlap at least a portion of the transmissive area TA. As an example, the transmissive area TA may overlap all or at least a portion of the active area AA. Therefore, the user may observe the image IM or may provide an external input TC via the transmissive area TA, however, this is merely an example. That is, the area through which the image IM is displayed and the area through which the external input TC is sensed may be separated from each other in the active area AA, and the area through which the image IM is displayed and the area through which the external input TC is sensed should not be limited to a specific embodiment.

[0062] The peripheral area NAA may be covered by the frame area BZA. The peripheral area NAA may be located adjacent to the active area AA. The peripheral area NAA may surround the active area AA. The peripheral area NAA may be an area where the image IM is not displayed. A driving circuit or a driving line may be located in the peripheral area NAA to drive the active area AA.

[0063] According to some embodiments, a portion of the peripheral area NAA of the electronic panel EP may be bent. As an example, the electronic panel EP may include a flat portion FN and a bent portion BN. The flat portion FN may be assembled to be substantially parallel to a plane defined by the first direction DR1 and the second direction DR2. The active area AA may be defined in the flat portion FN.

[0064] The bent portion BN may extend from the flat portion FN and may be bent relative to an imaginary bending axis. The bent portion BN may be assembled to be bent from the flat portion FN and positioned on the rear side of the flat portion FN. Since the bent portion BN overlaps with the flat portion FN in a plan view when assembled, the border area BZA of the electronic device 1000 may be reduced. Meanwhile, this is merely an example, and the bent portion BN may be omitted from the electronic panel EP.

[0065] The driving circuit IC may be mounted on the bent portion BN. The driving circuit IC may be provided in a chip form, however, it should not be limited thereto or thereby. According to some embodiments, the driving circuit IC may be electrically connected to the electronic panel EP via a flexible film after being provided to a separate circuit board.

[0066] The driving circuit IC may be electrically connected to the active area AA, and may apply an electrical signal to the active area AA. As an example, the driving circuit IC may include a data driving circuit, and may apply a data signal to the pixel PX arranged in the active area AA. According to some embodiments, the driving circuit IC may include a touch driving circuit, and may be electrically connected to an input sensor positioned in the active area AA. Meanwhile, this is merely an example, and according to some embodiments, the driving circuit IC may be designed to include various circuits other than the above-mentioned circuits, or to apply various electrical signals to the active area AA, and it should not be particularly limited.

[0067] The electronic device 1000 may further include a main circuit board electrically connected to the electronic panel EP and the driving circuit IC. The main circuit board may include various driving circuits for driving the electronic panel EP, or a connector for providing power. The main circuit board may be a rigid printed circuit board (PCB), however, according to some embodiments, the main circuit board may be a flexible circuit board, and it should not be particularly limited.

[0068] The electronic module 400 may be positioned below the display module 100. The electronic module 400 may receive an external input via the first area A1 or may output a signal via the first area A1. According to the present disclosure, since the first area A1 having a relatively high transmittance is defined in the active area AA, the electronic module 400 may be arranged to overlap with the active area AA. Therefore, the size of the bezel area BZA may be prevented from increasing.

[0069] The housing 200 may be coupled with the window 300 to provide an internal space (eg, a set or predetermined internal space), and may define the appearance of the electronic device 1000. Components of the electronic device 1000 such as the display module 100 and the electronic module 400 may be accommodated in the internal space.

[0070] The housing 200 may have a relatively high rigidity material. For example, the housing 200 may include glass, plastic, or metal materials or multiple frames, plates, and / or combinations thereof. The housing 200 may stably protect the components of the electronic device 1000 accommodated in the internal space from external impacts.

[0071] Reference Figure 3 And combined with Figure 1 and Figure 2, the electronic device 1000 may include a display module 100, a power module PM, a first electronic module EM1, and a second electronic module EM2. The display module 100, the power module PM, the first electronic module EM1, and the second electronic module EM2 may be electrically connected to each other.

[0072] Figure 3 The components of the display module 100 are shown as being included in the electronic panel EP (refer to Figure 2 ) in the display panel 110 and the input sensor 120. The display panel 110 may include a configuration for generating an image IM. The image IM generated by the display panel 110 may be displayed in the display surface FS and may be visible to the user from the outside through the transmission area TA. The input sensor 120 may sense an external input TC applied thereto from the outside. As described above, the input sensor 120 may sense an external input TC applied to the window 300.

[0073] The power module PM may supply power required for overall operations of the electronic device 1000. The power module PM may include a conventional battery module.

[0074] The first and second electronic modules EM1 and EM2 may each include various functional modules to operate the electronic device 1000. The first electronic module EM1 may be directly mounted on a motherboard electrically connected to the electronic panel EP, or may be electrically connected to the motherboard via a connector after being mounted on a separate substrate.

[0075] The first electronic module EM1 may include a control module CM, a wireless communication module TM, an image input module IIM, an audio input module AIM, a memory MM, and an external interface IF. Some of the modules may be electrically connected to the motherboard through a flexible circuit board without being mounted on the motherboard.

[0076] The control module CM may control the overall operation of the electronic device 1000. The control module CM may be (but not limited to) a microprocessor. For example, the control module CM may activate or disable the display module 100. The control module CM may control other modules such as the image input module IIM or the audio input module AIM based on a touch signal provided from the electronic panel EP.

[0077] The wireless communication module TM can transmit / receive wireless signals to / from other terminals using a Bluetooth or WiFi link. The wireless communication module TM can transmit / receive voice signals using a general communication line. The wireless communication module TM may include a transmitter TM1 that modulates a signal to be transmitted and transmits the modulated signal and a receiver TM2 that demodulates a signal applied thereto.

[0078] The image input module IIM can process image signals and convert them into image data that can be displayed through the electronic panel EP. The audio input module AIM can receive external sound signals through a microphone in a recording mode or a voice recognition mode and convert them into electronic voice data.

[0079] The external interface IF may serve as an interface between the control module CM and external devices such as an external charger, wired / wireless data ports, card slots (e.g., memory card slots and subscriber identity module / user identity module (SIM / UIM) card slots), etc.

[0080] The second electronic module EM2 may include an audio output module AOM, a light emitting module LM, a light receiving module LRM, and a camera module CMM. The components may be electrically connected to the electronic panel EP after being directly mounted on a motherboard, may be electrically connected to the electronic panel EP via a connector after being mounted on a separate substrate, or may be electrically connected to the first electronic module EM1.

[0081] The audio output module AOM may convert sound data provided from the wireless communication module TM or sound data stored in the memory MM, and may output the converted sound data to the outside.

[0082] The light emitting module LM may generate light and may output light. The light emitting module LM may emit infrared rays. The light emitting module LM may include a light emitting diode (LED) element. The light receiving module LRM may sense infrared rays. When infrared rays having a certain level (e.g., a set or predetermined level) or higher are sensed, the light receiving module LRM may be activated. The light receiving module LRM may include a complementary metal oxide semiconductor (CMOS) sensor. The infrared rays generated by the light emitting module LM and output from the light emitting module LM may be reflected by an external object (e.g., a finger or face of a user), and the reflected infrared rays may be incident into the light receiving module LRM. The camera module CMM may capture images of external objects.

[0083] According to some embodiments, the electronic module 400 may include at least one of the multiple components of the second electronic module EM2. For example, the electronic module 400 may include at least one of a camera, a speaker, a light sensing sensor, and a heat sensing sensor. The electronic module 400 may sense an external object via the first area A1 or may provide a sound signal such as a voice to the outside through the first area A1. In addition, the electronic module 400 may include multiple components and should not be limited to a specific embodiment. According to some embodiments, the electronic module 400 may be attached to the electronic panel EP by a separate adhesive.

[0084] Figure 4 The display panel 110 (see Figure 3 ) a portion XX' of the active area AA adjacent to the module hole MH.

[0085] Reference Figure 4 , among the pixels PX included in the display panel 110, most of the plurality of pixels PX may be arranged in the second area A2, and some of the plurality of pixels PX may be arranged in the second area A2 along a boundary between the first area A1 and the second area A2 and may be spaced apart from the first area A1.

[0086] The module hole MH may be defined in the active area AA. Therefore, at least some of the plurality of pixels PX may be arranged adjacent to the module hole MH, and at least some of the plurality of pixels PX may be spaced apart from the module hole MH, with the module hole MH interposed between at least some of the plurality of pixels PX.

[0087] At least one tip portion TIP may be defined in the first area A1 of the display panel 110. The electronic device 1000 (refer to Figure 2 ) can block the path through which moisture and / or oxygen enter the pixel PX from the module hole MH. That is, the element formed after the tip portion TIP is formed and including the organic material can be disconnected by the tip portion TIP. As an example, referring to Figure 5 The described light emitting layer EML may be disconnected in the region overlapping the tip portion TIP, and thus, a path through which moisture and / or oxygen enters the light emitting layer EML from the module hole MH may be blocked. Therefore, the display quality of the display panel 110 may be relatively improved.

[0088] When viewed in a plan view, the tip portion TIP may overlap the first area A1 and may surround at least a portion of the module hole MH. The tip portion TIP may be defined to be closer to the second area A2 than the module hole MH. When viewed in a plan view, the tip portion TIP may have a closed line shape to surround the module hole MH. The tip portion TIP may be provided in plurality, and each of the plurality of tip portions may surround the module hole MH.

[0089] According to some embodiments, a filling portion may be positioned in the module hole MH. The filling portion may include a polymer resin. Since the filling portion is positioned in the module hole MH, the filling portion may provide a flat surface for an element positioned on the filling portion in the module hole MH.

[0090] exist Figure 4In the embodiment, when viewed in a plan view, the tip portion TIP and the module hole MH have a circular shape, however, the tip portion TIP and the module hole MH may have shapes different from each other. In addition, each of the tip portion TIP and the module hole MH may have a closed line shape (including a polygonal shape, an elliptical shape, or a curved shape), or a shape including a plurality of partially disconnected patterns, however, it should not be particularly limited.

[0091] A portion of each of the signal lines SGL1 and SGL2 connected to the pixel PX may be positioned in the first area A1. The signal lines SGL1 and SGL2 may be connected to the pixels PX spaced apart from each other via the first area A1 with the module hole MH interposed therebetween. For ease of explanation, Figure 4 Two signal lines SGL1 and SGL2 among a plurality of signal lines connected to the pixel PX are shown as a representative example.

[0092] The first signal line SGL1 may extend in the first direction DR1. The first signal line SGL1 may be connected to pixels PX arranged in the same row along the first direction DR1 among the plurality of pixels PX. As a representative example, the first signal line SGL1 will be described as corresponding to one of the plurality of scan lines connected to the pixel PX.

[0093] Some of the plurality of pixels PX connected to the first signal line SGL1 may be positioned at the left side relative to the module hole MH, and other pixels PX of the plurality of pixels PX connected to the first signal line SGL1 may be positioned at the right side relative to the module hole MH. Therefore, even if some pixels PX are omitted around the module hole MH, the pixels PX arranged in the same row and connected to the first signal line SGL1 may be turned on or off in response to the same scan signal.

[0094] The second signal line SGL2 may extend in the second direction DR2. The second signal line SGL2 may be connected to pixels arranged in the same column in the second direction DR2 among the plurality of pixels PX. As a representative example, the second signal line SGL2 will be described as corresponding to one of the plurality of data lines.

[0095] Some of the plurality of pixels PX connected to the second signal line SGL2 may be positioned at the upper side relative to the module hole MH, and other pixels PX of the plurality of pixels PX connected to the second signal line SGL2 may be positioned at the lower side relative to the module hole MH. Therefore, even if some pixels PX are omitted around the module hole MH, the pixels PX arranged in the same column and connected to the second signal line SGL2 may receive data signals through the same line.

[0096] At least one of the first signal line SGL1 and the second signal line SGL2 may be disconnected at a point where the first signal line SGL1 and the second signal line SGL2 intersect in the first area A1, and a connection pattern positioned on a layer different from the disconnected signal line may also be provided to connect the disconnected portion of the disconnected signal line. However, the connection between the pixels PX spaced apart from each other with the module hole MH interposed therebetween should not be limited to or thereby.

[0097] Figure 5 It is along Figure 2 A cross-sectional view taken along line I-I'. Figure 5 References omitted Figure 2 The housing 200 is described.

[0098] The display module 100 may include a first area A1 and a second area A2 surrounding at least a portion of the first area A1. The first area A1 may include a dam area A1-D, an edge area A1-M, and a hole processing area A1-H.

[0099] The dam area A1-D may be adjacent to the second area A2. The edge area A1-M may be positioned between the dam area A1-D and the hole processing area A1-H. The hole processing area A1-H may overlap with the module hole MH.

[0100] The display panel 110 may include a base layer SUB, a circuit element layer, a display element layer, and an encapsulation layer TFE. In the present disclosure, the "circuit element layer" may be defined as including the transistor TR and the insulating layers 10, 20, 30, and 40. The "display element layer" may be defined as including the pixel defining layer 50 and the light emitting element OL.

[0101] The substrate layer SUB may provide a substrate surface on which display elements and signal lines of the display panel 110 are positioned. An insulating layer, a semiconductor layer, and a conductive layer may be formed on the substrate layer SUB by a coating process or a deposition process. Then, the insulating layer, the semiconductor layer, and the conductive layer may be selectively patterned by a photolithography process. Thus, a semiconductor pattern, a conductive pattern, and a signal line may be formed.

[0102] The base layer SUB may be provided in the form of a multilayer film in which inorganic layers and organic layers are alternately stacked, however, it should not be limited thereto. According to some embodiments, the base layer SUB may have a single-layer structure. In this case, the base layer SUB may include a synthetic resin film or may include one of glass and metal materials. The synthetic resin film may include a thermosetting resin. In particular, the synthetic resin film may be a polyimide-based resin layer, and the material used for the synthetic resin film should not be particularly limited. In the present disclosure, the first area A1 and the second area A2 are defined in the base layer SUB.

[0103] The transistor TR may be positioned on the base layer SUB. The transistor TR may include a semiconductor pattern SP, a source electrode SE, a drain electrode DE, and a gate electrode GE.

[0104] The semiconductor pattern SP may be positioned on the base layer SUB. The semiconductor pattern SP may include a silicon semiconductor. As an example, the semiconductor pattern SP may include a crystalline silicon semiconductor, a polycrystalline silicon semiconductor, or an amorphous silicon semiconductor, however, it should not be limited thereto or thereby. The semiconductor pattern SP may include an oxide semiconductor. The semiconductor pattern SP may include a variety of materials as long as the semiconductor pattern SP has semiconductor characteristics, and it should not be particularly limited.

[0105] The circuit element layer may be positioned on the base layer SUB. The circuit element layer may include transistors TR and insulating layers 10, 20, 30, and 40.

[0106] The semiconductor pattern SP of the transistor TR may be positioned on the base layer SUB. The semiconductor pattern SP may include a source region Sa, a drain region Da, and a channel region Ca. The semiconductor pattern SP may include a plurality of regions distinguished from each other by conductivity. As an example, the semiconductor pattern SP may have different electrical characteristics depending on whether it is doped, whether it is doped with an N-type dopant or a P-type dopant, or whether the metal oxide is reduced. A portion of the semiconductor pattern having a relatively high conductivity may be used as an electrode or a signal line, and may correspond to the source region Sa and the drain region Da of the transistor TR. An undoped or unreduced portion of the semiconductor pattern having a relatively low conductivity may correspond to the channel region Ca (or active region) of the transistor TR.

[0107] The circuit element layer may further include a barrier layer and / or a buffer layer positioned between the semiconductor pattern SP and the base layer SUB. The barrier layer may include an inorganic material. As an example, the barrier layer may include at least one of silicon oxide, aluminum oxide, titanium oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide.

[0108] The buffer layer may be positioned on the barrier layer, or when the barrier layer is omitted, the buffer layer may be positioned directly on the base layer SUB. The buffer layer may improve the adhesion between the barrier pattern and the semiconductor pattern and / or between the barrier pattern and the conductive pattern. The buffer layer may include a silicon oxide layer and a silicon nitride layer. In addition, the buffer layer may have a single-layer or multi-layer structure of silicon oxynitride, however, it should not be limited thereto or should not be limited thereto.

[0109] The first insulating layer 10 may be positioned on the base layer SUB and may cover the semiconductor pattern SP of the transistor TR. The first insulating layer 10 may include an inorganic layer having a single-layer or multi-layer structure.

[0110] The gate electrode GE may be positioned on the first insulating layer 10. When viewed in a plan view, the gate electrode GE may overlap the channel region Ca. The gate electrode GE may be used as a mask in a process of doping the semiconductor pattern SP.

[0111] The second insulating layer 20 may be positioned on the first insulating layer 10 and may cover the gate electrode GE. The second insulating layer 20 may include an inorganic layer having a single layer or multi-layer structure.

[0112] The source electrode SE and the drain electrode DE may be positioned on the second insulating layer 20. The source electrode SE may be connected to the source region Sa of the semiconductor pattern SP via a contact hole defined through the first insulating layer 10 and the second insulating layer 20. The drain electrode DE may be connected to the drain region Da of the semiconductor pattern SP via a contact hole defined through the first insulating layer 10 and the second insulating layer 20. The source electrode SE and the drain electrode DE may be arranged to be spaced apart from each other on the second insulating layer 20.

[0113] The third insulating layer 30 may be positioned on the second insulating layer 20 and may cover the source electrode SE and the drain electrode DE. The third insulating layer 30 may include an organic layer. The third insulating layer 30 including the organic layer may compensate for a step difference between components positioned thereunder and may provide a flat surface.

[0114] The circuit element layer may further include a connection electrode CNE. The connection electrode CNE may be positioned on the third insulating layer 30. The connection electrode CNE may electrically connect the transistor TR with the light emitting element OL. The connection electrode CNE may be connected to the source electrode SE via a contact hole defined through the third insulating layer 30, however, it should not be limited thereto or thereby. According to some embodiments, the circuit element layer may further include an additional electrode that connects the connection electrode CNE with the light emitting element OL, is positioned on an additional insulating layer between the third insulating layer 30 and the fourth insulating layer 40, and is connected to the connection electrode CNE through the additional insulating layer, however, the present disclosure should not be particularly limited thereto.

[0115] The fourth insulating layer 40 may be positioned on the third insulating layer 30 and may cover the connection electrode CNE. The fourth insulating layer 40 may include an organic layer. The fourth insulating layer 40 including the organic layer may provide a flat surface.

[0116] At the same time, the configuration of the circuit element layer should not be limited to Figure 5The configuration shown in , and the circuit element layer may further include an additional insulating layer. One or more insulating layers may be additionally provided to be positioned between the first insulating layer 10 to the fourth insulating layer 40, below the first insulating layer 10, or on the fourth insulating layer 40. The circuit element layer may have a variety of cross-sectional structures according to the circuit design, and should not be particularly limited.

[0117] The display element layer may be positioned on the circuit element layer. The display element layer may include a light emitting element OL and a pixel defining layer 50.

[0118] The light emitting element OL may be positioned in the second area A2. The light emitting element OL may include a first electrode AE, a light emitting layer EML, and a second electrode CE. The light emitting element OL may further include a hole control layer positioned between the first electrode AE ​​and the light emitting layer EML, and an electron control layer positioned between the light emitting layer EML and the second electrode CE.

[0119] Each of the second electrode CE, the hole control layer, and the electron control layer may be completely formed throughout the first area A1 and the second area A2. Each of the second electrode CE, the hole control layer, and the electron control layer may be completely formed throughout the active area AA by a deposition process using an open mask. Therefore, the second electrode CE, the hole control layer, and the electron control layer may be referred to as a common layer.

[0120] The first electrode AE ​​may be an anode electrode, and the second electrode CE may be a cathode electrode. As an example, the light emitting element OL may include an organic light emitting element, a quantum dot light emitting element, a micro-LED, or a nano-LED, however, it should not be limited thereto or thereby. The light emitting element OL may include various embodiments as long as light can be generated or the amount of light can be controlled according to an electrical signal.

[0121] The first electrode AE ​​may be positioned on the fourth insulating layer 40. The first electrode AE ​​may be connected to the connection electrode CNE via a contact hole defined through the fourth insulating layer 40. The first electrode AE ​​may be electrically connected to the drain region Da of the transistor TR via the connection electrode CNE and the source electrode SE.

[0122] The pixel defining layer 50 may be positioned on the fourth insulating layer 40. The pixel defining layer 50 is provided with a light emitting opening defined through the pixel defining layer 50 to expose at least a portion of the first electrode AE. The portion of the first electrode AE ​​exposed through the light emitting opening may correspond to a light emitting region.

[0123] The pixel defining layer 50 may be formed of a polymer resin. As an example, the pixel defining layer 50 may include a polyacrylate-based resin or a polyimide-based resin. In addition to the polymer resin, the pixel defining layer 50 may also include an inorganic material. According to some embodiments, the pixel defining layer 50 may include an inorganic material. As an example, the pixel defining layer 50 may include silicon nitride (SiN x ), silicon oxide (SiO x ), or silicon oxynitride (SiO x N y ).

[0124] The pixel defining layer 50 may include a light absorbing material. The pixel defining layer 50 may include a black colorant. The black colorant may include a black pigment or a black dye. The black colorant may include carbon black, a metal material such as chromium, or an oxide of a metal material.

[0125] The light emitting layer EML may be positioned on the first electrode AE. The light emitting layer EML may be positioned in a region corresponding to a light emitting opening defined through the pixel defining layer 50. That is, the light emitting layer EML may be provided to a plurality of pixels PX (refer to Figure 4 ), and when viewed in a plan view, the light emitting layer EML of the pixel PX can be provided in the form of a light emitting pattern to be provided individually in each pixel. Unlike the common layer, the light emitting layer EML can be formed by a deposition process using a patterned mask (e.g., a fine metal mask (FMM)).

[0126] The light emitting layer EML may provide (or emit) light having a color (e.g., a set or predetermined color). The light emitting layer EML may emit light having one color of red, blue, and green, however, it should not be limited thereto or thereby. The light emitting layer EML may generate white light by a combination of light emitting materials that generate red, green, and blue, respectively.

[0127] The light-emitting layer EML may include an organic light-emitting material and / or an inorganic light-emitting material. As an example, the light-emitting layer EML may include a fluorescent or phosphorescent material, an organic metal composite light-emitting material, or a quantum dot. The light-emitting layer EML may have a multilayer structure. As an example, the light-emitting layer EML may include a main light-emitting layer and an auxiliary light-emitting layer positioned on the main light-emitting layer. Depending on the wavelength of light emitted from the main light-emitting layer and the auxiliary light-emitting layer, the main light-emitting layer and the auxiliary light-emitting layer may have different thicknesses, and the resonance distance of the light-emitting element OL may be controlled by providing an auxiliary light-emitting layer. In addition, since the auxiliary light-emitting layer is provided, the color purity of the light emitted from the light-emitting layer EML may be improved.

[0128] The second electrode CE may be positioned on the light emitting layer EML. The second electrode CE may extend over the pixel PX (refer to Figure 4) are commonly arranged to receive a common voltage. The second electrode CE may extend from the second area A2 and may be arranged to overlap at least a portion of the dam area A1-D, however, it should not be limited thereto or thereby. The common layer may extend from the second area A2 to the edge area A1-M via the dam area A1-D, and the present disclosure should not be particularly limited thereto.

[0129] Each of the first electrode AE ​​and the second electrode CE may be a transmissive electrode, a semi-transmissive reflective electrode or a reflective electrode. The transmissive electrode may include a transparent metal oxide (e.g., indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), etc.). The semi-transmissive reflective electrode or the reflective electrode may include Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, LiF, Mo, Ti, Yb, W and a compound thereof, or a mixture thereof (e.g., AgMg, AgYb or MgYb), or a material having a stack structure of LiF and Ca or a stack structure of LiF and Al.

[0130] Each of the first electrode AE ​​and the second electrode CE may have a multilayer structure of a reflective layer or a semi-transmissive layer formed of the above-mentioned material, and a transparent conductive layer formed of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium tin zinc oxide (ITZO). As an example, the first electrode AE ​​and the second electrode CE having the multilayer structure may have a three-layer structure of ITO / Ag / ITO, however, it should not be limited thereto or thereby.

[0131] The encapsulation layer TFE may be positioned on the light emitting element OL and may cover (encapsulate) the light emitting element OL. The encapsulation layer TFE may include at least one insulating layer. The encapsulation layer TFE may include a first inorganic layer IOL1 and a second inorganic layer IOL2, and at least one organic layer MN positioned between the first inorganic layer IOL1 and the second inorganic layer IOL2. The first inorganic layer IOL1 may be positioned on the second electrode CE. The organic layer MN and the second inorganic layer IOL2 may be sequentially arranged on the first inorganic layer IOL1.

[0132] The first inorganic layer IOL1 and the second inorganic layer IOL2 can protect the light emitting element OL from moisture and / or oxygen. The first inorganic layer IOL1 and the second inorganic layer IOL2 can each include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. However, the materials used for the first inorganic layer IOL1 and the second inorganic layer IOL2 should not be limited thereto.

[0133] The organic layer MN may protect the light emitting element OL from foreign substances such as dust particles. The organic layer MN may include an acrylic-based resin. However, it should not be limited thereto or thereby.

[0134] The organic layer MN has a thickness that may be equal to or greater than about 5 um and equal to or less than about 10 um. According to the present disclosure, since the cover layer PVX including an organic material is positioned in the second area A2 and the dam area A1-D, the thickness of the organic layer MN may be reduced. Therefore, the ripples of the display module 100 may be improved. The ripples of the display module 100 will be described in more detail later.

[0135] According to some embodiments, the display module 100 may include a cover layer PVX. According to some embodiments, the cover layer PVX may be positioned directly on the second inorganic layer IOL2. The cover layer PVX may overlap the second area A2 and the dam area A1-D, and may be spaced apart from the edge area A1-M. The cover layer PVX may include an organic material.

[0136] The cover layer PVX may be formed on the encapsulation layer TFE by a photoresist process. The cover layer PVX may provide a flat surface for components positioned on the cover layer PVX. According to the present invention, the cover layer PVX overlapping the second area A2 may have a thickness equal to or greater than about 2um and equal to or less than about 5um. The portion of the cover layer PVX overlapping the dam area A1-D of the first area A1 has a thickness greater than the thickness of the portion of the cover layer PVX overlapping the second area A2.

[0137] According to the present disclosure, the cover layer PVX may be spaced apart from the edge region A1-M and the hole processing region A1-H, and therefore, a process of removing the organic layer overlapping the hole processing region A1-H and providing a flat surface (e.g., a pre-ablation process performed before the laser beam is irradiated onto the base layer SUB) may be omitted in the process of forming the module hole MH. This will be described in detail later.

[0138] The anti-reflection layer ARL may be positioned on the cover layer PVX. The anti-reflection layer ARL may be positioned between the cover layer PVX and the window 300. The anti-reflection layer ARL may reduce the reflection of external light incident thereto from the outside of the electronic device 1000. That is, the anti-reflection layer ARL may reduce the reflectivity of the electronic device 1000 relative to external light. The anti-reflection layer ARL may include a polarizer, a retarder, a destructive interference structure, or a plurality of color filters.

[0139] The first adhesive layer AD1 may be positioned between the anti-reflection layer ARL and the cover layer PVX and may attach the anti-reflection layer ARL to the cover layer PVX. The first adhesive layer AD1 may include at least one of an optically clear adhesive, an optically clear adhesive resin, and a pressure sensitive adhesive (PSA).

[0140] The window 300 may be positioned on the anti-reflection layer ARL. The second adhesive layer AD2 may be positioned between the anti-reflection layer ARL and the window 300, and may attach the anti-reflection layer ARL to the window 300. The second adhesive layer AD2 may include the same material as that of the first adhesive layer AD1.

[0141] The window 300 may further include a bezel pattern CBM positioned on the rear surface of the window 300. The bezel pattern CBM may be printed or colored on the rear surface of the window 300, or may be attached to the rear surface of the window 300 by a separate adhesive layer.

[0142] The bezel pattern CBM may be positioned in the first area A1, and may be provided with an opening defined through the bezel pattern CBM to correspond to the module hole MH. The bezel pattern CBM may prevent unnecessary external light from being incident on the electronic module 400, and thus, the performance of the electronic module 400 may be improved. In addition, the bezel pattern CBM may prevent the components positioned in the first area A1 from being perceived by the user. The bezel pattern CBM may include a material that blocks light, and the material used for the bezel pattern CBM should not be particularly limited.

[0143] The module hole MH may be defined through the display module 100. The module hole MH may correspond to the hole processing area A1-H of the first area A1. According to the present disclosure, the position, number, and shape of the module hole MH defined in the display module 100 may correspond to the position, number, and shape of the electronic module 400 positioned below the base layer SUB. The electronic module 400 may overlap with the module hole MH. According to the present disclosure, since the electronic module 400 is arranged to overlap with the active area AA (refer to Figure 2 ) overlap, so the NAA in the peripheral area (refer to Figure 2 ) to arrange the electronic module 400. Therefore, the peripheral area NAA (refer to Figure 2 ) can be reduced.

[0144] The module hole MH may be formed through the base layer SUB, the circuit element layer, the display element layer, and the encapsulation layer TFE overlapping the hole processing area A1-H of the first area A1 of the display panel 110. Figure 4The described filling portion may be a polymer resin filled in an inner space between the base layer SUB and the window 300 formed by the circuit element layer, the display element layer, and the encapsulation layer TFE except the base layer SUB in a process of forming the module hole MH.

[0145] According to some embodiments, at least a portion of the bezel pattern CBM may be exposed without being covered by the first adhesive layer AD1, the second adhesive layer AD2, and the anti-reflection layer ARL, and an opening may be defined through the first adhesive layer AD1, the second adhesive layer AD2, and the anti-reflection layer ARL to correspond to the opening defined through the bezel pattern CBM. A portion of the second adhesive layer AD2 may cover a portion of the bezel pattern CBM.

[0146] The circuit element layer of the display panel 110 may further include a dam pattern DMP positioned in the dam area A1-D of the first area A1. The dam pattern DMP may be positioned between the module hole MH and the second area A2 and may surround the module hole MH. The dam pattern DMP may be provided in plurality and may have different widths and heights from each other.

[0147] As an example, the dam pattern DMP may include a first portion DM1, a second portion DM2, a third portion DM3, and a fourth portion DM4 sequentially stacked. Each of the first portion DM1, the second portion DM2, the third portion DM3, and the fourth portion DM4 may include an organic material. As an example, at least one of the first portion DM1, the second portion DM2, the third portion DM3, and the fourth portion DM4 may include the same material as an insulating layer including an organic material among the first insulating layer 10, the second insulating layer 20, the third insulating layer 30, and the fourth insulating layer 40.

[0148] According to some embodiments, in at least one dam pattern DMP, one of the first portion DM1, the second portion DM2, the third portion DM3, and the fourth portion DM4 may be omitted, and thus, the at least one dam pattern DMP may have a two-layer or three-layer structure. However, it should not be particularly limited.

[0149] A portion of the dam pattern DMP may be covered by the second electrode CE. The other portion of the dam pattern DMP may be covered by the first inorganic layer IOL1 of the encapsulation layer TFE. The dam pattern DMP may define a boundary of the organic layer MN in the dam area A1-D. Thus, the organic layer MN may be arranged along the dam pattern DMP to surround the module hole MH. At least one of the plurality of dam patterns DMP may include protruding patterns U-1 and U-2 and lower patterns B-1 and B-2.

[0150] The lower opening 30-OP may be defined between the first portions DM1 adjacent to each other to expose the second insulating layer 20, and the upper opening 40-OP may be defined between the second portions DM2 adjacent to each other to correspond to the lower opening 30-OP and expose the second insulating layer 20. In the present disclosure, the lower opening 30-OP and the upper opening 40-OP overlapping each other may be defined as one tip opening.

[0151] Each of the protruding patterns U-1 and U-2 may include one side UE and another side UC. The one side UE of the first protruding pattern U-1 may protrude between the side surface of the first portion DM1 and the side surface of the second portion DM2 of the dam pattern DMP defining the tip opening, and the other side UC of the first protruding pattern U-1 may be positioned between the first portion DM1 and the second portion DM2. The one side UE of the first protruding pattern U-1 protruding between the side surface of the first portion DM1 and the side surface of the second portion DM2 may be covered by the first inorganic layer IOL1.

[0152] A portion of the first protruding pattern U- 1 positioned between the first portion DM1 and the second portion DM2 may be connected to the corresponding first lower pattern B- 1 via a contact hole 30 -H defined through the first portion DM1 .

[0153] One side UE of the second protruding pattern U-2 may protrude between a side surface of the first portion DM1 defining the tip opening and a side surface of the second portion DM2 of the dam pattern DMP, and the other side UC of the second protruding pattern U-2 may be positioned between the first portion DM1 and the second portion DM2. One side UE of the second protruding pattern U-2 protruding between the side surfaces of the first portion DM1 and the second portion DM2 may be covered by the first inorganic layer IOL1.

[0154] A portion of the second protruding pattern U- 2 positioned between the first portion DM1 and the second portion DM2 may be connected to the corresponding second lower pattern B- 2 via a contact hole 30 -H defined through the first portion DM1 .

[0155] The circuit element layer may include a tip portion TIP. One tip portion TIP may be defined by a lower opening 30-OP, an upper opening 40-OP, and a side UE each protruding from a corresponding tip opening of different protrusion patterns U-1 and U-2. The side UEs respectively included in different protrusion patterns U-1 and U-2 of the tip portion TIP may face each other.

[0156] The circuit element layer may further include a half tip portion TIPa. The half tip portion TIPa may be defined by only one of the sides UE of the protrusion patterns U-1 and U-2 protruding from the corresponding tip opening. Figure 5Two tip portions TIP and two half tip portions TIPa are shown as representative examples, however, the number of the tip portions TIP and the number of the half tip portions TIPa should not be particularly limited, and the half tip portion TIPa may be omitted.

[0157] The tip portion TIP and the semi-tip portion TIPa may surround the module hole MH, and when viewed in a plan view, the tip portion TIP and the semi-tip portion TIPa may have a closed line shape. Figure 4 The tip portion TIP described may correspond to reference Figure 5 One of the tip portion TIP and the semi-tip portion TIPa described.

[0158] The floating patterns CP may be positioned in the corresponding tip openings, respectively. The floating pattern CP may include the same material as the common layer. As an example, the floating pattern CP may include the same material as at least one of the second electrode CE, the hole control layer, and the electron control layer. The floating pattern CP may correspond to a portion of the common layer that is disconnected due to the tip portion TIP and the semi-tip portion TIPa in a process of forming the common layer throughout the active area AA.

[0159] According to the present disclosure, as the floating pattern CP including the same material as the common layer is disconnected by the tip portion TIP and the semi-tip portion TIPa, a path through which moisture and / or oxygen enters the light emitting element OL from the module hole MH can be blocked. Therefore, even if the module hole MH is defined in the active area AA, the display quality of the display panel 110 can be improved.

[0160] Figure 6 is a cross-sectional view showing a display module 100 according to some embodiments of the present disclosure. Figure 6 In the same / similar reference numerals, Figures 1 to 5 , and thus, detailed description of the same / similar elements will be omitted.

[0161] The electronic device 1000-a may include a display module 100, a housing 200 (see Figure 2 ), window 300 and electronic module 400. In the following, the description will focus on reference Figure 5 The display module 100 described Figure 6 The differences between the display modules 100 are shown in FIG.

[0162] The display module 100 may include a display panel 110 , an intermediate layer SIL, a cover layer PVX, a first adhesive layer AD1 , an anti-reflection layer ARL, and a second adhesive layer AD2 .

[0163] The display panel 110 may include a circuit element layer including a base layer SUB, a transistor TR and insulating layers 10 , 20 , 30 , and 40 , a display element layer including a pixel defining layer 50 and a light emitting element OL, and an encapsulation layer TFE.

[0164] The intermediate layer SIL may be positioned on the display panel 110. As an example, the intermediate layer SIL may be positioned on the second inorganic layer IOL2. The intermediate layer SIL may be positioned in the second area A2, and in an area other than the hole processing area A1-H of the first area A1.

[0165] The intermediate layer SIL may include an inorganic material. As an example, the intermediate layer SIL may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide.

[0166] According to some embodiments, the cover layer PVX may be directly positioned on the intermediate layer SIL. The cover layer PVX may overlap with the second area A2 and the dam area A1-D, and the cover layer PVX may be spaced apart from the edge area A1-M. The cover layer PVX may include an organic material. The cover layer PVX may be formed on the intermediate layer SIL by a photoresist process. The cover layer PVX may provide a flat surface for a component positioned on the cover layer PVX.

[0167] Figure 7 is a cross-sectional view showing a display module 100 according to some embodiments of the present disclosure. Figure 7 In the same / similar reference numerals, Figures 1 to 5 , and thus, detailed description of the same / similar elements will be omitted.

[0168] The electronic device 1000-b may include a display module 100, a housing 200 (see Figure 2 ), window 300 and electronic module 400. In the following, the description will focus on reference Figure 5 The display module 100 described Figure 7 The differences between the display modules 100 are shown in FIG.

[0169] The display module 100 may include a display panel 110 , an input sensor 120 , a cover layer PVX, a first adhesive layer AD1 , an anti-reflection layer ARL, and a second adhesive layer AD2 .

[0170] The display panel 110 may include a circuit element layer including a base layer SUB, a transistor TR and insulating layers 10, 20, 30 and 40, a display element layer including a pixel defining layer 50 and a light emitting element OL, and an encapsulation layer TFE. According to some embodiments, the input sensor 120 may correspond to the reference Figure 3 An input sensor 120 is described.

[0171] The input sensor 120 may sense a user input TC (refer to Figure 1 ). User input TC (refer to Figure 1 ) can include various types of external input such as a part of the user's body, light, heat, a pen, or pressure.

[0172] The input sensor 120 may be positioned on the display panel 110. As an example, the input sensor 120 may be formed directly on the encapsulation layer TFE. The input sensor 120 may include conductive patterns MTL1 and MTL2 and sensing insulation layers TIL1, TIL2, and TIL3. The sensing insulation layers TIL1, TIL2, and TIL3 may include a first sensing insulation layer TIL1, a second sensing insulation layer TIL2, and a third sensing insulation layer TIL3. The conductive patterns MTL1 and MTL2 may overlap with the pixel defining layer 50, and the conductive patterns MTL1 and MTL2 may be spaced apart from an opening defined through the pixel defining layer 50.

[0173] The first sensing insulating layer TIL1 may be positioned directly on the encapsulation layer TFE. The second sensing insulating layer TIL2 may be positioned on the first sensing insulating layer TIL1. The first conductive pattern MTL1 may be positioned on the second sensing insulating layer TIL2, and may be covered by the third sensing insulating layer TIL3.

[0174] The second conductive pattern MTL2 may be positioned on the third sensing insulating layer TIL3. According to some embodiments, the second conductive pattern MTL2 included in the input sensor 120 may be covered by the cover layer PVX.

[0175] Each of the conductive patterns MTL1 and MTL2 may have conductivity. Each of the conductive patterns MTL1 and MTL2 may have a single layer or multilayer structure and should not be particularly limited. When viewed in a plan view, at least one of the conductive patterns MTL1 and MTL2 may be provided in the form of a grid line.

[0176] The grid lines forming the conductive patterns MTL1 and MTL2 may overlap the pixel defining layer 50 and may be spaced apart from the light emitting layer EML. Therefore, although the input sensor 120 is directly formed on the display panel 110, the pixels PX (refer to Figure 2 )The light generated can be provided to the user without being interfered with by the input sensor 120.

[0177] The cover layer PVX may be positioned on the third sensing insulating layer TIL3 and may cover the second conductive pattern MTL2. The cover layer PVX may compensate for a step difference occurring in the display panel 110. Thus, a flat surface may be provided on a component positioned on the display panel 110. The cover layer PVX may include an organic material.

[0178] According to some embodiments, the first and third sensing insulating layers TIL1 and TIL3 may overlap the second area A2 and the dam area A1-D and may be spaced apart from the edge area A1-M. The first and third sensing insulating layers TIL1 and TIL3 may include an organic material.

[0179] According to some embodiments, each of the thickness of the first sensing insulation layer TIL1 and the thickness of the third sensing insulation layer TIL3 in the second area A2 may be greater than the thickness of the cover layer PVX in the second area A2.

[0180] The second sensing insulating layer TIL2 may extend from the second region A2 to the edge region A1-M via the dam region A1-D. Therefore, one end of the second sensing insulating layer TIL2 adjacent to the boundary between the edge region A1-M and the hole processing region A1-H may be exposed to the outside through the module hole MH. The second sensing insulating layer TIL2 may include an inorganic material.

[0181] According to some embodiments, the first sensing insulating layer TIL1, the third sensing insulating layer TIL3 and the covering layer PVX may be formed by a photoresist process. Therefore, the first sensing insulating layer TIL1, the third sensing insulating layer TIL3 and the covering layer PVX may overlap with the second area A2 and the dam area A1-D, and may be spaced apart from the edge area A1-M. Therefore, the path through which moisture / oxygen entering from the module hole MH moves along the first sensing insulating layer TIL1, the third sensing insulating layer TIL3 and the covering layer PVX including organic materials may be blocked. Therefore, the display quality of the electronic device 1000-b may be improved.

[0182] Figures 8 to 12 is a cross-sectional view illustrating a method of manufacturing an electronic device according to some embodiments of the present disclosure. Figures 8 to 12 shows the manufacturing reference Figure 5 The process of the electronic device 1000 is described. Figures 8 to 12 In the same / similar reference numerals, Figures 1 to 5 The same / similar elements in FIG. 1 and thus, their details will be omitted.

[0183] Reference Figure 8 And combined with Figure 5, the method of manufacturing the electronic device 1000 may include providing a display panel 110. The display panel 110 may be provided in a state where a circuit element layer including a base layer SUB, a transistor TR and insulating layers 10, 20, 30 and 40, a display element layer including a pixel defining layer 50 and a light emitting element OL, and an encapsulation layer TFE are formed therein.

[0184] The base layer SUB may include a first area A1 and a second area A2 surrounding the first area A1 (refer to Figure 2 The first area A1 may include a dam area A1-D, an edge area A1-M, and a hole processing area A1-H. The dam area A1-D may be defined as being adjacent to the second area A2 (refer to Figure 2 The edge region A1-M may be positioned between the dam region A1-D and the hole processing region A1-H.

[0185] The encapsulation layer TFE may include first and second inorganic layers IOL1 and IOL2 and at least one organic layer MN positioned between the first and second inorganic layers IOL1 and IOL2. The first and second inorganic layers IOL1 and IOL2 may contact each other in the edge region A1-M.

[0186] Then, the method of manufacturing the electronic device 1000 may include forming a preliminary cover layer PVX-a (referred to as a cover layer in the claims) on the display panel 110. The preliminary cover layer PVX-a may be formed by completely coating an organic material throughout the first and second areas A1 and A2.

[0187] Thereafter, the method of manufacturing the electronic device 1000 may include patterning the initial cover layer PVX-a. The initial cover layer PVX-a may be patterned by a photoresist process. Therefore, the photoresist process may be performed after positioning the photomask PR over the initial cover layer PVX-a so that the photomask PR overlaps the edge region A1-M and the hole processing region A1-H.

[0188] refer to Fig. 9 , the initial covering layer PVX-a (refer to Figure 8 ) is patterned to form a cover layer PVX through which an opening P-OP is defined. The initial cover layer PVX-a overlapping the edge region A1-M and the hole processing region A1-H may be removed by a photoresist process to form the opening P-OP. Therefore, the second inorganic layer IOL2 overlapping the edge region A1-M and the hole processing region A1-H may be exposed through the opening P-OP.

[0189] Then, the method of manufacturing the electronic device 1000 may include irradiating a laser beam onto the rear surface SB of the base layer SUB. The laser beam may be irradiated onto the rear surface SB of the base layer SUB along the boundary between the edge area A1-M and the hole processing area A1-H using a laser unit LS positioned above the rear surface SB of the base layer SUB. This may be to form the module hole MH in the display panel 110 (refer to Figure 5 )’s preliminary work.

[0190] Reference Fig.10 and Fig.11 , the method of manufacturing the electronic device 1000 may include forming a module hole MH. After irradiating the laser beam, an etchant may be sprayed to the region irradiated with the laser beam to form the module hole MH. The etchant may be sprayed to the region irradiated with the laser beam while the spray unit EA positioned above the rear surface SB of the base layer SUB moves along the region irradiated with the laser beam.

[0191] Reference Fig.12 , the method of manufacturing the electronic device 1000 may further include coupling the anti-reflection layer ARL. The anti-reflection layer ARL may be coupled to the cover layer PVX through the first adhesive layer AD1. An opening may be defined through the first adhesive layer AD1 and the anti-reflection layer ARL to overlap with the opening P-OP.

[0192] Then, the method of manufacturing the electronic device 1000 may further include coupling the window 300. The window 300 may be coupled to the anti-reflection layer ARL through the second adhesive layer AD2. A frame pattern CBM may be formed on the rear surface of the window 300 overlapping the first area A1. The frame pattern CBM may be provided with an opening defined therethrough and overlapping the module hole MH. The second adhesive layer AD2 may be provided with an opening defined therethrough and overlapping the opening P-OP, and the frame pattern CBM may be exposed through the opening defined by the first adhesive layer AD1, the anti-reflection layer ARL, and the second adhesive layer AD2.

[0193] According to the present disclosure, since the thickness of the organic layer MN is in the second area A2 (refer to Figure 5 ) is limited to a range from about 5 um or more to about 10 um or less, and thus ripples generated when the thickness of the organic layer MN varies in the dam area A1-D can be improved. In addition, the electronic device 1000 may include a plurality of organic layers located only in the second area A2 (refer to Figure 2 ) and the cover layer PVX in the dam area A1-D and spaced apart from the edge area A1-M and the hole processing area A1-H, and therefore, in the process of forming the module hole MH, the pre-ablation process required to remove the organic layer formed by the inkjet process can be omitted. Therefore, the manufacturing cost in the method of manufacturing an electronic device can be reduced.

[0194] Figures 13 to 17 is a cross-sectional view illustrating a method of manufacturing an electronic device according to some embodiments of the present disclosure. Figures 13 to 17 shows the manufacturing reference Figure 7 The process of the electronic device 1000-b is described. Figures 13 to 17 In the same / similar reference numerals, Figures 1 to 12 The same / similar elements in FIG. 1 and thus, their details will be omitted.

[0195] Reference Fig.13 And combined with Figure 7 , the method of manufacturing the electronic device 1000-b may include providing a display panel 110. The display panel 110 may be provided in a state where a circuit element layer including a base layer SUB, a transistor TR and insulating layers 10, 20, 30 and 40, a display element layer including a pixel defining layer 50 and a light emitting element OL, and an encapsulation layer TFE are formed.

[0196] The base layer SUB may include a first area A1 and a second area A2 surrounding the first area A1 (refer to Figure 2 The first area A1 may include a dam area A1-D, an edge area A1-M, and a hole processing area A1-H. The dam area A1-D may be defined as being adjacent to the second area A2 (refer to Figure 2 The edge region A1-M may be positioned between the dam region A1-D and the hole processing region A1-H.

[0197] Then, the method of manufacturing the electronic device 1000-b may further include forming the input sensor 120. The input sensor 120 may be formed on the display panel 110 through a continuous process. Therefore, the first sensing insulating layer TIL1 may be directly formed on the second inorganic layer IOL2. Figure 2 ) completely coats an organic material and patterns the organic material using a photoresist process to form a first sensing insulating layer TIL1.

[0198] Forming the input sensor 120 may include forming a second sensing insulating layer TIL2 on the first sensing insulating layer TIL1. Figure 2 ) completely coats an inorganic material and patterns the inorganic material using a photoresist process to form a second sensing insulating layer TIL2.

[0199] Thereafter, the method of manufacturing the electronic device 1000-b may include forming a first conductive pattern MTL1 (refer to Figure 7). The second sensing insulating layer TIL2 may be coated with a material including a metal material and the material may be bonded to the pixel defining layer 50 (refer to Figure 7 ) is patterned to form a first conductive pattern MTL1 (refer to Figure 7 ).

[0200] The method of manufacturing the electronic device 1000-b may include forming a third sensing insulating layer TIL3 on the second sensing insulating layer TIL2. Figure 2 ) completely coats an organic material and patterns the organic material through a photoresist process to form a third sensing insulation layer TIL3.

[0201] The method of manufacturing the electronic device 1000-b may include forming a second conductive pattern MTL2 (refer to Figure 7 ). The third sensing insulating layer TIL3 may be formed by coating a material including a transparent metal oxide material on the third sensing insulating layer TIL3 and separating the transparent metal oxide material from the pixel defining layer 50 (refer to Figure 7 ) is patterned to form a second conductive pattern MTL2 (refer to Figure 7 ). When viewed in a plan view, the second conductive pattern MTL2 (refer to Figure 7 ) can have a lattice shape or a grid shape.

[0202] The method of manufacturing the electronic device 1000-b may include forming a preliminary cover layer PVX-a (referred to as a cover layer in the claims) on the input sensor 120. The preliminary cover layer PVX-a may be formed by completely coating an organic material throughout the first area A1 and the second area A2.

[0203] The method of manufacturing the electronic device 1000-b may include patterning the initial cover layer PVX-a. The initial cover layer PVX-a may be patterned by a photoresist process. Therefore, the photoresist process may be performed after positioning the photomask PR above the initial cover layer PVX-a so that the photomask PR overlaps the edge region A1-M and the hole processing region A1-H.

[0204] Reference Fig.14 According to the method of manufacturing the electronic device 1000-b, the initial cover layer PVX-a (refer to Fig.13) is patterned, and thus, a cover layer PVX through which an opening P-OP is defined may be formed. The initial cover layer PVX-a overlapping the edge region A1-M and the hole processing region A1-H may be removed by a photoresist process to form the opening P-OP. Thus, the second inorganic layer IOL2 overlapping the edge region A1-M and the hole processing region A1-H may be exposed through the opening P-OP.

[0205] The method of manufacturing the electronic device 1000-b may include irradiating a laser beam onto the rear surface SB of the base layer SUB. The laser beam may be irradiated onto the rear surface SB of the base layer SUB along the boundary between the edge area A1-M and the hole processing area A1-H using a laser unit LS positioned above the rear surface SB of the base layer SUB. This may be a method of forming a module hole MH in the display panel 110 (refer to Figure 7 )’s preliminary work.

[0206] Reference Fig.15 and Fig.16 , the method of manufacturing the electronic device 1000-b may include forming a module hole MH. After irradiating the laser beam, an etchant may be sprayed to the area irradiated with the laser beam to form the module hole MH. The etchant may be sprayed to the area irradiated with the laser beam while the spray unit EA positioned above the back surface SB of the base layer SUB moves along the area irradiated with the laser beam.

[0207] Reference Fig.17 , the method of manufacturing the electronic device 1000-b may further include coupling an anti-reflection layer ARL. The anti-reflection layer ARL may be coupled to the cover layer PVX through the first adhesive layer AD1. An opening may be defined through the first adhesive layer AD1 and the anti-reflection layer ARL to overlap with the opening P-OP.

[0208] Then, the method of manufacturing the electronic device 1000-b may further include coupling the window 300. The window 300 may be coupled to the anti-reflection layer ARL through the second adhesive layer AD2. A border pattern CBM may be formed on the rear surface of the window 300 overlapping the first area A1. The border pattern CBM may be provided with an opening defined therethrough and overlapping the module hole MH. The second adhesive layer AD2 may be provided with an opening defined therethrough and overlapping the opening P-OP, and the border pattern CBM may be exposed through the opening defined by the first adhesive layer AD1, the anti-reflection layer ARL, and the second adhesive layer AD2.

[0209] Although the embodiments of the present disclosure have been described, it should be understood that the present disclosure should not be limited to these embodiments, but various changes and modifications may be made by one of ordinary skill in the art within the spirit and scope of the present disclosure as claimed in the appended claims.

[0210] Thus, the disclosed subject matter should not be limited to any single embodiment described herein, and the scope of the inventive concept should be determined in accordance with the following claims and their equivalents.

Claims

1. An electronic device, in, The electronic device comprises: A display panel, comprising a base layer, a pixel and an encapsulation layer, the base layer comprising a first area and a second area surrounding the first area, the pixel overlapping the second area on the base layer, the encapsulation layer covering the pixel, and the encapsulation layer being provided with a module hole defined through the encapsulation layer and overlapping the first area; a cover layer comprising an organic material and on the display panel; an anti-reflection layer on the cover layer; an electronic module overlapping the module hole; and a window, on the anti-reflection layer, The first region includes a dam region adjacent to the second region and surrounding the module hole, and an edge region between the module hole and the dam region, and the cover layer overlaps the dam region and the second region and is spaced apart from the edge region.

2. The electronic device according to claim 1, in, A portion of the cover layer overlapping the second region has a thickness equal to or greater than 2 micrometers and equal to or less than 5 micrometers.

3. The electronic device according to claim 1, in, A portion of the cover layer overlapping the dam region of the first region has a thickness greater than a thickness of the portion of the cover layer overlapping the second region.

4. The electronic device according to claim 1, in, The encapsulation layer comprises: A first inorganic layer covering the pixel; a second inorganic layer on the first inorganic layer; and The organic layer is between the first inorganic layer and the second inorganic layer.

5. The electronic device according to claim 4, in, The capping layer is in contact with the second inorganic layer.

6. The electronic device according to claim 4, in, The first inorganic layer and the second inorganic layer contact each other in the edge region.

7. The electronic device according to claim 4, in, The display panel further includes an intermediate layer between the second inorganic layer and the cover layer and extending from the second region to the edge region via the dam region, and the intermediate layer includes an inorganic material.

8. The electronic device according to claim 4, in, The organic layer overlapping the second region has a thickness equal to or greater than 5 micrometers and equal to or less than 10 micrometers.

9. The electronic device according to claim 4, in, The electronic device further comprises an input sensor, wherein the input sensor comprises: A first sensing insulating layer, on the packaging layer; a second sensing insulating layer, on the first sensing insulating layer; A first conductive layer, on the second sensing insulating layer; a third sensing insulating layer covering the first conductive layer and on the second sensing insulating layer; and A second conductive layer is on the third sensing insulating layer, wherein the covering layer covers the second conductive layer and is on the third sensing insulating layer.

10. The electronic device according to claim 9, in, The first and third sensing insulating layers overlap the second region and the dam region, are spaced apart from the edge region, and the second sensing insulating layer extends from the second region to the edge region via the dam region.

11. The electronic device according to claim 10, in, Each of a thickness of the first sensing insulating layer and a thickness of the third sensing insulating layer is greater than a thickness of the capping layer.

12. The electronic device according to claim 11, in, The first sensing insulating layer and the third sensing insulating layer include an organic material, and the second sensing insulating layer includes an inorganic material.

13. The electronic device according to claim 4, in, The electronic device further includes a plurality of dam patterns in the dam region and surrounding the module hole, wherein each of the plurality of dam patterns includes a tip portion protruding from a side surface of a corresponding one of the plurality of dam patterns and including a conductive material.

14. The electronic device according to claim 13, in, The tip portion is covered by the first inorganic layer.

15. The electronic device according to claim 13, in, A boundary of the organic layer in the dam region is defined by one of the plurality of dam patterns.

16. The electronic device according to claim 1, in, The electronic device further comprises: a first adhesive layer between the cover layer and the anti-reflection layer; and A second adhesive layer is between the anti-reflection layer and the window, wherein the first adhesive layer and the second adhesive layer each include at least one of an optically clear adhesive, an optically clear adhesive resin, and a pressure-sensitive adhesive.

17. The electronic device according to claim 1, in, The window includes a bezel pattern on a rear surface of the window overlapping the first area, and the bezel pattern is provided with an opening defined through the bezel pattern and overlapping the module hole.

18. A method of manufacturing an electronic device, in, The method comprises: A display panel is provided, the display panel comprising a base layer, a pixel and an encapsulation layer, a first region including a hole processing region, an edge region surrounding the hole processing region and a dam region surrounding the edge region is defined in the base layer, the pixel is formed on the base layer, and the encapsulation layer covers the pixel; coating an organic material on the display panel to form a covering layer; patterning the cover layer, the cover layer overlapping the hole processing area and the edge area; irradiating a laser beam onto the rear surface of the base layer along a boundary between the hole processing region and the edge region; and An etchant is sprayed toward the boundary to form a module hole, wherein the patterning of the capping layer is performed by a photoresist process.

19. The method according to claim 18, in, The encapsulation layer includes a first inorganic layer, an organic layer on the first inorganic layer, and a second inorganic layer on the organic layer, the first inorganic layer and the second inorganic layer contact each other in the edge region, and in the patterning of the covering layer, the second inorganic layer overlapping the edge region is exposed via an opening formed through the covering layer.

20. The method according to claim 19, in, The organic layer has a thickness equal to or greater than 5 micrometers and equal to or less than 10 micrometers, and the capping layer has a thickness equal to or greater than 2 micrometers and equal to or less than 5 micrometers.

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