Eye pattern jitter analysis method and system for oscilloscope

Abstract

The invention belongs to the technical field of oscilloscope testing, and particularly relates to an oscilloscope eye pattern jitter analysis method and system, and the method comprises the steps: obtaining to-be-analyzed oscilloscope signal data; extracting clock information in the obtained signal data to obtain a data clock signal; carrying out synchronization processing on the obtained signal data based on the obtained data clock signal to obtain a synchronous data signal; superposing the obtained synchronous data signals to generate an oscilloscope eye diagram; and analyzing the generated oscilloscope eye diagram by adopting a self-adaptive window function and a peak valley detection method to obtain eye diagram jitter information. By analyzing and processing oscilloscope signal data, the precision and speed of complex signal jitter analysis are improved, and the requirement for real-time analysis of oscilloscope signals is further met.

Description

Technical Field

[0001] The invention belongs to the technical field of oscilloscope testing, and in particular relates to an eye diagram jitter analysis method and system for an oscilloscope. Background Art

[0002] The statements in this section merely provide background information related to the present invention and do not necessarily constitute prior art.

[0003] In high-speed communication systems, oscilloscope eye diagram analysis and jitter measurement are important means of evaluating signal quality. An eye diagram is a graph of a series of digital signals accumulated on an oscilloscope. It is used to show the superposition effect of digital signals in multiple cycles and reflect the overall characteristics of digital signals. Based on the eye diagram, the influence of inter-symbol crosstalk and noise can be obtained, which can help engineers observe the noise, distortion and jitter of digital signals. Jitter refers to the deviation of the signal from the ideal clock position and is a key factor affecting the performance of the communication system.

[0004] Traditional analysis methods usually rely on complex hardware equipment, such as high-performance oscilloscopes, and time-consuming software algorithms, such as Fourier transform-based jitter analysis. These methods may face problems such as poor real-time performance and limited analysis accuracy when processing high-speed serial signals, especially when dealing with non-periodic jitter.

[0005] According to the inventors, the existing eye diagram jitter analysis process is: signal capture (using an oscilloscope or other test equipment to capture high-speed serial signals), data preprocessing (filtering and amplifying the captured signals to reduce noise), clock recovery (recovering the clock signal from the signal through software PLL or other algorithms), bit alignment (using the clock signal to bit-align the data), eye diagram generation (superimposing the aligned signal waveforms to form an eye diagram), jitter analysis (calculating the deterministic jitter and random jitter of the signal based on Fourier transform or other statistical methods). However, this traditional method has high computational complexity and slow processing speed, and cannot meet the needs of real-time analysis; at the same time, the jitter analysis accuracy of complex signals is limited, which may lead to misjudgment; in addition, the high cost of hardware equipment limits the popularity and application of eye diagram analysis. Summary of the invention

[0006] To solve the above problems, the present invention proposes an oscilloscope eye diagram jitter analysis method and system. The present invention improves the accuracy and speed of complex signal jitter analysis by analyzing and processing oscilloscope signal data, further meeting the needs of real-time analysis of oscilloscope signals.

[0007] According to some embodiments, a first solution of the present invention provides an eye diagram jitter analysis method for an oscilloscope, which adopts the following technical solution:

[0008] An eye diagram jitter analysis method for an oscilloscope, comprising:

[0009] Obtain oscilloscope signal data to be analyzed;

[0010] Extracting clock information from the acquired signal data to obtain a data clock signal;

[0011] Perform synchronization processing on the acquired signal data based on the obtained data clock signal to obtain a synchronous data signal;

[0012] The resulting synchronous data signals are superimposed to generate an oscilloscope eye diagram;

[0013] The generated oscilloscope eye diagram is analyzed using adaptive window function and peak-valley detection method to obtain the eye diagram jitter information.

[0014] As a further technical limitation, the synchronous processing of the acquired signal data is performed by combining a cross-correlation function synchronous processing method with a phase detection synchronous processing method.

[0015] As a further technical limitation, the specific process of the oscilloscope eye diagram generated by the adaptive window function analysis is: setting the initial window function parameters according to the obtained synchronization data signal, dynamically adjusting the window function parameters in combination with the morphological feature parameters of the generated oscilloscope eye diagram, and iteratively optimizing the window function in combination with the gradient descent method to obtain the eye diagram jitter information.

[0016] As a further technical limitation, the specific process of analyzing the generated oscilloscope eye diagram using the peak and valley detection method is: preprocessing the generated oscilloscope eye diagram data, identifying the peaks and valleys in the preprocessed oscilloscope eye diagram data, and calculating the difference between adjacent peaks and valleys to identify the change point of the oscilloscope eye diagram waveform.

[0017] Furthermore, based on the identified change points of the oscilloscope eye diagram waveform, characteristic parameters of the oscilloscope waveform are extracted, and analysis and evaluation of the oscilloscope eye diagram are completed based on the extracted characteristic parameters; wherein the extracted characteristic parameters of the oscilloscope waveform include at least peak height, trough depth and peak-to-trough spacing.

[0018] As a further technical limitation, the obtained eye diagram jitter information is displayed and outputted in the form of graphics and numerical values ​​on the interactive interface of the oscilloscope, and the real-time update of the eye diagram and jitter analysis is completed by adjusting the oscilloscope parameters.

[0019] According to some embodiments, a second solution of the present invention provides an eye diagram jitter analysis system for an oscilloscope, which adopts the following technical solution:

[0020] An eye diagram jitter analysis system for an oscilloscope, comprising:

[0021] an acquisition module, configured to acquire oscilloscope signal data to be analyzed;

[0022] An extraction module, configured to extract clock information from the acquired signal data to obtain a data clock signal;

[0023] A synchronization module, which is configured to perform synchronization processing on the acquired signal data based on the obtained data clock signal to obtain a synchronization data signal;

[0024] The analysis module is configured to superimpose the obtained synchronous data signal to generate an oscilloscope eye diagram; and adopt an adaptive window function and a peak-valley detection method to analyze the generated oscilloscope eye diagram to obtain eye diagram jitter information.

[0025] According to some embodiments, a third solution of the present invention provides a computer-readable storage medium, which adopts the following technical solution:

[0026] A computer-readable storage medium stores a program, which, when executed by a processor, implements the steps of the eye diagram jitter analysis method of an oscilloscope as described in the first solution of the present invention.

[0027] According to some embodiments, a fourth solution of the present invention provides an electronic device, which adopts the following technical solution:

[0028] An electronic device comprises a memory, a processor and a program stored in the memory and running on the processor, wherein when the processor executes the program, the steps in the eye diagram jitter analysis method of an oscilloscope as described in the first solution of the present invention are implemented.

[0029] According to some embodiments, a fifth solution of the present invention provides a computer program product, which adopts the following technical solution:

[0030] A computer program product comprises software codes, wherein the program in the software codes executes the steps in the eye diagram jitter analysis method of an oscilloscope as described in the first solution of the present invention.

[0031] Compared with the prior art, the present invention has the following beneficial effects:

[0032] The present invention uses a multi-core processor to accelerate data preprocessing and analysis tasks, and improves data processing speed through parallel computing; it realizes efficient calculation of eye diagram and jitter analysis, can process high-speed serial signals faster, and meets the needs of real-time analysis; it no longer relies too much on expensive hardware equipment such as high-performance oscilloscopes, but uses data acquisition cards and software algorithms to reduce the cost of the analysis system, improve popularity and application scope; through methods such as adaptive window functions and statistical models, the accuracy of complex signal jitter analysis is improved, the possibility of misjudgment is reduced, especially the analysis effect of non-periodic jitter is better; an interactive interface is provided to allow users to adjust parameters and update analysis results in real time, which has higher flexibility. At the same time, the software algorithm is easier to expand and upgrade functions; using technologies such as digital phase-locked loops and cross-correlation functions, the accuracy of clock recovery and data synchronization is improved, and the accuracy of bit alignment is ensured. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The drawings in the specification that constitute a part of this embodiment are used to provide a further understanding of this embodiment. The schematic embodiments of this embodiment and their descriptions are used to explain this embodiment and do not constitute improper limitations on this embodiment.

[0034] Figure 1 This is a flow chart of the eye diagram jitter analysis method of an oscilloscope in Embodiment 1 of the present invention;

[0035] Figure 2 This is a class diagram of eye diagram jitter analysis of an oscilloscope in Embodiment 1 of the present invention;

[0036] Figure 3 Schematic diagram of eye diagram jitter analysis results of an oscilloscope in Embodiment 1 of the present invention. DETAILED DESCRIPTION

[0037] The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

[0038] It should be noted that the following detailed descriptions are exemplary and are intended to provide further explanation of the present application. Unless otherwise specified, all technical and scientific terms used herein have the same meanings as those commonly understood by those skilled in the art to which the present application belongs.

[0039] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit exemplary embodiments according to the present invention. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprising" and / or "including" are used in this specification, it indicates the presence of features, steps, operations, devices, components and / or combinations thereof.

[0040] In the absence of conflict, the embodiments of the present invention and the features of the embodiments may be combined with each other.

[0041] Embodiment 1

[0042] Embodiment 1 of the present invention introduces an eye diagram jitter analysis method for an oscilloscope.

[0043] like Figure 1 An oscilloscope eye diagram and jitter analysis method shown includes the following steps:

[0044] (1) Data collection and preprocessing;

[0045] (2) Clock recovery;

[0046] (3) Eye diagram generation;

[0047] (4) Jitter analysis;

[0048] (5) Result visualization and interaction.

[0049] As one or more implementations, this embodiment uses a high-performance data acquisition card (DAQ) to capture high-speed serial signals at an appropriate sampling rate. A low-pass filter (LPF) is applied to remove high-frequency noise to ensure signal quality. The display range of the input signal is adjusted through automatic gain control (AGC), that is, the input signal is displayed within the range of ±3.5 grids in the center of the oscilloscope screen, providing a data range for subsequent eye diagram and jitter analysis, which is convenient for normalization processing.

[0050] In this embodiment, a high-speed data acquisition card is connected to an oscilloscope interface to acquire data from the oscilloscope acquisition card, thereby realizing real-time acquisition of high-speed serial data signals in the range of 500K to 2.7Gbps. It should be noted that after acquiring the oscilloscope data, the acquired oscilloscope data needs to be pre-processed by filtering and denoising to reduce external interference and the noise component of the signal itself, thereby providing a clear data basis for subsequent clock recovery and eye diagram generation.

[0051] As one or more implementations, this embodiment uses a digital phase-locked loop (DLL) or software PLL algorithm to extract clock information from the signal to achieve clock recovery. A cross-correlation function (CCF) or phase detection algorithm is used to synchronize data streams to ensure data bit alignment.

[0052] The process of synchronizing data streams in this embodiment is as follows:

[0053] Initialization: The PLL system is initialized, including setting the initial phase, loop filter parameters, etc., to prepare for the phase tracking process;

[0054] Phase detection: The phase detector (PD) in the PLL is responsible for detecting the phase difference between the input signal and the output signal of the local oscillator (VCO). This phase difference is converted into an error signal, which represents the difference between the current phase and the ideal phase;

[0055] Phase increment estimation: Based on the error signal output by the phase detector, the PLL estimates the phase increment through the Digital Loop Filter (DLF). The function of the DLF is to filter and integrate the error signal to generate an incremental signal to control the VCO phase adjustment. This process is carried out continuously to gradually reduce the phase error;

[0056] Phase adjustment: According to the phase increment signal output by the DLF, the VCO adjusts the phase of its output signal so that it gradually approaches the phase of the input signal. This adjustment process is achieved by changing the control voltage or frequency of the VCO;

[0057] Repeated comparison and locking: The above process (phase detection, phase increment estimation, phase adjustment) is repeated until the phase difference between the output signal of the PLL and the input signal reaches a sufficiently small range, that is, the PLL is considered to be locked. At this point, the output signal of the PLL can be used as a recovered clock signal;

[0058] Data extraction: Based on PLL locking, the synchronized clock and data information can be extracted from the input signal.

[0059] It should be noted that the traditional hardware phase-locked loop (HPLL) may be affected by the characteristics of the hardware itself, such as circuit noise, temperature changes, etc., resulting in jitter in the recovered clock signal. The PLL based on phase increment estimation realizes phase tracking and adjustment through digital algorithms, effectively avoiding the jitter components caused by hardware factors and improving the accuracy of data measurement; the parameters of the PLL (such as loop filter parameters, VCO gain, etc.) can be adjusted and optimized through software to adapt to different application scenarios and signal characteristics. This flexibility and configurability is difficult to match with HPLL; with the continuous development of digital circuit technology, PLL can be more easily integrated into modern digital signal processing chips, reducing the complexity and cost of system design. In contrast, HPLL usually requires more analog circuit components, which increases the difficulty and cost of design.

[0060] This embodiment uses a built-in clock recovery algorithm, such as software PLL (Phase-Locked Loop), to automatically extract the original reference clock signal by analyzing the received data sequence. During the clock recovery process, the software algorithm will consider the time domain characteristics and frequency domain characteristics of the signal to ensure that the recovered clock signal is highly consistent with the original transmitted clock, thereby providing an accurate time reference for subsequent eye diagram generation and jitter analysis.

[0061] It should be noted that the design of the clock recovery mechanism usually includes the following key steps:

[0062] 1) Sampling data preprocessing

[0063] DC offset removal: This is done by calculating the mean of the data series and then subtracting this mean from each sample value.

[0064] High-pass filtering: Use digital filters (such as FIR or IIR filters) to remove unwanted low-frequency components. Synchronous sampling clock correction: If the sampling clock and the clock frequency of the data signal are not completely synchronized, correction is required to ensure that the sampling clock and the clock period of the data signal are consistent.

[0065] 2) Autocorrelation function (ACF) calculation

[0066] Calculate the autocorrelation function: For each possible delay τ, calculate the product of the data sequence x[n] and itself x[n+τ], and then divide it by the length of the data sequence N minus τ to obtain the autocorrelation function R[τ].

[0067] Find the peak of the autocorrelation function: The peak of the autocorrelation function usually corresponds to the period of the data sequence. By finding the maximum autocorrelation function value and its corresponding delay τ, the period of the data T = τ can be determined.

[0068] 3) Cyclic Prefix (CP) Detection

[0069] Cyclic prefix matching: First identify the cyclic prefix pattern, and then search for this pattern in the received data.

[0070] Clock phase adjustment: Once the cyclic prefix is ​​found, the data sequence can be adjusted based on its position to synchronize it with the sender's clock.

[0071] 4) Multipath Phase Recovery

[0072] Maximum Likelihood Estimation (MLE): By building a signal model, the statistical characteristics of the received signal are used to estimate the most likely phase solution.

[0073] Blind equalization: It does not rely on prior knowledge of the transmission system and estimates the phase solution by optimizing the statistical characteristics of the received signal.

[0074] It should be noted that the PLL clock recovery method focuses more on clock recovery in a single path or relatively simple transmission environment; while multipath phase recovery is more suitable for complex environments with multiple transmission paths; PLL mainly uses the structure and algorithm of the digital phase-locked loop to achieve phase tracking and adjustment; while multipath phase recovery may use more complex signal processing algorithms, such as maximum likelihood estimation; PLL has the advantages of high precision, high stability and easy digital integration; and multipath phase recovery has stronger capabilities in dealing with multipath interference and signal fading.

[0075] 5) Software and hardware collaborative design

[0076] Hardware acceleration: For computationally intensive operations such as FFT, FPGA accelerators are used to increase processing speed. Software control: The software is responsible for controlling the behavior of the hardware, including configuring hardware parameters, starting hardware operations, etc.

[0077] As one or more implementation modes, a software algorithm is used to dynamically generate an eye diagram, and an "eye" diagram representing the signal quality is formed by superimposing signal waveforms of multiple data cycles; the horizontal direction of the eye diagram reflects the timing jitter characteristics of the signal, and the vertical direction represents the amplitude stability of the signal.

[0078] This embodiment uses the cumulative superposition method to superimpose multiple synchronized data points on the same time scale to form an eye diagram. Interpolation algorithms (such as linear interpolation, cubic spline interpolation, etc.) are applied to fill in missing data to ensure the smoothness and accuracy of the eye diagram. By dynamically adjusting the scaling of the eye diagram, the visual effect is optimized and details can be observed more easily.

[0079] As one or more implementation modes, this embodiment adopts a method combining time domain and frequency domain analysis. In the time domain analysis, deterministic jitter (DJB) and random jitter (RJB), as well as the opening and closing state of the eye diagram can be measured; in the frequency domain analysis, the time domain signal is converted into the frequency domain through fast Fourier transform (FFT), and the spectrum characteristics of the signal are analyzed to obtain more comprehensive jitter information.

[0080] It should be noted that the present embodiment models jitter using a dual Dirac model, which can more accurately describe the characteristics of deterministic jitter (DJ) and random jitter (RJ), especially their distribution in the histogram; the tail fitting algorithm is used to accurately determine the tail area in the histogram, so as to more accurately separate DJ and RJ, thereby improving the accuracy of jitter separation; the present embodiment is not only applicable to high-speed serial signals, but also to other types of signal jitter separation, and has strong versatility and adaptability; it can process jitter components of different sources and characteristics, such as system internal noise, external interference, etc.; the tail fitting algorithm in the present embodiment is relatively simple and has a moderate amount of calculation, which can improve the analysis efficiency while ensuring accuracy; the combination of time domain and frequency domain analysis methods can optimize the analysis process and reduce unnecessary calculations.

[0081] This embodiment uses an adaptive window function (such as a Hanning window, a Hamming window, etc.) to reduce boundary effects and improve frequency domain resolution; specifically:

[0082] 1. Select the window function

[0083] Select the appropriate window function according to the signal characteristics and analysis requirements. The Hanning window is a commonly used window function, which is defined as: w(n) = 0.5[1-cos(N-12πn)]; where N is the length of the window (i.e. the number of samples) and n is the sample index (from 0 to N-1).

[0084] 2. Apply window function

[0085] Apply the selected window function to the original signal. This is usually achieved by multiplying each sample value of the window function with the corresponding sample value of the signal. For a signal x[n] and a window function w[n], the signal xw[n] after applying the window function is: xw[n] = x[n]·w[n]; it should be noted that the length of the window function should match the length of the signal segment (or analysis window).

[0086] 3. Fast Fourier Transform FFT

[0087] Perform FFT on the signal xw[n] after applying the window function to obtain its frequency domain representation; FFT converts the time domain signal into a sequence of complex numbers in the frequency domain, where each complex number represents the amplitude and phase of a specific frequency component.

[0088] 4. Analyze the results

[0089] Analyze the FFT results to obtain the spectral characteristics of the signal. Due to the use of the window function, the side lobes in the spectrum will be suppressed, thereby improving the frequency domain resolution and the accuracy of spectrum estimation.

[0090] 5. Adaptive Adjustment

[0091] In some cases, it may be necessary to adaptively adjust the parameters of the window function based on the characteristics of the signal (although this is usually not necessary for fixed-shape windows such as Hanning and Hamming windows). For example, the length or type of the window may be selected based on the dynamic range or frequency content of the signal.

[0092] 6. Validate and Iterate

[0093] Verify whether the results after using the window function meet the analysis requirements. If not, you may need to adjust the window function type, length, or analysis parameters and repeat the above process.

[0094] This embodiment uses a fast Fourier transform (FFT) algorithm to convert the time domain signal to the frequency domain and analyze the spectral characteristics of the signal; determines the open and closed state of the eye diagram through a peak and valley detection algorithm, and calculates deterministic jitter (DJB) and random jitter (RJB); specifically, in each bit period of the eye diagram, finds the maximum value (peak value) of the signal, which usually corresponds to the "open" state of the signal; similarly, finds the minimum value (valley value) of the signal in each bit period, which usually corresponds to the "closed" state of the signal. The positions of the peaks and valleys are accurately determined by setting thresholds; based on the positions of the peaks and valleys, the open and closed state of each bit period in the eye diagram can be determined; DJB is evaluated by measuring the deviation of all peaks (or valleys) in the eye diagram relative to the ideal position and calculating the statistical characteristics of these deviations (maximum value, minimum value, average value, etc.); using histogram analysis, the amplitude of RJB is estimated by fitting the tail of the histogram.

[0095] Combine statistical models (such as Gaussian distribution model) to model random jitter and improve analysis accuracy; specifically, extract sample points from around the center of the eye diagram (or a reference point) and construct a histogram of these points; determine the central area and tail area of ​​the histogram, where the tail area usually contains sample points with larger jitter values ​​away from the center; extract data points in the tail area from the histogram, which can be achieved by setting a threshold, that is, only considering sample points greater than a certain value; select Rayleigh distribution or Gaussian distribution to determine the fitting model; use the extracted tail data to estimate the parameters of the Gaussian distribution (mean μ and standard deviation σ); when fitting the tail of the jitter, estimate the parameters through the standard deviation σ that is directly related to the amplitude of RJB; combine the evaluation of the degree of fit of the fitting model to the tail data, and achieve it by calculating the goodness of fit statistics (such as the residual sum of squares and Akaike information criterion AIC); if the fitting effect is not good, it is necessary to reselect the model or adjust the fitting parameters.

[0096] As one or more implementation modes, this embodiment supports multiple graphical display modes, including TIE histogram, TIE trend graph, TIE spectrum graph and bathtub curve, etc. These graphs intuitively show the statistical characteristics and jitter distribution of the signal. Users can easily adjust parameters such as sampling rate, window size, etc. through the graphical interface to meet different analysis requirements and view changes in analysis results in real time.

[0097] This embodiment provides a low-cost, high-efficiency oscilloscope real-time eye diagram and jitter analysis tool, and through an accurate digital phase-locked loop clock recovery method based on phase delta estimation and a jitter separation method based on double Dirkat tail fitting, a comprehensive and in-depth analysis of high-speed serial data signals is achieved, providing strong support for the design, testing and optimization of high-speed communication systems.

[0098] Embodiment 2

[0099] Embodiment 2 of the present invention introduces an eye diagram jitter analysis system for an oscilloscope.

[0100] An eye diagram jitter analysis system for an oscilloscope, comprising:

[0101] an acquisition module, configured to acquire oscilloscope signal data to be analyzed;

[0102] An extraction module, configured to extract clock information from the acquired signal data to obtain a data clock signal;

[0103] A synchronization module, which is configured to perform synchronization processing on the acquired signal data based on the obtained data clock signal to obtain a synchronization data signal;

[0104] The analysis module is configured to superimpose the obtained synchronous data signal to generate an oscilloscope eye diagram; and adopt an adaptive window function and a peak-valley detection method to analyze the generated oscilloscope eye diagram to obtain eye diagram jitter information.

[0105] The detailed steps are the same as the eye diagram jitter analysis method of the oscilloscope provided in the first embodiment, and will not be repeated here.

[0106] Embodiment 3

[0107] Embodiment 3 of the present invention provides a computer-readable storage medium.

[0108] A computer-readable storage medium stores a program, which, when executed by a processor, implements the steps of the eye diagram jitter analysis method of an oscilloscope as described in Embodiment 1 of the present invention.

[0109] The detailed steps are the same as the eye diagram jitter analysis method of the oscilloscope provided in the first embodiment, and will not be repeated here.

[0110] Embodiment 4

[0111] A fourth embodiment of the present invention provides an electronic device.

[0112] An electronic device comprises a memory, a processor and a program stored in the memory and running on the processor, wherein when the processor executes the program, the steps in the eye diagram jitter analysis method of an oscilloscope as described in the first embodiment of the present invention are implemented.

[0113] The detailed steps are the same as the eye diagram jitter analysis method of the oscilloscope provided in the first embodiment, and will not be repeated here.

[0114] Embodiment 5

[0115] Embodiment 5 of the present invention provides a computer program product.

[0116] A computer program product includes software codes, wherein the program in the software codes executes the steps in the eye diagram jitter analysis method of an oscilloscope as described in the first embodiment of the present invention.

[0117] The detailed steps are the same as the eye diagram jitter analysis method of the oscilloscope provided in the first embodiment, and will not be repeated here.

[0118] The above description is only a preferred embodiment of the present embodiment and is not intended to limit the present embodiment. For those skilled in the art, the present embodiment may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present embodiment shall be included in the protection scope of the present embodiment.

Claims

1. An oscilloscope eye diagram jitter analysis method, characterized in that: include: Obtain oscilloscope signal data to be analyzed; Extracting clock information from the acquired signal data to obtain a data clock signal; Perform synchronization processing on the acquired signal data based on the obtained data clock signal to obtain a synchronous data signal; The resulting synchronous data signals are superimposed to generate an oscilloscope eye diagram; The generated oscilloscope eye diagram is analyzed using adaptive window function and peak-valley detection method to obtain the eye diagram jitter information.

2. The eye diagram jitter analysis method of an oscilloscope as claimed in claim 1, characterized in that: The acquired signal data is synchronously processed by combining a cross-correlation function synchronous processing method with a phase detection synchronous processing method.

3. The eye diagram jitter analysis method of an oscilloscope as claimed in claim 1, characterized in that: The specific process of the oscilloscope eye diagram generated by the adaptive window function analysis is as follows: setting the initial window function parameters according to the obtained synchronization data signal, dynamically adjusting the window function parameters in combination with the morphological characteristic parameters of the generated oscilloscope eye diagram, and iteratively optimizing the window function in combination with the gradient descent method to obtain the eye diagram jitter information.

4. The eye diagram jitter analysis method of an oscilloscope as claimed in claim 1, characterized in that: The specific process of analyzing the generated oscilloscope eye diagram using the peak-valley detection method is as follows: preprocessing the generated oscilloscope eye diagram data, identifying the peaks and valleys in the preprocessed oscilloscope eye diagram data, and calculating the difference between adjacent peaks and valleys to identify the change point of the oscilloscope eye diagram waveform.

5. The eye diagram jitter analysis method of an oscilloscope as claimed in claim 4, characterized in that: Based on the identified change points of the oscilloscope eye diagram waveform, characteristic parameters of the oscilloscope waveform are extracted, and analysis and evaluation of the oscilloscope eye diagram are completed based on the extracted characteristic parameters; wherein the extracted characteristic parameters of the oscilloscope waveform include at least peak height, trough depth and peak-to-trough spacing.

6. The eye diagram jitter analysis method of an oscilloscope as claimed in claim 1, characterized in that: The obtained eye diagram jitter information is displayed and output in the form of graphics and numerical values ​​on the oscilloscope interactive interface, and the real-time update of the eye diagram and jitter analysis is completed by adjusting the oscilloscope parameters.

7. An oscilloscope eye diagram jitter analysis system, characterized in that: include: an acquisition module, configured to acquire oscilloscope signal data to be analyzed; An extraction module, configured to extract clock information from the acquired signal data to obtain a data clock signal; A synchronization module, which is configured to perform synchronization processing on the acquired signal data based on the obtained data clock signal to obtain a synchronization data signal; The analysis module is configured to superimpose the obtained synchronous data signal to generate an oscilloscope eye diagram; and adopt an adaptive window function and a peak-valley detection method to analyze the generated oscilloscope eye diagram to obtain eye diagram jitter information.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the steps of the eye diagram jitter analysis method of an oscilloscope according to any one of claims 1 to 6 are implemented.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and running on the processor, characterized in that: When the processor executes the program, the steps of the eye diagram jitter analysis method of the oscilloscope according to any one of claims 1 to 6 are implemented.

10. A computer program product comprising software code, characterized in that The program in the software code executes the steps of the eye diagram jitter analysis method for an oscilloscope according to any one of claims 1 to 6.

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