Computing system, method, device, medium and program product

Abstract

The invention discloses a computing system, a computing method, computing equipment, a medium and a program product in the technical field of computers. The heterogeneous acceleration card with the built-in Ethernet controller forms the heterogeneous acceleration pool, the heterogeneous acceleration pool is connected with the Ethernet switching module in an Ethernet mode or a remote direct data access mode, and the Ethernet switching module is connected with the computing resource pool; the management core in the computing resource pool can manage the acceleration cards in the at least one heterogeneous acceleration pool and the binding relationship between the computing core and the acceleration cards, and distribute the processing task to the acceleration cards in the at least one heterogeneous acceleration pool, so that the acceleration cards in the at least one heterogeneous acceleration pool cooperatively complete the processing task. Wherein data transmission is accelerated in an Ethernet mode or a remote direct data access mode, so that not only can sufficient computing power support be provided for task operation, but also high bandwidth and low delay can be provided for high-speed communication and large-data-volume transmission of tasks, and rapid and stable operation of model training tasks is facilitated.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a computing system, method, device, medium and program product. Background Art

[0002] At present, model training requires the support of massive computing power, usually requiring a large number of servers as nodes, forming a cluster through a high-speed network, and interconnecting and collaborating with each other to complete the task. However, for large-scale, long-term model training tasks, the communication volume required for a single computing iteration alone reaches hundreds of GB, in addition to the communication requirements of various parallel modes. If the network bandwidth is not large enough and the delay is long, not only will the computing power decrease marginally, but the time cost of model training will also increase. In addition, large model training also has relatively high requirements for latency and packet loss.

[0003] Therefore, how to build a corresponding computing system for model training tasks is a problem that technical personnel in this field need to solve. Summary of the invention

[0004] In view of this, the purpose of this application is to provide a computing system, method, device, medium and program product to build a corresponding computing system for model training tasks. The specific scheme is as follows:

[0005] In a first aspect, the present application provides a computing system, including: a computing resource pool, at least one heterogeneous acceleration pool, and an Ethernet switching module connected between the computing resource pool and the at least one heterogeneous acceleration pool;

[0006] The at least one heterogeneous acceleration pool includes: a plurality of acceleration cards; each acceleration card includes: an Ethernet controller and at least one computing core, the Ethernet controller communicates with the computing core in a remote direct data access manner;

[0007] Each accelerator card in the at least one heterogeneous acceleration pool communicates with the Ethernet switching module via Ethernet or remote direct data access;

[0008] The computing resource pool includes: a plurality of computing cores, and the same computing core has a binding relationship with at least one accelerator card in the at least one heterogeneous acceleration pool;

[0009] The multiple computing cores include a management core, which is used to manage each accelerator card in the at least one heterogeneous acceleration pool and the binding relationship, and distribute processing tasks to each accelerator card in the at least one heterogeneous acceleration pool.

[0010] Optionally, each acceleration card in the at least one heterogeneous acceleration pool includes: a gold finger and a power connector; the gold finger and the power connector connect each device in the corresponding acceleration card and provide power to each device in the corresponding acceleration card.

[0011] Optionally, the gold fingers and the power connector in each acceleration card in the at least one heterogeneous acceleration pool supply power simultaneously during the startup process of the corresponding acceleration card.

[0012] Optionally, a switching chip is connected between the Ethernet controller in each acceleration card in the at least one heterogeneous acceleration pool and the computing core in the corresponding acceleration card;

[0013] Correspondingly, the Ethernet controller in each acceleration card in the at least one heterogeneous acceleration pool communicates with the computing core in the corresponding acceleration card in a remote direct data access manner through the switching chip.

[0014] Optionally, each acceleration card in the at least one heterogeneous acceleration pool includes: a homologous clock device, which is connected to a computing core, a switching chip and an Ethernet controller in the corresponding acceleration card.

[0015] Optionally, each accelerator card in the at least one heterogeneous acceleration pool includes: a clock generator, wherein the clock generator is connected between a homologous clock device and a computing core, between a homologous clock device and a switching chip, and between a homologous clock device and an Ethernet controller in the corresponding accelerator card;

[0016] Correspondingly, the clock generator is used to select a clock source for the computing core, switching chip and Ethernet controller in the corresponding acceleration card; the clock source is: a homologous clock device in the corresponding acceleration card or a clock device in the computing core bound to the corresponding acceleration card.

[0017] Optionally, each acceleration card in the at least one heterogeneous acceleration pool includes: a control unit; the control unit is used to implement timing control of information transmission in the corresponding acceleration card.

[0018] Optionally, each acceleration card in the at least one heterogeneous acceleration pool includes: a link selector; the link selector connects the computing core, the switching chip, the Ethernet controller, the homologous clock device, the power supply device and the control unit in the corresponding acceleration card.

[0019] Optionally, the Ethernet switching module includes: at least one switch; the at least one switch connects the computing resource pool and the at least one heterogeneous acceleration pool.

[0020] Optionally, each accelerator card in the at least one heterogeneous acceleration pool includes: a first node controller; the first node controller is used to collect device information and operation information in the corresponding accelerator card;

[0021] Correspondingly, each computing core in the computing resource pool includes: a second node controller; the second node controller is used to collect device information and operation information in the corresponding computing core;

[0022] Correspondingly, the Ethernet switching module includes: a central controller; the central controller is used to collect device information and operation information in the acceleration card collected by the first node controller, and device information and operation information in the computing core collected by the second node controller.

[0023] Optionally, the first node controller is used to collect status information of an acceleration chip in a corresponding acceleration card and sensor data of the board.

[0024] Optionally, the second node controller is used to collect core operation information and sensor data in the corresponding computing core.

[0025] Optionally, the central controller is used to construct a topology map including each computing core in the computing resource pool and each acceleration card in the at least one heterogeneous acceleration pool according to the collected information.

[0026] Optionally, the central controller is used to synchronize the collected information to the management core in the computing resource pool;

[0027] Correspondingly, the management core manages each accelerator card in the at least one heterogeneous acceleration pool and the binding relationship according to the received synchronization information, and distributes processing tasks to each accelerator card in the at least one heterogeneous acceleration pool.

[0028] Optionally, the management core is used to formulate corresponding task allocation strategy and binding relationship adjustment strategy according to the received synchronization information.

[0029] Optionally, the central controller is used to generate log data based on the collected information, and analyze the log data to perform fault diagnosis.

[0030] Optionally, the computing system further includes: a bus switching module connected to the at least one heterogeneous acceleration pool; the bus switching module is also connected to another computing resource pool.

[0031] In a second aspect, the present application provides a calculation method, which is applied to a management core, comprising:

[0032] Receive processing tasks;

[0033] Sending the processing task to an Ethernet switching module in the computing system, so that the Ethernet switching module distributes the processing task to at least one heterogeneous acceleration pool in the computing system through Ethernet or remote direct data access;

[0034] The computing system includes: a computing resource pool, the at least one heterogeneous acceleration pool, and the Ethernet switching module connected between the computing resource pool and the at least one heterogeneous acceleration pool;

[0035] The at least one heterogeneous acceleration pool includes: a plurality of acceleration cards; each acceleration card includes: an Ethernet controller and at least one computing core, the Ethernet controller communicates with the computing core in a remote direct data access manner;

[0036] Each accelerator card in the at least one heterogeneous acceleration pool communicates with the Ethernet switching module via Ethernet or remote direct data access;

[0037] The computing resource pool includes: multiple computing cores, and the same computing core has a binding relationship with at least one acceleration card in the at least one heterogeneous acceleration pool; the management core is any one of the multiple computing cores.

[0038] In a third aspect, the present application provides an electronic device, including:

[0039] Memory for storing computer programs;

[0040] A processor is used to execute the computer program to implement the aforementioned disclosed computing method.

[0041] In a fourth aspect, the present application provides a non-volatile storage medium for storing a computer program, wherein the computer program implements the aforementioned disclosed computing method when executed by a processor.

[0042] In a fifth aspect, the present application provides a computer program product, comprising a computer program / instruction, which implements the steps of the aforementioned disclosed computing method when executed by a processor.

[0043] It can be seen from the above scheme that the present application provides a computing system, including: a computing resource pool, at least one heterogeneous acceleration pool, and an Ethernet switching module connected between the computing resource pool and the at least one heterogeneous acceleration pool; the at least one heterogeneous acceleration pool includes: a plurality of acceleration cards; each acceleration card includes: an Ethernet controller and at least one computing core, the Ethernet controller communicates with the computing core in a remote direct data access manner; each acceleration card in the at least one heterogeneous acceleration pool communicates with the Ethernet switching module via Ethernet or a remote direct data access manner; the computing resource pool includes: a plurality of computing cores, the same computing core has a binding relationship with at least one acceleration card in the at least one heterogeneous acceleration pool; the plurality of computing cores include a management core, the management core is used to manage each acceleration card in the at least one heterogeneous acceleration pool and the binding relationship, and distribute processing tasks to each acceleration card in the at least one heterogeneous acceleration pool.

[0044] It can be seen that the technical effect of the present application is: heterogeneous acceleration cards with built-in Ethernet controllers form a heterogeneous acceleration pool, and the heterogeneous acceleration pool is connected to the Ethernet switching module through Ethernet or remote direct data access, and the Ethernet switching module is connected to the computing resource pool; the management core in the computing resource pool can manage the binding relationship between each accelerator card in at least one heterogeneous acceleration pool, the computing core and the accelerator card, and distribute processing tasks to each accelerator card in at least one heterogeneous acceleration pool, so that each accelerator card in at least one heterogeneous acceleration pool can cooperate to complete the processing task. The computing power system constructed by the present application for the model training task accelerates data transmission through Ethernet or remote direct data access, which can not only provide sufficient computing power support for the operation of the task, but also provide high bandwidth and low latency for high-speed communication and large data transmission of the task, which is conducive to the rapid and stable operation of the model training task.

[0045] Correspondingly, a computing device, equipment, medium and program product provided by the present application also have the above-mentioned technical effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0047] Figure 1 A schematic diagram of a computing system disclosed in this application;

[0048] Figure 2 This is a principle block diagram of a GPU accelerator card disclosed in this application;

[0049] Figure 3 A power supply circuit diagram of a GPU accelerator card disclosed in this application;

[0050] Figure 4 A clock circuit diagram of a GPU accelerator card disclosed in this application;

[0051] Figure 5 A communication diagram between a GPU and an Ethernet controller disclosed in this application;

[0052] Figure 6 A schematic diagram of an RDMA communication software stack disclosed in this application;

[0053] Figure 7 An architectural diagram of a computing system disclosed in this application;

[0054] Figure 8 An architectural diagram of another computing system disclosed in this application;

[0055] Fig. 9 This is an architecture diagram of another computing system disclosed in this application;

[0056] Fig.10 A schematic diagram of a communication method disclosed in this application;

[0057] Fig.11 A topological diagram disclosed in this application;

[0058] Fig.12 A schematic diagram of an accelerator card management disclosed in this application;

[0059] Fig.13 This is another schematic diagram of accelerator card management disclosed in this application;

[0060] Fig.14 A schematic diagram of kernel communication of a general computing node disclosed in this application;

[0061] Fig.15 A schematic diagram of a heterogeneous virtual computing power management subsystem disclosed in this application;

[0062] Fig.16 A schematic diagram of a heterogeneous computing resource pool management architecture disclosed in this application;

[0063] Fig.17 A server structure diagram provided for this application;

[0064] Fig.18 A terminal structure diagram provided for this application. DETAILED DESCRIPTION

[0065] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other examples obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0066] At present, model training requires the support of massive computing power, and usually requires a large number of servers as nodes, forming a cluster through a high-speed network, and the servers are interconnected and cooperate with each other to complete the task. However, for large-scale and long-term model training tasks, the communication volume required for a single calculation iteration alone reaches the order of hundreds of GB, in addition to the communication requirements of various parallel modes. If the bandwidth of the network is not large enough and the delay is long, it will not only reduce the marginal computing power, but also increase the time cost of model training. In addition, large model training also has high requirements for latency and packet loss. To this end, the present application provides a computing solution that can build a corresponding computing power system for model training tasks, accelerate data transmission through Ethernet or remote direct data access, and not only provide sufficient computing power support for the operation of tasks, but also provide high bandwidth and low latency for high-speed communication and large data transmission of tasks, which is conducive to the rapid and stable operation of model training tasks.

[0067] See also Figure 1 As shown, an embodiment of the present application discloses a computing system, including: a computing resource pool, at least one heterogeneous acceleration pool, and an Ethernet switching module connected between the computing resource pool and the at least one heterogeneous acceleration pool.

[0068] Among them, at least one heterogeneous acceleration pool includes: multiple acceleration cards; each acceleration card includes: an Ethernet controller and at least one computing core, and the Ethernet controller communicates with the computing core in a remote direct data access manner. Each acceleration card in at least one heterogeneous acceleration pool communicates with the Ethernet switching module via Ethernet or remote direct data access. The computing resource pool includes: multiple computing cores, and the same computing core has a binding relationship with at least one acceleration card in at least one heterogeneous acceleration pool. The multiple computing cores include a management core, which is used to manage each acceleration card and the binding relationship in at least one heterogeneous acceleration pool, and distribute processing tasks to each acceleration card in at least one heterogeneous acceleration pool.

[0069] It should be noted that each accelerator card includes a circuit structure for implementing related data operations, which can be specifically presented as: GPU, FPGA, etc., which are collectively referred to as operation cores in this embodiment. The computing resource pool is composed of many processor cores, and a processor core is: a computing core; including a processor core dedicated to serving as a management end, which is referred to as a management core in this embodiment.

[0070] In one embodiment, each accelerator card in the at least one heterogeneous acceleration pool includes: a gold finger and a power connector; the gold finger and the power connector connect various devices in the corresponding accelerator card and supply power to various devices in the corresponding accelerator card. The gold finger and the power connector in each accelerator card in the at least one heterogeneous acceleration pool supply power simultaneously during the startup process of the corresponding accelerator card.

[0071] In one embodiment, a switching chip is connected between the Ethernet controller in each accelerator card in the at least one heterogeneous acceleration pool and the computing core in the corresponding accelerator card; accordingly, the Ethernet controller in each accelerator card in the at least one heterogeneous acceleration pool and the computing core in the corresponding accelerator card communicate in a remote direct data access manner through the switching chip.

[0072] In one embodiment, each accelerator card in the at least one heterogeneous acceleration pool includes: a homologous clock device, which is connected to the computing core, switching chip and Ethernet controller in the corresponding accelerator card. Wherein, each accelerator card in the at least one heterogeneous acceleration pool includes: a clock generator, which is connected between the homologous clock device and the computing core, between the homologous clock device and the switching chip, and between the homologous clock device and the Ethernet controller in the corresponding accelerator card; accordingly, the clock generator is used to select a clock source for the computing core, switching chip and Ethernet controller in the corresponding accelerator card; the clock source is: the homologous clock device in the corresponding accelerator card or the clock device in the computing core bound to the corresponding accelerator card.

[0073] In one embodiment, each accelerator card in the at least one heterogeneous accelerator pool includes: a control unit; the control unit is used to implement timing control of information transmission in the corresponding accelerator card. The control unit may be specifically a CPLD, an MCU (Microcontroller Unit), or the like.

[0074] In one embodiment, each acceleration card in the at least one heterogeneous acceleration pool includes: a link selector; the link selector connects the computing core, the switching chip, the Ethernet controller, the homologous clock device, the power supply device and the control unit in the corresponding acceleration card.

[0075] In one embodiment, the Ethernet switching module includes: at least one switch; the at least one switch connects the computing resource pool and at least one heterogeneous acceleration pool.

[0076] In one embodiment, each accelerator card in at least one heterogeneous acceleration pool includes: a first node controller; the first node controller is used to collect device information and operation information in the corresponding accelerator card; accordingly, each computing core in the computing resource pool includes: a second node controller; the second node controller is used to collect device information and operation information in the corresponding computing core; accordingly, the Ethernet switching module includes: a central controller; the central controller is used to collect device information and operation information in the accelerator card collected by the first node controller, and device information and operation information in the computing core collected by the second node controller.

[0077] The first node controller is used to collect the status information of the acceleration chip in the corresponding acceleration card and the sensor data of the board. The second node controller is used to collect the core operation information and sensor data in the corresponding computing core. The central controller is used to construct a topology map including each computing core in the computing resource pool and each accelerator card in at least one heterogeneous acceleration pool according to the collected information.

[0078] In one embodiment, the central controller is used to synchronize the collected information to the management core in the computing resource pool; accordingly, the management core manages each accelerator card and binding relationship in at least one heterogeneous acceleration pool according to the received synchronization information, and distributes processing tasks to each accelerator card in at least one heterogeneous acceleration pool.

[0079] In one implementation, the management core is used to formulate corresponding task allocation strategies and binding relationship adjustment strategies according to the received synchronization information.

[0080] In one embodiment, the central controller is used to generate log data based on the collected information, and analyze the log data to perform fault diagnosis.

[0081] In one embodiment, the computing system further includes: a bus switching module connected to at least one heterogeneous acceleration pool; the bus switching module is also connected to another computing resource pool.

[0082] It can be seen that in this embodiment, the heterogeneous acceleration card with built-in Ethernet controller forms a heterogeneous acceleration pool, and the heterogeneous acceleration pool is connected to the Ethernet switch module through Ethernet or remote direct data access, and the Ethernet switch module is connected to the computing resource pool; the management core in the computing resource pool can manage the binding relationship between each accelerator card in at least one heterogeneous acceleration pool, the computing core and the accelerator card, and distribute processing tasks to each accelerator card in at least one heterogeneous acceleration pool, so that each accelerator card in at least one heterogeneous acceleration pool can cooperate to complete the processing task. This embodiment is a computing power system constructed for model training tasks. It accelerates data transmission through Ethernet or remote direct data access. It can not only provide sufficient computing power support for the operation of the task, but also provide high bandwidth and low latency for high-speed communication and large data transmission of the task, which is conducive to the rapid and stable operation of the model training task.

[0083] For heterogeneous accelerator cards, this application enables GPU data to be directly encapsulated into Ethernet frames to achieve direct communication between Ethernet and GPU. Heterogeneous accelerator cards support dual-port 100G Ethernet and RDMA (Remote Direct Memory Access) functions, and support GPU chips, Ethernet controller integration, and GPU memory remote direct access functions through software stacks and drivers, thereby achieving data flow from GPU directly to Ethernet.

[0084] The core of the design of heterogeneous accelerator cards is the Ethernet controller, which is mainly responsible for data transmission and network interaction. It can provide high-bandwidth, ultra-low latency Ethernet network services to meet the needs of high-speed transmission of the entire system network. In one example, the Ethernet controller uses two SFP28-type input / output interfaces for external connection, and transmits external computing tasks to the accelerator card through network transmission; it uses PCIe Gen4 X8 connection internally, and transmits externally transmitted data to the GPU chip based on the Peer-to-Peer communication mechanism, and the GPU chip processes the data. When the GPU chip interacts with the Ethernet controller, based on the remote direct access function of the GPU memory, point-to-point transmission of video memory data between different GPUs is realized. The accelerator card integrated network card (ie, Ethernet controller) can achieve ultra-low latency and support PCIe Gen4 full link.

[0085] See also Figure 2 , a GPU accelerator card principle block diagram is as follows Figure 2 shown. Figure 2In the GPU accelerator card, the card is a PCIE (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard) card, including a PCIE gold finger connector and a power connector, which is connected to two 100G networks and connected to the switch through an optical module and an optical fiber cable, and can transmit data with other GPUs. The uplink PCIE Gen4 x16 link of the GPU accelerator card is connected to the gold finger, and the Switch connects two PCIE Gen4 x16s to the network control chip and the GPU accelerator chip. The card form factor of the GPU accelerator card is a PCIe card form factor, with a full height of 111.15mm, a length of 267.7mm, and a double width of 39.04m). The key chips of the card include the GPU accelerator chip (i.e., the computing core), the Switch chip (i.e., the switching chip), the network chip (i.e., the network card), and the CPLD (Complex Programmable Logic Device). The PCIEGen4X16 of the gold finger is connected to PCIE_SW, and PCIE_SW outputs another 2 PCIE X16s, which are connected to the GPU chip and the NIC (Network Interface Card) chip respectively. The GPU chip realizes high-performance data processing and computing functions, the Switch realizes the port expansion of PCIE, and the NIC can realize the expansion of 100G network optical ports, complete network virtualization, offload acceleration, data flow forwarding and other tasks, in which the CPLD chip is used for interrupt timing control and information interaction. The heterogeneous computing accelerator card integrates the hardware heterogeneous computing environment through software, so that heterogeneous processors can communicate and transmit data through the PCIE high-speed bus and high-performance network Ethernet, and realize cross-platform operation of computing tasks. It also completes collaborative computing through higher-level system division and task scheduling to achieve higher computing performance and better computing efficiency. The accelerator card can be deployed in various forms such as 4 cards, 8 cards, 16 cards or 32 cards on a single host to meet the landing needs of various industries. It can be widely used in smart finance, intelligent recommendation, fast search, content review, artificial intelligence generation, intelligent customer service and other fields.

[0086] like Figure 3As shown in the figure, the default power supply mode of the GPU accelerator card is that the power connector inputs P12V to power the entire board, and the gold finger provides P3V3_STBY to power the CPLD and FRU. Considering that the power supply in the whole machine may cause insufficient power supply during power transient impact, the PCIE gold finger P12V_GF is reserved to the power supply of SW and NIC, which can share about 50W of power consumption. The board card 12V power supply is obtained by connecting the board card cable to the host motherboard, with a maximum power of 270W. The board card 3V3 power supply is transferred out through P12V on the board card to power the entire board. The board card 3V3_STBY power supply is obtained by connecting the host motherboard through the gold finger on the board card, and the power meets the PCIe5.0 standard. At the same time, for power supply application scenarios with power transient impact (such as GPU startup, dynamic hot plugging, etc.), the board card reserves a soldering resistor to connect the gold finger and the Power Connector 12V power supply. The gold finger provides 3V3_STBY and 12V (60W Max) at the same time.

[0087] like Figure 4 As shown, the GPU card accesses the 100MHz homologous clock signal from the PCIe gold finger and accesses the ClockBuffer respectively. The Buffer expands 3 100MHz clocks to the GPU, Switch chip, and NIC chip. At the same time, the ClockGenerator non-homologous clock solution is reserved to avoid clock delay and jitter abnormalities caused by long lines. If the clock comes from the host, the clock line is long, but in this embodiment, the clock can be selected: host or local.

[0088] It should be noted that the GPU and Ethernet controller NIC are directly connected through the switch chip PCIe SW, which can cope with the computing power challenges of large models. The accelerator card uses the direct connection technology between the switch chip and the Ethernet controller, which is different from the traditional NIC card connected to the switch chip to the CPU, and then the CPU and the network card are interconnected. The heterogeneous computing accelerator card integrates the GPU chip and Ethernet controller to realize the data flow from the GPU directly to RDMA, such as Figure 5 As shown in the figure, the GPU and Ethernet controller NIC are connected through the switch chip Switch, and communicate in the remote direct memory access mode. In addition, the heterogeneous computing accelerator card supports dual-port 100G Ethernet and RDMA functions.

[0089] In one example, the system RDMA communication software stack is as follows: Figure 6As shown. Usually, the communication between cluster nodes is completed through the network. For network card devices that support RDMA, it is necessary to call the interface to initiate a network transmission request. The driver in the software stack supports registering RDMA network card related interfaces. The RDMA network card will communicate with the GPU kernel driver through the kernel driver standard interface to complete the direct transmission of data and realize remote direct access to memory. Only the GPU and RDMA network card participate in the entire data path, avoiding redundant jumps of data to system memory and effectively reducing communication delays.

[0090] It can be seen that in this example, GPUs can be directly connected; GPUs are directly connected to Ethernet controllers through switching chips; host CPUs are interconnected through Ethernet controllers and switches. Among them, the heterogeneous computing accelerator card is directly connected to the Ethernet controller through the switching chip, realizing the combination of GPU chips and Ethernet chips under the same root port; through the high-bandwidth and low-latency interconnection RDMA technology, effective aggregation between chips is achieved.

[0091] In one example, the architecture diagram of the computing system can refer to Figure 7 , the general computing resource pool (corresponding to another computing resource pool) is interconnected with heterogeneous computing acceleration resource pools such as GPU and FPGA through internal buses and internal bus switching modules. In addition, heterogeneous acceleration cards use Ethernet to implement RDMA functions to directly access the memory of heterogeneous acceleration cards remotely, reduce the data transmission delay of acceleration cards, and improve computing performance. The entire system can be horizontally expanded to achieve interconnection between systems, thereby realizing larger-scale heterogeneous computing acceleration pooling. Among them, device resource pooling is achieved through high-performance switching of the system internal bus and software-defined system design, and the binding relationship at the physical link level between the device and the CPU is released. The port configuration and resource allocation path of the switching network can be flexibly adjusted, and the shared resource pool can be divided into fine-grained sections to achieve on-demand elastic allocation of device resources and multi-host sharing. In view of the current problems that the performance expansion of the host system in the data center is limited by the system interconnection bandwidth, the performance mismatch between storage at all levels, and the low utilization of I / O resources, through the pooled system design, dynamic resource allocation and load balancing can be flexibly realized for diversified scenario requirements, and the fusion of multi-platform processor computing power and the coordinated scheduling of heterogeneous acceleration resources can be realized to alleviate the bottleneck problem of data center performance expansion.

[0092] Figure 7The heterogeneous computing acceleration resource pool (i.e., heterogeneous acceleration pool) shown in the figure can maximize computing power and efficiency. According to the differences in resource categories such as general computing and heterogeneous computing, similar computing resources are integrated to form a resource pool to realize on-demand resource reorganization between different devices. Through hardware reconstruction, fine-grained resource segmentation and pooling are realized, general computing resources and heterogeneous computing resources are more closely integrated, and the resource pools are connected by fully interconnected ultra-high-speed internal and external interconnection technology to realize the integration of heterogeneous computing power; at the same time, computing resources can realize task scheduling and load balancing according to business scenarios. Through software definition, a business-aware resource reconstruction decision system is established to complete the intelligent reconstruction of hardware resources, realize the pooling and centralized management of resources, thereby completing dynamic adjustment, flexible combination and intelligent allocation, improving the computing efficiency and response rate of the entire system, and realizing the intelligence and efficiency of heterogeneous computing.

[0093] In one example, the topology of the heterogeneous computing acceleration resource pool and the internal bus switching module is refined to obtain Figure 7 Corresponding Figure 8 .like Figure 8 As shown, the internal bus switching module ( Figure 8 The high-performance switching chip in the Figure 8 The network switching unit in the system includes many network switches NET.

[0094] It should be noted that the internal bus switching module includes not only many switching chips, but also CPLD, management controller, baseboard controller, network switching chip and UART (Universal Asynchronous Receiver / Transmitter) chip; a heterogeneous computing acceleration resource pool includes not only many GPUs, but also baseboard controller and CPLD, etc. For details, please refer to Fig. 9 . In other words: each resource pool can realize flexible resource configuration through reconstruction and decoupling, and interconnect with the processor through the local multi-channel monitoring and diagnosis network, focusing on monitoring and management and fault detection at the hardware layer, collecting the operating status information of the host system in real time and monitoring and management, and can also be connected to many sensors to read environmental conditions and control the temperature through fans. It also supports other system management functions, including remote power control, serial LAN, server host and memory monitoring and error logging. At the same time, when the entire system controller diagnoses a fault, it will display the host system fault and warning in a comprehensive and intuitive manner through the panel indicator light in the form of optical path diagnosis in an obvious form.

[0095] Compared with traditional AI servers, heterogeneous computing acceleration resource pools support two P2P communication methods, such as Fig.10As shown. In addition to PCIe link P2P communication, direct connection technology between the switching chip and the Ethernet controller can also be used. The RDMA communication library needs to call the interface to initiate a network transmission request. The driver in the software stack supports registering RDMA network card related interfaces. The RDMA network card will communicate with the GPU kernel driver through the kernel driver standard interface to complete direct data transmission and realize remote direct access to the video memory. Only the GPU and the RDMA network card participate in the entire data path, avoiding redundant jumps of data to the system memory and effectively reducing communication delays. Pearl represents the internal bus switching module.

[0096] In one example, servers are interconnected through heterogeneous accelerator cards and switches, and multiple training servers are connected to each other to achieve cluster computing power. A feasible topology is as follows: Fig.11 As shown, in Fig.11 In the distributed acceleration server GPU node P2P, cluster expansion is achieved through the parameter plane switch, 1:1 non-blocking; the business plane and storage plane cluster networks are connected to separate switches respectively, which can support 1:1 non-blocking or 2:1 convergence; the cluster out-of-band management network is connected to the TOR out-of-band management switch.

[0097] Since the management of individual accelerator card components is very important in large-scale cluster systems, this embodiment also implements the overall out-of-band management of the system for heterogeneous computing accelerator cards. The main functions include: device monitoring, log management, fault diagnosis, configuration management, etc. Fig.12 shown.

[0098] Hardware device monitoring: The server monitors the acceleration card hardware device through an out-of-band path, and the management chip BMC monitors the components in the acceleration card system through the I2C bus protocol, including the status of the acceleration chip, the temperature of the board, the voltage and other sensor data. The status of each chip in the acceleration card is collected through the boundary scan chain to locate the fault; the control code is sent to each chip through the boundary scan chain to achieve the functions of conduction test, hardware configuration, module reset, fault isolation, etc. Temperature monitoring: The management chip dynamically obtains the heat dissipation requirements and temperature information required for the working environment of the acceleration card. Such as: heterogeneous acceleration chip temperature, heterogeneous acceleration chip memory temperature, inlet and outlet air temperature, etc. Voltage monitoring: Access the power chip monitoring to dynamically obtain board-level related voltage status.

[0099] Fault diagnosis and log management: The system BMC can obtain error information such as overvoltage, undervoltage, and overtemperature on the acceleration chip through the I2C bus protocol, and can also obtain the acceleration chip's serial number, firmware version, and driver version, as well as chip operating voltage, board power consumption, and other information. When the acceleration card system fails, the BMC will record the logs generated by real-time monitoring of the machine status in the local file system. On-site technicians can export the logs through the BMC web page or other tools to troubleshoot and analyze the logs, locate the problem, and solve the problem.

[0100] Configuration management: supports the configuration of network, user, alarm and other software, and supports the import and export of configuration files.

[0101] In terms of accelerator card management, the computing unit and management unit are decoupled and standardized, and common management, security and control functions are separated from the computing unit. This makes it compatible with different computing power platforms and management platforms, supports unified management of multiple interfaces and multiple cores, and meets the needs of different application scenarios. The management unit needs to implement computing power allocation and management, multi-core module voltage regulation and power consumption management to ensure high-efficiency system design; implement resource utilization, I / O throughput, and resource health status monitoring, and achieve coordinated power on and off, centralized management of resources and topology to ensure system availability; achieve on-demand rapid deployment and automatic management of hardware resources, resource key information monitoring and fault management, intelligent fault location and recovery, and ensure computing system reliability. The system management module is responsible for unified management, provides external operation and maintenance capabilities through standardized service interfaces, and realizes integrated monitoring, fault warning, and visual management.

[0102] The system power-on and power-off coordinated control process is as follows:

[0103] 1. After the PSU in each unit supplies power, the VR transfers each STBY power and sends the PG of the last STBY power to the CPLD.

[0104] 2. When the STBY in each chassis is powered on and the CPLD and BMC are working normally, the host and the CPLD in the resource pool send the STBY power PG signal to the BMC through I2C / UART.

[0105] 3. The host and resource pool BMC send the STBY PG completion signal to the BMC of the core switching unit through the network. At this time, each unit waits for the switch unit's key power-on signal to proceed to the next step.

[0106] 4. After pressing the power button of the core switching unit, the power-on signal is given to the CPLD, and the CPLD controls the EN signal of the Main Power.

[0107] 5. At the same time, the Power on signal is sent to the BMC, and the BMC sends the power-on signal to the BMCs of each chassis through the network.

[0108] 6. The BMCs of the host and resource pool send the power-on signal to their respective CPLDs through I2C / UART. The CPLD controls the EN of each VR and, after receiving the last powered PG, sends the power-on completion signal to the BMC and mCPU of the core switching unit through the network and BMC.

[0109] The system power-on reset workflow is as follows:

[0110] 1. After STBY is powered on, the host's BMC will scan the ID of the local interconnect cable CDFP interface and the CDFP ID of the corresponding core switching unit to establish a mapping table.

[0111] 2. Similarly, the BMC of the core switching unit will scan the ID of the local CDFP interface and the CDFPID of the corresponding resource pool to establish a mapping table.

[0112] 3. After each unit is powered on, it waits for the PERST signal. The host sends PERST to each module through the CPU and CPLD. The host's BMC sends the PERST information to the core switching unit BMC through the TOR switch.

[0113] 4. The PREST of the core switching unit except SW is triggered by the PLTRST of the mCPU. The PREST of SW is notified to the CPLD by the BMC through I2C, and the CPLD sends the PREST to the SW and CDFP. The resource pool sends the PREST from the interconnection cable CDFP to the CPLD, and the CPLD sends it to each GPU device.

[0114] For details, please refer to Fig.13 , the accelerator card management functions implemented are as follows:

[0115] Topology identification: supports topology view viewing, which can view node summary information such as node type, power-on status, overall health status, etc.

[0116] Asset information management: Supports viewing device information level by level. You can view device details such as device asset information, high-speed interface connection status, etc. through the Web / Redfish page.

[0117] Collaborative control: supports centralized power-on and power-off control, and each unit is powered on and off in sequence; supports system reset function, automatically detects reset signals for reset during the power-on process and host restart process; supports reset control after resource reallocation, etc.

[0118] In system design, the discovery, management, and elastic adjustment of system resources are key. The control module, as the core management unit for dynamic resource adjustment, controls high-performance switching units to realize automatic discovery of resource topology and flexible and automatic switching of resources, including: Resource identification and display: Provide network interface and visual WEB interface for resource list and topology display, including heterogeneous computing resource unit information, I / O port information, etc.; Dynamic resource allocation: Through key technologies such as hot removal, hot insertion, and hot reset of equipment, dynamic allocation and adjustment of heterogeneous computing units in seconds are realized; Load balancing: Based on the optimized scheduling algorithm of load balancing, physical resources are dynamically and evenly allocated, and fine-grained storage resources are allocated on demand to maximize the release of heterogeneous computing power; Expert template: According to parameters such as business needs, resource status and performance indicators, expert template description and dynamic switching interface of heterogeneous computing power resources are realized, so that applications can apply for resources based on expert templates, and network interface and visual WEB interface are provided to realize the visual application of expert templates.

[0119] In order to give full play to the performance of heterogeneous multi-cores and adapt to various application scenarios, it is very important that applications can be freely migrated between multi-cores. However, migration between heterogeneous multi-cores with different instruction sets has always been a difficult problem in the industry. Load migration and resource scheduling are applied in the following scenarios: the operating system performs load balancing, and processes are migrated to static or lightly loaded cores; according to different load types, they are migrated to cores of different instruction set architectures; when the power consumption state changes, it is necessary to handle the migration of some processes to achieve power consumption control; when a core is overheated, the process is migrated to other cores, etc.

[0120] The operating system of a general computing node (i.e., host) contains multiple kernels. Each kernel is compiled and runs under a specific ISA instruction set. The entire system uses a unified system software to implement balanced scheduling of computing power on demand for applications. At the operating system level, communication and coordination between kernels are implemented, so that the entire system still has a global state under different ISA core running instances; on this basis, through a unified scheduling core and the application of advanced scheduling technology, the application program is unaware of the underlying hardware. Through the collaboration of the operating system and the scheduling system, the application can automatically select the optimal mapping, realizing the performance improvement of multi-instruction set heterogeneous multi-core systems, such as Fig.14 shown.

[0121] For general computing nodes, this embodiment provides a heterogeneous virtual computing power management subsystem. This system combines heterogeneous resource computing power virtualization and remote scheduling technology at the technical level, and combines the use and management needs of heterogeneous virtualized resources by users and administrators at the application level. For details, please refer to Fig.15 The system ensures that different users have the following basic capabilities when using virtualized resources in different scenarios:

[0122] Transparency: Without modifying system component codes and user codes, the system allows users to call local or remote heterogeneous virtual computing power to execute applications, just like executing them on physical resources.

[0123] Low overhead: The system enables applications running on it to achieve performance as close as possible to that of physical resources when using heterogeneous virtual computing power.

[0124] Isolation: The system manages the allocation and release of heterogeneous virtual computing power for each container, so that containers are completely isolated from each other while sharing physical resources.

[0125] In order to achieve the above goals, the heterogeneous virtual computing power management subsystem mainly includes three components. The heterogeneous virtual computing power management platform is responsible for the front-end interaction logic for end users and administrators. The heterogeneous virtual computing power management center component is responsible for the resource scheduling and management of the entire system. The heterogeneous virtual computing power management node component is responsible for the specific operation execution on each computing node.

[0126] Heterogeneous virtual computing power management platform: A heterogeneous resource scheduling management platform for users and administrators, responsible for receiving user job requests and creating a virtualized computing environment based on specific business needs. At the same time, it receives and summarizes the node device information reported by the node component, and then sends the device summary information to the central component. Specifically, the platform includes the following functions:

[0127] User management: The platform implements basic management of users and roles by storing information such as users and related groups and permissions.

[0128] Resource management: The platform manages all heterogeneous computing physical devices and virtual devices through statistics and different views, including node resource summary, node status information, and operations such as disabling, enabling, and removing virtual devices.

[0129] Quota management: The platform manages and allocates these computing resources by configuring specific quotas for virtual heterogeneous computing resources, including virtual total computing power limit, virtual total video memory limit, computing power limit and video memory limit of a single virtual device, etc.

[0130] Policy management: The platform configures and manages various scheduling policies based on the specific needs of administrators by abstracting the different policies of the scheduler in the central component. For specific scheduling policies, please refer to the description of the central component.

[0131] See also Fig.16, a schematic diagram of a heterogeneous computing resource pool management architecture, with the Pooled System Management Controller (PSMC) in the high-performance switching unit as the center, the heterogeneous computing acceleration unit and the general computing unit are respectively equipped with the Pooled Node Management Controller (PNMC), PSMC as the central management node, and PNMC as a distributed node managed by PSMC to achieve the full life cycle management of the heterogeneous computing resource pool. In the heterogeneous computing resource pool system, the discovery, management, and elastic adjustment of heterogeneous computing resources are the key. This project designs a pooled management engine as the core management unit for dynamic resource adjustment. The pooled management engine will control the high-performance switching unit to realize automatic discovery of resource topology and flexible and automatic resource switching, and provide a standard interface for the data center monitoring and management platform to realize centralized management of massive resources at the data center level.

[0132] PSMC is crucial in the management of distributed heterogeneous acceleration pooled servers. It is a bridge for information communication and is responsible for unified management. Its main functions include node topology identification, centralized display of asset information, and coordinated power on and off. Through standardized service interfaces, it provides external operation and maintenance capabilities to achieve integrated monitoring, fault warning, and visual management. The heterogeneous computing resource pool management system interconnects the management controllers of pooled nodes at all levels through the network to build a management platform for independent engines.

[0133] A calculation method provided in an embodiment of the present application is introduced below. The calculation method described below can be cross-referenced with other embodiments described in this document.

[0134] An embodiment of the present application discloses a computing method applied to a management core, including: receiving a processing task; sending the processing task to an Ethernet switching module in a computing system, so that the Ethernet switching module distributes the processing task to at least one heterogeneous acceleration pool in the computing system via Ethernet or remote direct data access.

[0135] The computing system includes: a computing resource pool, at least one heterogeneous acceleration pool, and an Ethernet switching module connected between the computing resource pool and the at least one heterogeneous acceleration pool; the at least one heterogeneous acceleration pool includes: a plurality of acceleration cards; each acceleration card includes: an Ethernet controller and at least one computing core, the Ethernet controller communicates with the computing core in a remote direct data access manner; each acceleration card in the at least one heterogeneous acceleration pool communicates with the Ethernet switching module in an Ethernet manner or a remote direct data access manner; the computing resource pool includes: a plurality of computing cores, the same computing core has a binding relationship with at least one acceleration card in the at least one heterogeneous acceleration pool; the management core is any one of the plurality of computing cores.

[0136] It can be seen that this embodiment provides a computing method that accelerates data transmission through Ethernet or remote direct data access, which can not only provide sufficient computing power support for the operation of the task, but also provide high bandwidth and low latency for high-speed communication and large data transmission of the task, which is conducive to the rapid and stable operation of the model training task.

[0137] An electronic device provided in an embodiment of the present application is introduced below. The electronic device described below can be referenced to other embodiments described in this document.

[0138] The present application discloses an electronic device, including:

[0139] Memory, used to store computer programs;

[0140] A processor is used to execute the computer program to implement the method disclosed in any of the above embodiments.

[0141] Furthermore, the present application also provides an electronic device. The electronic device can be Fig.17 The server shown can also be Fig.18 Terminal shown. Fig.17 and Fig.18 All of them are structural diagrams of electronic devices according to an exemplary embodiment, and the contents in the diagrams cannot be regarded as any limitation on the scope of use of the present application.

[0142] Fig.17 A schematic diagram of the structure of a server provided in an embodiment of the present application. The server may specifically include: at least one processor, at least one memory, a power supply, a communication interface, an input / output interface, and a communication bus. The memory is used to store a computer program, which is loaded and executed by the processor to implement the relevant steps in the calculation disclosed in any of the aforementioned embodiments.

[0143] In this embodiment, the power supply is used to provide working voltage for each hardware device on the server; the communication interface can create a data transmission channel between the server and external devices, and the communication protocol it follows is any communication protocol that can be applied to the technical solution of the present application, and is not specifically limited here; the input and output interface is used to obtain external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs and is not specifically limited here.

[0144] In addition, the memory as a carrier for resource storage can be a read-only memory, random access memory, disk or CD, etc. The resources stored thereon include operating system, computer programs and data, etc. The storage method can be temporary storage or permanent storage.

[0145] The operating system is used to manage and control the hardware devices and computer programs on the server to realize the operation and processing of the data in the memory by the processor, and it can be Windows Server, Netware, Unix, Linux, etc. In addition to computer programs that can be used to complete the calculation method disclosed in any of the aforementioned embodiments, computer programs can also further include computer programs that can be used to complete other specific tasks. In addition to data such as application update information, data can also include data such as application developer information.

[0146] Fig.18 A schematic diagram of the structure of a terminal provided in an embodiment of the present application, the terminal may specifically include but is not limited to a smart phone, a tablet computer, a laptop computer or a desktop computer, etc.

[0147] Generally, the terminal in this embodiment includes: a processor and a memory.

[0148] Among them, the processor may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor may be implemented in at least one hardware form of DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), and PLA (Programmable Logic Array). The processor may also include a main processor and a coprocessor. The main processor is a processor for processing data in the awake state, also known as a CPU (Central Processing Unit); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor may be integrated with a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor may also include an AI (Artificial Intelligence) processor, which is used to process computing operations related to machine learning.

[0149] The memory may include one or more computer non-volatile storage media, which may be non-transitory. The memory may also include high-speed random access memory, and non-volatile memory, such as one or more disk storage devices, flash memory storage devices. In this embodiment, the memory is used to store at least the following computer program, wherein, after the computer program is loaded and executed by the processor, it can implement the relevant steps in the computing method performed by the terminal side disclosed in any of the aforementioned embodiments. In addition, the resources stored in the memory may also include an operating system and data, etc., and the storage method may be temporary storage or permanent storage. Among them, the operating system may include Windows, Unix, Linux, etc. The data may include, but is not limited to, update information of the application.

[0150] In some embodiments, the terminal may also include a display screen, an input and output interface, a communication interface, a sensor, a power supply, and a communication bus.

[0151] Those skilled in the art will understand that Fig.18 The structure shown in the figure does not constitute a limitation on the terminal, and may include more or fewer components than those shown in the figure.

[0152] A non-volatile storage medium provided in an embodiment of the present application is introduced below. The non-volatile storage medium described below can be cross-referenced with other embodiments described herein.

[0153] A non-volatile storage medium for storing a computer program, wherein the computer program, when executed by a processor, implements the computing method disclosed in the above-mentioned embodiment. The non-volatile storage medium is a computer-readable non-volatile storage medium, which, as a carrier for storing resources, may be a read-only memory, a random access memory, a disk or an optical disk, etc. The resources stored thereon include an operating system, a computer program and data, etc., and the storage method may be temporary storage or permanent storage.

[0154] A computer program product provided in an embodiment of the present application is introduced below. The computer program product described below can be cross-referenced with other embodiments described in this document.

[0155] A computer program product comprises a computer program / instruction, which implements the steps of the aforementioned disclosed computing method when executed by a processor.

[0156] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0157] The steps of the method or algorithm described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of non-volatile storage medium known in the art.

[0158] Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A computing system, characterized in that: include: A computing resource pool, at least one heterogeneous acceleration pool, and an Ethernet switching module connected between the computing resource pool and the at least one heterogeneous acceleration pool; The at least one heterogeneous acceleration pool includes: a plurality of acceleration cards; each acceleration card includes: an Ethernet controller and at least one computing core, the Ethernet controller communicates with the computing core in a remote direct data access manner; Each accelerator card in the at least one heterogeneous acceleration pool communicates with the Ethernet switching module via Ethernet or remote direct data access; The computing resource pool includes: a plurality of computing cores, and the same computing core has a binding relationship with at least one accelerator card in the at least one heterogeneous acceleration pool; The multiple computing cores include a management core, which is used to manage each accelerator card in the at least one heterogeneous acceleration pool and the binding relationship, and distribute processing tasks to each accelerator card in the at least one heterogeneous acceleration pool.

2. The computing system according to claim 1, characterized in that Each acceleration card in the at least one heterogeneous acceleration pool includes: a gold finger and a power connector; the gold finger and the power connector connect each device in the corresponding acceleration card and provide power to each device in the corresponding acceleration card.

3. The computing system according to claim 2, characterized in that The gold fingers and the power connector in each accelerator card in the at least one heterogeneous acceleration pool are supplied with power simultaneously during the startup process of the corresponding accelerator card.

4. The computing system according to claim 1, characterized in that: A switching chip is connected between the Ethernet controller in each acceleration card in the at least one heterogeneous acceleration pool and the computing core in the corresponding acceleration card; Correspondingly, the Ethernet controller in each acceleration card in the at least one heterogeneous acceleration pool communicates with the computing core in the corresponding acceleration card in a remote direct data access manner through the switching chip.

5. The computing system according to claim 1, characterized in that: Each acceleration card in the at least one heterogeneous acceleration pool includes: a homologous clock device, and the homologous clock device is connected to the computing core, the switching chip and the Ethernet controller in the corresponding acceleration card.

6. The computing system according to claim 5, characterized in that: Each accelerator card in the at least one heterogeneous acceleration pool includes: a clock generator, wherein the clock generator is connected between a homologous clock device and a computing core, between a homologous clock device and a switching chip, and between a homologous clock device and an Ethernet controller in the corresponding accelerator card; Correspondingly, the clock generator is used to select a clock source for the computing core, switching chip and Ethernet controller in the corresponding acceleration card; the clock source is: a homologous clock device in the corresponding acceleration card or a clock device in the computing core bound to the corresponding acceleration card.

7. The computing system according to claim 1, characterized in that: Each acceleration card in the at least one heterogeneous acceleration pool includes: a control unit; the control unit is used to implement timing control of information transmission in the corresponding acceleration card.

8. The computing system according to claim 1, wherein: Each acceleration card in the at least one heterogeneous acceleration pool includes: a link selector; the link selector is connected to the computing core, the switching chip, the Ethernet controller, the homologous clock device, the power supply device and the control unit in the corresponding acceleration card.

9. The computing system according to claim 1, characterized in that: The Ethernet switching module includes: at least one switch; the at least one switch connects the computing resource pool and the at least one heterogeneous acceleration pool.

10. The computing system according to claim 1, characterized in that Each accelerator card in the at least one heterogeneous acceleration pool includes: a first node controller; the first node controller is used to collect device information and operation information in the corresponding accelerator card; Correspondingly, each computing core in the computing resource pool includes: a second node controller; the second node controller is used to collect device information and operation information in the corresponding computing core; Correspondingly, the Ethernet switching module includes: a central controller; the central controller is used to collect device information and operation information in the acceleration card collected by the first node controller, and device information and operation information in the computing core collected by the second node controller.

11. The computing system according to claim 10, characterized in that: The first node controller is used to collect status information of the acceleration chip in the corresponding acceleration card and sensor data of the board.

12. The computing system according to claim 10, characterized in that: The second node controller is used to collect core operation information and sensor data in the corresponding computing core.

13. The computing system according to claim 10, characterized in that: The central controller is used to construct a topology map including each computing core in the computing resource pool and each acceleration card in the at least one heterogeneous acceleration pool according to the collected information.

14. The computing system according to claim 10, characterized in that: The central controller is used to synchronize the collected information to the management core in the computing resource pool; Correspondingly, the management core manages each accelerator card in the at least one heterogeneous acceleration pool and the binding relationship according to the received synchronization information, and distributes processing tasks to each accelerator card in the at least one heterogeneous acceleration pool.

15. The computing system according to claim 10, characterized in that: The management core is used to formulate corresponding task allocation strategy and binding relationship adjustment strategy according to the received synchronization information.

16. The computing system according to claim 10, characterized in that: The central controller is used to generate log data according to the collected information, and analyze the log data to perform fault diagnosis.

17. The computing system according to any one of claims 1 to 16, characterized in that: The computing system further includes: a bus switching module connected to the at least one heterogeneous acceleration pool; the bus switching module is also connected to another computing resource pool.

18. A calculation method, characterized in that: Applied to management core, including: Receive processing tasks; Sending the processing task to an Ethernet switching module in the computing system, so that the Ethernet switching module distributes the processing task to at least one heterogeneous acceleration pool in the computing system through Ethernet or remote direct data access; The computing system includes: a computing resource pool, the at least one heterogeneous acceleration pool, and the Ethernet switching module connected between the computing resource pool and the at least one heterogeneous acceleration pool; The at least one heterogeneous acceleration pool includes: a plurality of acceleration cards; each acceleration card includes: an Ethernet controller and at least one computing core, the Ethernet controller communicates with the computing core in a remote direct data access manner; Each accelerator card in the at least one heterogeneous acceleration pool communicates with the Ethernet switching module via Ethernet or remote direct data access; The computing resource pool includes: multiple computing cores, and the same computing core has a binding relationship with at least one acceleration card in the at least one heterogeneous acceleration pool; the management core is any one of the multiple computing cores.

19. An electronic device, characterized in that: include: Memory for storing computer programs; A processor, configured to execute the computer program to implement the method according to claim 18.

20. A non-volatile storage medium, characterized in that: Used to store a computer program, wherein the computer program implements the method according to claim 18 when executed by a processor.

21. A computer program product comprising a computer program / instructions, characterized in that The computer program / instructions implement the method of claim 18 when executed by a processor.

Images