Reset circuit, reset method and multi-core heterogeneous system

Abstract

The invention discloses a reset circuit, a reset method and a multi-core heterogeneous system. The reset circuit is applied to the multi-core heterogeneous system comprising at least two hardware domains. Each mutually isolated hardware domain is composed of a plurality of processor cores with different architectures in the multi-core heterogeneous system and hardware resources connected with each processor core; each hardware domain and the operating system corresponding to each hardware domain form each domain system; each domain system accesses system resources through a system bus; the reset circuit comprises a monitoring module which is used for monitoring each monitored object and obtaining a monitoring signal for each monitored object; the first processing module is used for acquiring a target reset mode from at least two reset modes according to the monitoring signal; processing the monitoring signal based on the target reset mode to obtain a first reset signal; and the reset control module is used for controlling the output of a first reset signal, and the output first reset signal is used for resetting the monitored object matched with the target reset mode.

Description

Technical Field

[0001] The present application relates to the field of reset technology, and in particular to a reset circuit, a reset method and a multi-core heterogeneous system. Background Art

[0002] In order to ensure the normal operation of the system, a combination of software and hardware is usually used to monitor each module in the system. In the combination of software and hardware, software is usually used to periodically initiate a "feeding the dog" operation to the watchdog circuit. The watchdog circuit performs a counting function and determines whether the count of the watchdog circuit can be cleared in time, thereby monitoring whether the operation is normal. If an abnormality is detected, the system can be restarted by resetting the system. In this combination of software and hardware, on the one hand, the frequent initiation of the "feeding the dog" operation by the software undoubtedly occupies software resources. On the other hand, the reset generated by the software combination has poor real-time performance and cannot meet the growing requirements. Summary of the invention

[0003] The present application provides a reset circuit, a reset method and a multi-core heterogeneous system to at least solve the above technical problems existing in the prior art.

[0004] According to a first aspect of the present application, a reset circuit is provided, which is applied to a multi-core heterogeneous system, wherein the multi-core heterogeneous system includes at least two hardware domains; each hardware domain is composed of a plurality of processor cores with different architectures in the multi-core heterogeneous system and hardware resources connected to each processor core, and the hardware domains are isolated from each other; each hardware domain and an operating system corresponding to each hardware domain constitute each domain system; each domain system accesses system resources through a system bus; the circuit includes:

[0005] A monitoring module, used to monitor each monitoring object and obtain a monitoring signal for each monitoring object, wherein each monitoring object includes at least one of a domain system, a system bus and a system resource;

[0006] A first processing module is used to obtain a target reset mode from at least two reset modes for the monitoring signal; based on the target reset mode, the monitoring signal is processed to obtain a first reset signal;

[0007] The reset control module is used to control the output of a first reset signal, and the output first reset signal is used to achieve the reset of the monitoring object matching the target reset mode.

[0008] In one possible implementation,

[0009] A second processing module, connected to the first processing module, for processing the first reset signal based on the target reset mode to obtain a second reset signal;

[0010] The reset control module is connected to the second processing module and is used to control the output of the second reset signal. The output second reset signal is used to reset the monitored object matching the target reset mode.

[0011] In one possible implementation, each reset mode includes a first reset parameter and a second reset parameter; the first reset parameters and the second reset parameters in different reset modes are different;

[0012] The first processing module is used to process the monitoring signal based on the first reset parameter in the target reset mode to obtain a first reset signal;

[0013] The second processing module is used to process the first reset signal based on the second reset parameter in the target reset mode to obtain a second reset signal;

[0014] The first reset parameter and the second reset parameter in the target reset mode are different.

[0015] In one possible implementation, the monitoring signal is an M-channel signal, where M is a positive integer greater than or equal to 2; the target reset mode has a first reset parameter, and the first reset parameter includes M-channel reset parameters;

[0016] The first processing module is used to perform a logic operation on each monitoring signal and each reset parameter to obtain a first logic signal of each channel, wherein each first logic signal is a logic signal for each monitoring object;

[0017] The first logic signals of each channel are sorted by using the sorting rule for each monitored object to obtain the first reset signal.

[0018] In one possible implementation, each monitoring signal includes M bits of sub-signals, and each reset parameter includes M bits of sub-parameters;

[0019] The first processing module is used to perform a bitwise logical AND operation on each sub-signal in each monitoring signal and each sub-parameter in each reset parameter to obtain an intermediate signal of each channel, wherein the intermediate signal is M bits;

[0020] A logic OR operation is performed on the M-bit intermediate signals of each path to obtain the first logic signal of each path.

[0021] In one possible implementation, the first reset signal includes M bit sub-signals; the second reset parameter includes M bit sub-parameters; wherein M is a positive integer greater than or equal to 2;

[0022] The second processing module is used to perform bitwise logic operations on each sub-signal in the first reset signal and each sub-parameter in the second reset parameter to obtain each second logic signal, wherein each second logic signal is a logic signal for each monitored object;

[0023] The second logic signals are sorted according to the sorting rule for each monitored object to obtain the second reset signal.

[0024] In one possible implementation manner, the second processing module is used to sample each sub-signal under the action of a sampling clock to obtain each sampled sub-signal;

[0025] Performing an inversion operation on each sampled sub-signal;

[0026] Perform a bitwise logical AND operation on each inverted sampled sub-signal obtained by the inversion operation and each sub-parameter in the second reset parameter to obtain each second logic signal.

[0027] In one possible implementation, the target reset mode is a first reset mode or a second reset mode, and the monitored object to be reset in the first reset mode is different from the monitored object to be reset in the second reset mode.

[0028] According to a second aspect of the present application, a reset method is provided, which is applied to a multi-core heterogeneous system, wherein the multi-core heterogeneous system includes at least two hardware domains; each hardware domain is composed of a plurality of processor cores with different architectures in the multi-core heterogeneous system and hardware resources connected to each processor core, and the hardware domains are isolated from each other; each hardware domain and an operating system corresponding to each hardware domain constitute each domain system; each domain system accesses system resources through a system bus; the method includes:

[0029] Monitor each monitoring object to obtain a monitoring signal for each monitoring object, wherein each monitoring object includes at least one of a domain system, a system bus, and a system resource;

[0030] For the monitoring signal, obtain a target reset mode from at least two reset modes; based on the target reset mode, process the monitoring signal to obtain a first reset signal;

[0031] The output of the first reset signal is controlled, and the output first reset signal is used to achieve the reset of the monitoring object matching the target reset mode.

[0032] According to a third aspect of the present application, a multi-core heterogeneous system is provided, the multi-core heterogeneous system comprising at least two hardware domains; each hardware domain is composed of a plurality of processor cores with different architectures in the multi-core heterogeneous system and hardware resources connected to each processor core, and the hardware domains are isolated from each other; each hardware domain and the operating system corresponding to each hardware domain constitute each domain system; each domain system accesses system resources through a system bus; the multi-core heterogeneous system also includes the reset circuit described above.

[0033] According to a fourth aspect of the present application, an electronic device is provided, including:

[0034] at least one processor; and

[0035] a memory communicatively connected to the at least one processor; wherein,

[0036] The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method described in the present application.

[0037] According to a fifth aspect of the present application, a non-transitory computer-readable storage medium storing computer instructions is provided, wherein the computer instructions are used to execute the method described in the present application.

[0038] According to a sixth aspect of the present application, a computer program product is provided, comprising a computer program or instructions, which implement the method described in the present application when executed by a processor.

[0039] The technical solution of the present application is a hardware reset solution. Compared with the software-hard combination method in the related art, the monitoring signal is processed based on the target reset mode, which can quickly obtain the (first) reset signal, and can reset the abnormality in the first time, meeting the real-time requirements of the reset. This hardware reset solution of the present application can effectively avoid the occupation of software resources, so that limited software resources can be released.

[0040] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present application, nor is it intended to limit the scope of the present application. Other features of the present application will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] By reading the detailed description below with reference to the accompanying drawings, the above and other purposes, features and advantages of the exemplary embodiments of the present application will become easily understood. In the accompanying drawings, several embodiments of the present application are shown in an exemplary and non-limiting manner, wherein:

[0042] In the drawings, the same or corresponding reference numerals represent the same or corresponding parts.

[0043] Figure 1 The schematic diagram of the multi-core heterogeneous system in the embodiment of the present application is shown Figure 1 ;

[0044] Figure 2 The schematic diagram of the multi-core heterogeneous system in the embodiment of the present application is shown Figure 2 ;

[0045] Figure 3 The schematic diagram of the multi-core heterogeneous system in the embodiment of the present application is shown Figure 3 ;

[0046] Figure 4 The schematic diagram of the reset circuit in the embodiment of the present application is shown in FIG. Figure 1 ;

[0047] Figure 5 The schematic diagram of the reset circuit in the embodiment of the present application is shown in FIG. Figure 2 ;

[0048] Figure 6 An example of a reset circuit in an embodiment of the present application is shown Figure 1 ;

[0049] Figure 7 A schematic diagram showing the specific composition of the reset circuit in an embodiment of the present application is shown;

[0050] Figure 8 An example of a reset circuit in an embodiment of the present application is shown Figure 2 ;

[0051] Fig. 9 A schematic diagram of the implementation flow of the reset method in an embodiment of the present application is shown;

[0052] Fig.10 A schematic diagram of the structure of an electronic device in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0053] In order to make the purpose, features, and advantages of the present application more obvious and easy to understand, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0054] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings. The described embodiments should not be regarded as limiting the present application. All other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of this application.

[0055] In the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it can be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0056] In the following description, the terms "first\second" involved are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It can be understood that "first\second" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.

[0057] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0058] It should be understood that in the various embodiments of the present application, the size of the serial number of each implementation process does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0059] The reset circuit of the present application is located in a multi-core heterogeneous system, and the processing logic of the reset method of the present application is deployed in the multi-core heterogeneous system. In the embodiment of the present application, the multi-core heterogeneous system is a multi-core heterogeneous chip. A multi-core heterogeneous chip refers to a chip that integrates two or more processor cores in a single chip. For example, a single SOC (system on chip) chip with two or more processor cores integrated. Each processor core in the multi-core heterogeneous chip can be used as an independent processor, and can independently run the instructions that each processor core needs to run to achieve the tasks that each processor core needs to achieve. It can be understood that the multi-core heterogeneous chip is a chip with a multi-core processor. Compared with a single-core processor chip, the independent operation of each core task can speed up the operation speed and improve the multi-task execution capability, thereby bringing the advantage of high performance. And the multi-core processor is set on the same chip, which has the advantage of low cost.

[0060] like Figure 1As shown, the multi-core heterogeneous chip includes multiple processor cores, and the multiple processor cores include a first processor core, a second processor core...an Lth processor core. L is a positive integer greater than or equal to 2, and is flexibly set according to actual conditions. Among the multiple processor cores, each processor core is equivalent to a computing engine, and its type and / or number may be different. Among them, the types of processor cores include cores with strong computing power and cores with strong real-time performance (fast computing). In actual applications, most of the multiple processor cores are processor cores of different types, and a few cores are processor cores of the same type. Alternatively, the multiple processor cores may be processor cores of different types, and thus the multi-core heterogeneous chip is composed of two or more processor cores with different architectures. The difference in the type and / or number of processor cores can achieve different architectures between processor cores to a certain extent.

[0061] In practical applications, among all processor cores, as long as there are two or more processor cores of different types, such processor cores can be called multi-core heterogeneous, and the chip including these processor cores can be regarded as a multi-core heterogeneous chip.

[0062] For example, since the embedded processor (ARM) has the advantages of low cost and low power consumption, the digital signal processor (DSP) has the advantage of digital dedicated processing, and the field programmable logic array (FPGA) has the advantage of high-speed processing. Each type of processor is used as a processor core. These types of processors are designed on the same SOC chip, and a multi-core heterogeneous SOC chip can be obtained.

[0063] like Figure 2 As shown, each processor core and the hardware resources connected to each processor core, such as a clock controller, an interrupt controller, a memory space, etc., constitute each hardware domain. That is, a multi-core heterogeneous chip includes multiple hardware domains. In a multi-core heterogeneous chip, each hardware domain is a collection of a group of hardware resources. Different hardware domains are isolated from each other, and this isolation can be regarded as a physical isolation, such as the hardware design in the same hardware domain is in a similar position of the multi-core heterogeneous chip, and the hardware design in different hardware domains is in different positions of the multi-core heterogeneous chip to achieve isolation in physical position. Of course, the mutual isolation between different hardware domains in the embodiment of the present application may not be physical isolation, but logical isolation. This logical isolation can be reflected in: the hardware resources in the same hardware domain need to use the same communication identifier to access the hardware domain. That is, the hardware resources in the same hardware domain can access each other based on the communication identifier in the hardware domain. Hardware resources in different hardware domains are accessed using different communication identifiers.

[0064] In practical applications, it is preferred that the mutual isolation between different hardware domains is a logical isolation, which can at least save chip space.

[0065] like Figure 3 As shown, in a multi-core heterogeneous chip, an operating system can be configured for each hardware domain. For example, a first operating system is configured for the first hardware domain, a second operating system is configured for the second hardware domain, and so on. The operating systems configured for different hardware domains can be the same, can be different, and are preferably different. For example, the first operating system configured for the first hardware domain is a Linux system, and the second operating system configured for the second hardware domain is an Android system. Among them, since the Linux system has the characteristics of high security and the Android system has the characteristics of lightness, tasks with high security requirements in the multi-core heterogeneous system can be handed over to Linux for execution, and tasks that need to run lightly in the multi-core heterogeneous system can be handed over to the Android system for execution. Therefore, in a multi-core heterogeneous system, different operating systems on different hardware domains can be used to achieve efficient execution of each task.

[0066] In a multi-core heterogeneous chip, an operating system may be configured for each hardware domain in most hardware domains according to actual needs, and no operating system may be configured for a small number of hardware domains, depending on specific usage.

[0067] In the embodiment of the present application, there is also a communication demand between hardware domains. When there is a communication demand between different hardware domains, an inter-core communication mechanism can be used to realize the communication between hardware domains. Among them, the inter-core communication mechanism in the multi-core heterogeneous system includes a mailbox mechanism suitable for instruction transmission and a memory sharing mechanism suitable for data sharing. Inter-core communication within a single SOC chip can ensure that data is transmitted within the same chip, ensuring data security and transmission speed.

[0068] Generally, there are differences in hardware resources in different hardware domains, and such differences may be reflected in differences in hardware type, hardware model, hardware quantity, etc. Such differences can, to a certain extent, reflect the heterogeneity of multi-core heterogeneous systems. As can be seen from the previous introduction, the multi-core heterogeneity in this application is a concept at the hardware level and has nothing to do with the software level.

[0069] like Figure 1 As shown, the multi-core heterogeneous chip in the embodiment of the present application also includes various types of control units. Various types of control units include but are not limited to: a power control unit, a non-volatile storage control unit, a volatile storage control unit, etc. Among them, the power control unit is used to control the power supply unit to realize the supply of power to the multi-core heterogeneous chip. The non-volatile storage control unit is used to control the access of at least one processor core in the multi-core heterogeneous chip to the non-volatile storage unit. The volatile storage control unit is used to control the access of at least one processor core in the multi-core heterogeneous chip to the volatile storage unit.

[0070] Among them, the power supply unit, non-volatile storage unit, and volatile storage unit are hardware resources outside the multi-core heterogeneous chip and can be called when the multi-core heterogeneous chip needs them. In addition, the audio output unit (such as a speaker or loudspeaker), audio acquisition unit (such as a microphone), video output unit (such as a display) and other hardware are hardware resources outside the multi-core heterogeneous chip and can also be called when the multi-core heterogeneous chip needs them to achieve normal audio and video output.

[0071] The reset method of the embodiment of the present application is implemented on a multi-core heterogeneous system. The multi-core heterogeneous system involved in the reset method of the present application includes M hardware domains, where M is a positive integer greater than or equal to 2. The M hardware domains can be Figure 2 All or part of the L hardware domains shown, preferably all of the hardware domains. Each hardware domain corresponds to an operating system. For example, hardware domain 1 corresponds to a first operating system, hardware domain 2 corresponds to a second operating system, and hardware domain M corresponds to an Mth operating system. Each hardware domain is composed of a plurality of processor cores with different architectures in a multi-core heterogeneous system and hardware resources connected to each processor core, and each hardware domain is isolated from each other. Figure 3 For more information on the multi-core heterogeneous system shown in Figure 1 and / or Figure 2 The relevant instructions are as follows, and the repeated parts are not repeated.

[0072] In this application, the hardware domain and the operating system corresponding to the hardware domain may constitute a domain system, and a multi-core heterogeneous chip includes two or more such domain systems. Each domain system may access system resources through the system bus. System resources may include peripherals such as an integrated circuit bus (I2C), a universal asynchronous receiver and transmitter (UART), an interface (IO), and may also include resources that can be shared between domain systems, such as speakers, microphones, interrupt controllers, etc.

[0073] According to the role of the domain system, the domain system in the multi-core heterogeneous system can be roughly divided into two categories: one is the application domain, and the other is the management domain. Among them, the number of management domains can be one, two or more, preferably one. The number of application domains is usually two or more. Taking the application of a multi-core heterogeneous system to a vehicle as an example, the application domain is used to realize various functions of the vehicle, such as instrument functions and in-car entertainment functions (IVI functions). The management domain is used to manage each application domain. In actual applications, the instrument function and the in-car entertainment function can be integrated in different application domains. In this way, the multi-core heterogeneous system used in the vehicle has an application domain that includes at least an instrument domain and an IVI domain. Of course, in addition to the application domain and the management domain, according to actual application requirements, the multi-core heterogeneous system in this application may also include a small system domain and / or a security domain. Among them, the security domain is used to ensure the security of the multi-core heterogeneous system, and the small system domain is used to assist other domain systems to realize the powerful functions of the multi-core heterogeneous system. For example, the small system domain can realize accelerated startup.

[0074] The reset circuit and reset method provided by the present application are a solution to timely reset when an abnormality is detected at the hardware level. Compared with the combination of software and hardware in the related art, the use of a hardware circuit for reset is a hardware reset solution that can reset the abnormality in the first place, meet the real-time requirements of the reset, and avoid occupying software resources. The technical solution of the present application is described in detail below.

[0075] Figure 4 The schematic diagram of the reset circuit in the embodiment of the present application is shown in FIG. Figure 1 .like Figure 4 As shown, the circuit includes: a monitoring module, a first processing module and a reset control module.

[0076] The monitoring module is used to monitor each monitoring object and obtain a monitoring signal for each monitoring object. The monitoring objects include at least one of a domain system, a system bus and a system resource.

[0077] In the present application, the monitoring object can be a domain system, a system bus, a system resource of peripherals such as I2C, UART, etc. A separate monitoring module can be set for each monitoring object, and the same monitoring module can also be set for some or all monitoring objects. In practical applications, it is preferred to set a separate monitoring module for each monitoring object, and each monitoring module summarizes its own monitoring information to the total monitoring module. The monitoring module monitors the monitoring object mainly to monitor whether the monitoring object is abnormal. For example, if the monitoring module monitors that the monitoring signal-timeout (timeout or overflow) signal is 1, it is considered that the monitoring object is abnormal. If the monitoring signal-timeout signal is 0, it is considered that the monitoring object is normal. The opposite is also possible. Each monitoring object has its own monitoring signal. For example, the monitoring signal of each monitoring object is the timeout signal of the monitoring object. The monitoring module obtains the value of the timeout signal by regularly monitoring or irregularly monitoring the timeout signal of the monitoring object.

[0078] The first processing module is connected to the monitoring module and is used to obtain a target reset mode from at least two reset modes for the monitoring signal; based on the target reset mode, the monitoring signal is processed to obtain a first reset signal.

[0079] The present application provides four reset modes, namely, bypass mode, single module reset mode, multi-module reset mode and overall reset mode. If the bypass mode is used for reset, it means that the software and hardware methods in the relevant technology are used for reset, and the technical solution of the present application is not used for reset. If the single module reset mode, multi-module reset mode and overall reset mode are used, it means that the technical solution of the present application is used for reset. Among them, when the single module reset mode is used for reset, for a single monitored object that generates a timeout exception, only the single monitored object is reset. When the multi-module reset mode is used for reset, two or three objects among the multiple monitored objects are combined, and as long as one monitored object in the combination generates a timeout exception, all monitored objects in the combination are reset. When the overall reset mode is used for reset, as long as one monitored object generates a timeout exception, all monitored objects are reset. That is, the entire SOC is reset.

[0080] The target reset mode is one of the four reset modes mentioned above, which can be pre-set. Alternatively, it can be switched from a pre-set mode to another mode according to the actual application. For example, after the single module reset mode is pre-set as the target reset mode, a switching instruction is generated according to the actual application to switch the target reset mode from the single module reset mode to the multi-module reset mode. The switching of the target reset mode can be implemented at the software level or by a hardware circuit, without specific limitation.

[0081] Each reset mode has a corresponding reset parameter. The reset parameters in different reset modes are different. In different reset modes, different reset parameters are used to process the monitoring signal to obtain different (first) reset signals. For example, in the single-module reset mode, the reset parameters in the single-module reset mode are used to obtain a reset signal that only resets a single monitored object. In the multi-module reset mode, the reset parameters in the multi-module reset mode are used to obtain a reset signal that resets each monitored object in the combination. In the entire reset mode, the reset parameters in the overall reset mode are used to obtain a reset signal for resetting all monitored objects, that is, the entire SOC.

[0082] The reset control module is connected to the first processing module and is used to control the output of the first reset signal. The output first reset signal is used to reset the monitored object matching the target reset mode.

[0083] In the present application, the first processing module outputs a first reset signal to the reset control module. The first reset signal is output by the reset control module to the monitoring object that needs to be reset. The reset of the monitoring object matching the target reset mode can be understood as follows: in the single-module reset mode, the reset control module can output a reset signal only to a single monitoring object to reset the monitoring object. In the multi-module reset mode, the reset control module can output a reset signal to all monitoring objects in the combination to reset each monitoring object in the combination. In the overall reset mode, the reset control module can output a reset signal to the entire SOC to restart the SOC.

[0084] It can be understood that the target reset mode can be the first reset mode of the aforementioned four reset modes, such as the single-module reset mode, or the second reset mode of the aforementioned four reset modes, such as the multi-module reset mode. Because the monitoring object that needs to be reset in the single-module reset mode is a single object, and the monitoring object that needs to be reset in the multi-module reset mode is a combined object, the monitoring object to be reset in the first reset mode may be different from the monitoring object to be reset in the second reset mode. For example, in the single-module reset mode, peripheral 1 is reset. In the multi-module reset mode, the monitoring objects of the combination of peripheral 2, memory and domain system 1 are reset.

[0085] As can be seen from the previous description, the reset circuit is a hardware circuit. The technical solution of the present application is a reset performed by a hardware circuit, which is a hardware reset solution. Compared with the combination of software and hardware in the related art, the monitoring signal is processed based on the target reset mode, which can quickly obtain the (first) reset signal, and can reset the abnormality in the first time, meeting the real-time requirements of the reset. This hardware reset solution of the present application can effectively avoid the occupation of software resources, so that limited software resources can be released.

[0086] In addition, the present application provides a variety of reset modes, and the reset objects (monitoring objects that need to be reset) in different reset modes are different. Using a variety of reset modes, it is possible to reset a single monitoring object, a combination of monitoring objects, and all monitoring objects. That is, using different reset modes, it is possible to accurately reset the monitoring objects that need to be reset. The technical solution of the present application provides a technical support for accurate hardware reset. It can effectively avoid the problem in the related art that normal monitoring objects cannot work properly due to global reset. Alternatively, it can effectively avoid the problem that objects that do not need to be reset are also reset due to the reset of the reset object and cannot work properly.

[0087] Combination Figure 4 In the reset circuit shown, in one embodiment, the monitoring signal in the present application is M-channel signals, where M is a positive integer greater than or equal to 2. For example, there are M monitoring objects, and each monitoring object corresponds to one monitoring signal. The target reset mode has a (first) reset parameter, and the (first) reset parameter includes M-channel reset parameters. In the same reset mode, each monitoring object corresponds to a reset parameter.

[0088] For example, assuming that there are five monitoring objects, namely, domain system 1, system bus, memory, peripheral 1 and peripheral 2, and each monitoring object corresponds to one monitoring signal, there are M=5 monitoring signals in total (the first monitoring signal, the second monitoring signal ... the fifth monitoring signal). In the target reset mode, each monitoring object corresponds to a reset parameter, and there are M=5 reset parameters in total (the first reset parameter, the second reset parameter ... the fifth reset parameter).

[0089] Based on this, the first processing module in the present application is used to perform logical operations on each monitoring signal and each reset parameter to obtain the first logic signal of each channel, wherein each first logic signal is a logic signal for each monitoring object; and the first logic signals of each channel are sorted using the sorting rules for each monitoring object to obtain the first reset signal.

[0090] Exemplarily, a logical operation is performed on the 1st monitoring signal and the 1st reset parameter to obtain the (first) logic signal of the 1st channel, and a logical operation is performed on the 2nd monitoring signal and the 2nd reset parameter to obtain the (first) logic signal of the 2nd channel, and so on to obtain the (first) logic signals of each channel. Each logic signal corresponds to a monitoring object. For example, the 1st logic signal is a logic signal for domain system 1, and the 2nd logic signal is a logic signal for the system bus. According to the pre-set sorting rules for each monitoring object, such as, according to the sorting rule of domain system 1, system bus, memory, peripheral 1 and peripheral 2, the 1st to 5th logic signals are sorted, thereby obtaining the (first) reset signal output by the first processing module to the reset control module.

[0091] The above scheme can be regarded as a scheme for obtaining the (first) reset signal based on the logical operation of each monitoring signal and each reset parameter. The scheme is simple and easy to implement in engineering. With this scheme, the (first) reset signal can be obtained in the first time, thereby achieving timely or real-time reset of the object to be reset, meeting the real-time requirement.

[0092] As an implementation method, each monitoring signal includes M-bit sub-signals, and each reset parameter includes M-bit sub-parameters. Each monitoring signal and each reset parameter are divided into bits. Exemplarily, the first monitoring signal includes 5 sub-signals, from bit0 to bit 4. The first reset parameter includes 5 sub-parameters, from bit0 to bit 4. Thus, for each monitoring signal, the method for obtaining the first logic signal of each channel can be described as follows:

[0093] The first processing module is used to perform bit-by-bit logical AND operations on each sub-signal in each monitoring signal and each sub-parameter in each reset parameter to obtain an intermediate signal of each channel, wherein the intermediate signal is M bits; and perform a logical OR operation on the M-bit intermediate signal of each channel to obtain a first logic signal of each channel.

[0094] Exemplarily, a logical AND operation is performed on the sub-signal of bit0 of the first monitoring signal and the sub-parameter of bit0 of the first reset parameter to obtain a 1-bit (first) operation result. A logical AND operation is performed on the sub-signal of bit1 of the first monitoring signal and the sub-parameter of bit1 of the first reset parameter to obtain a 1-bit (second) operation result, and so on, until a logical AND operation is performed on the 5-bit sub-signal of the first monitoring signal and the 5-bit sub-parameter of the first reset parameter to obtain 5 1-bit operation results. These 5 1-bit operation results are sorted and used as the intermediate signal of the first channel. These 5 1-bit operation results are logically ORed to obtain the (first) logic signal of the first channel. The above is an explanation based on the first channel as an example. The process of obtaining the first logic signal of other channels is similar to that of the first channel and will not be repeated.

[0095] The above scheme can be regarded as a scheme for obtaining a (first) logic signal based on the logic operation of the sub-signal in the monitoring signal and the sub-parameter in the reset parameter. The scheme is simple and easy to implement in engineering. With this scheme, the accuracy and real-time performance of the first logic signal of each channel can be guaranteed, providing a technical support for timely or real-time acquisition of the (first) reset signal.

[0096] Figure 5 The schematic diagram of the reset circuit in the embodiment of the present application is shown in FIG. Figure 2 .like Figure 5 As shown, the circuit includes: a monitoring module, a first processing module connected to the monitoring module, a second processing module connected to the first processing module, and a reset control module connected to the second processing module. Figure 4 The description is repeated and no further elaboration is given.

[0097] The second processing module is connected to the first processing module, and is used to process the first reset signal based on the target reset mode to obtain a second reset signal.

[0098] The reset control module is connected to the second processing module and is used to control the output of the second reset signal. The output second reset signal is used to reset the monitored object matching the target reset mode.

[0099] It can be seen from the above content that in the technical solution of the present application, the reset control module can directly use the first reset signal obtained by the first processing module as the reset signal for the monitored object that needs to be reset. The second reset signal obtained by the second processing module can also be used as the reset signal for the monitored object that needs to be reset. Different from the scheme in which the first processing module obtains the first reset signal, the second processing module obtains the second reset signal by processing the first reset signal based on the target reset mode. This scheme of obtaining the second reset signal that ultimately resets the monitored object through the first reset signal and the target reset mode provides another technical support for hardware reset of the monitored object.

[0100] For the aforementioned four reset modes, in each reset mode, a (first) reset parameter is provided for the first processing module, so that the first processing module processes the monitoring signal based on the first reset parameter in the target reset mode, thereby obtaining a first reset signal. In addition, in the present application, in each reset mode, a (second) reset parameter is provided for the second processing module. It is possible that in the same reset mode, such as the target reset mode, there is a difference between the first reset parameter provided for the first processing module and the second reset parameter provided for the second processing module. It is also possible that in different reset modes, the first reset parameters provided for the first processing module are different, and the second reset parameters provided for the second processing module are different. In the present application, the second processing module can process the first reset signal based on the second reset parameter in the target reset mode, thereby obtaining a second reset signal.

[0101] It can be seen that in the present application, the first processing module is based on the (first) reset parameter and the monitoring signal in the target reset mode to obtain the first reset signal. The second processing module is based on the (second) reset parameter and the first reset signal in the target reset mode to obtain the second reset signal. Regardless of whether the reset signal output by the reset control module to the monitoring object that needs to be reset is the first reset signal or the second reset signal, the reset signal output to the monitoring object that needs to be reset is based on the target reset mode. It can be seen that which mode of the four reset modes is selected as the target reset mode needs to be combined with actual application. In each reset mode, the configuration of the two reset parameters (the first reset parameter and the second reset parameter) also needs to be combined with actual application. In the present application, based on the first reset parameter and the monitoring signal in the target reset mode, the scheme of obtaining the first reset signal can ensure the accuracy of the first reset signal. Based on the second reset parameter and the first reset signal in the target reset mode, the scheme of obtaining the second reset signal can ensure the accuracy of the second reset signal. The accuracy of the two reset signals can ensure the accuracy of the reset of the monitoring object, thereby achieving accurate reset and avoiding the problem that the normal monitoring object cannot work normally due to global reset.

[0102] Combination Figure 5 In the reset circuit shown in one embodiment, the first reset signal and the second reset parameter can be divided into bits respectively. In this way, the first reset signal includes M sub-signals. The second reset parameter includes M sub-parameters. Wherein M is a positive integer greater than or equal to 2. Exemplarily, the first reset signal includes 5 1-bit sub-signals, from bit0 to bit 4. The second reset parameter includes 5 1-bit sub-parameters, from bit0 to bit 4. In this way, the second processing module can perform bitwise logical operations on each sub-signal in the first reset signal and each sub-parameter in the second reset parameter to obtain each second logic signal, wherein each second logic signal is a logic signal for each monitored object. Using the sorting rule for each monitored object, the second logic signals are sorted to obtain the second reset signal. The sub-signal of bit0 in the first reset signal and the sub-parameter of bit0 in the second reset parameter are logically operated to obtain a (first) operation result of 1 bit. A logic operation is performed on the sub-signal of bit 1 in the first reset signal and the sub-parameter of bit 1 in the second reset parameter to obtain a (second) operation result of 1 bit, and so on, until the 5-bit sub-signal in the first reset signal and the 5-bit sub-parameter in the second reset parameter are all logically operated to obtain 5 1-bit operation results. These 5 1-bit operation results are used as 5 second logic signals. Each (second) logic signal corresponds to a monitoring object. For example, the first logic signal is a logic signal for domain system 1, and the second logic signal is a logic signal for the system bus. According to the pre-set sorting rules for each monitoring object, such as the sorting rules of domain system 1, system bus, memory, peripheral 1 and peripheral 2, the first logic signal to the fifth logic signal are sorted, thereby obtaining the (second) reset signal output by the second processing module to the reset control module.

[0103] The above scheme can be regarded as a scheme of obtaining the (second) reset signal based on the logic operation of the first reset signal and the second reset parameter. The scheme is simple and easy to implement in engineering. With this scheme, the (second) reset signal can be obtained in the first time, thereby achieving timely or real-time reset of the object to be reset, meeting the real-time requirement.

[0104] In practical applications, the first reset signal is a long level signal, and the SOC works with a certain working clock, so it is necessary to convert the first reset signal, which is a long level signal, into a level signal that can adapt to the working clock of the SOC through the second processing module, and then obtain each second logic signal through the aforementioned bitwise logic operation of the second processing module. In implementation, it is possible that, under the action of the sampling clock, the second processing module samples each sub-signal to obtain each sampled sub-signal. The second processing module performs an inversion operation on each sampled sub-signal, and then performs a bitwise logic AND operation on each inverse sampled sub-signal obtained by the inversion operation and each sub-parameter in the second reset parameter, thereby obtaining each second logic signal. In this way, the second reset signal output by the second processing module to the reset control module can successfully realize the handshake function between modules, thereby ensuring the successful reset of the monitored object.

[0105] Combine the following Figure 6 , Figure 7 and Figure 8 , and explain the technical solution of this application in detail.

[0106] Combination Figure 6 As shown, the monitoring object includes the central processing unit (CPU), system bus, memory, peripheral 1 and peripheral 2 of the domain system as an example for explanation, and peripheral 1 and peripheral 2 can be two different types of peripherals. For example, peripheral 1 can be an I2C interface, and peripheral 2 can be a UART interface. In this application scenario, a bus_mon module for monitoring the monitoring object is set on each monitoring object. The bus_mon module on each monitoring object is connected to the monitoring module of the reset circuit. When the bus_mon module on the monitoring object monitors the timeout signal, the timeout signal is transmitted to the monitoring module. The monitoring module transmits the signal to the first processing module, and after being processed by the first processing module, a first reset signal is obtained and transmitted to the second processing module. After being processed by the second processing module, a second reset signal is obtained, and the second reset signal is transmitted to the reset control module. The reset control module outputs a reset control signal to the monitoring object that needs to be reset, so that the monitoring object can be reset.

[0107] exist Figure 7In this example, to_mon module is used as the monitoring module, rst_gen module is used as the first processing module, and rst_hds module is used as the second processing module. In this application scenario, to_cpu represents the signal monitored by the CPU, to_bus represents the signal monitored by the system bus, to_m represents the signal monitored by the memory, to_p1 represents the signal monitored by peripheral 1, and to_p2 represents the signal monitored by peripheral 2. The above signals can take the value of 1 when the timeout signal is monitored, and the value of 0 when the timeout signal is not monitored, and vice versa. If there is no special explanation, in this example, the value of 1 when the timeout signal is monitored and the value of 0 when the timeout signal is not monitored are used as an example for explanation.

[0108] Exemplarily, if it is monitored that the CPU has a timeout signal, to_cpu can be set to 1. If it is monitored that the system bus does not have a timeout signal, to_bus can be set to 0. In this way, when a monitoring cycle arrives, each of to_cpu, to_bus, to_m, to_p1 and to_p2 will have a value, either 1 or 0. According to the sorting rules for each monitored object, such as the sorting rules of CPU, system bus, memory, peripheral 1 and peripheral 2 in this scenario, to_cpu, to_bus, to_m, to_p1 and to_p2 are sorted to obtain a data to_o[4:0] with a width of M=5 bits. to_o[4:0] represents the values ​​monitored for the CPU, system bus, memory, peripheral 1 and peripheral 2 in a monitoring cycle from low to high. In this scenario, to_o[4:0] can be used as a monitoring signal obtained by the monitoring module in this application.

[0109] In the rst_gen module, there are 5 sub-modules, namely rst0_gen, rst1_gen, rst2_gen, rst3_gen and rst4_gen. Each sub-module corresponds to a monitoring object, for example, rst0_gen to rst4_gen correspond to CPU, system bus, memory, peripheral 1 and peripheral 2 respectively. Each sub-module includes 5 parallel AND gates and an OR gate connected to the 5 AND gates.

[0110] In each reset mode, a corresponding first reset parameter is set for the rst_gen module. Further, in each reset mode, the first reset parameter includes corresponding reset parameters set for the five submodules rst0_gen to rst4_gen. Assume that, in each reset mode, the corresponding reset parameter set for the rst0_gen submodule is rst0_cfg, the reset parameter set for the rst1_gen submodule is rst1_cfg, the reset parameter set for the rst2_gen submodule is rst2_cfg, the reset parameter set for the rst3_gen submodule is rst3_cfg, and the reset parameter set for the rst4_gen submodule is rst4_cfg. The five reset parameters rst0_cfg to rst4_cfg can be used as M-way reset parameters in this application.

[0111] As an implementation method, the bit width of rst0_cfg to rst4_cfg and the bit width of to_o[4:0] can be consistent with the number of monitored objects, both of which are 5 bits wide. In this way, rst0_cfg to rst4_cfg can be considered as rst0_cfg[4:0] to rst4_cfg[4:0].

[0112] In implementation, the to_mon module to_o[4:0] is divided into 5 paths, which are output to the rst0_gen~rst4_gen 5 sub-modules in the rst_gen module. Each sub-module processes to_o[4:0] by processing one path of to_o[4:0]. Take the rst0_gen path as an example to illustrate the processing process of each path, and refer to the understanding of the processing process of other paths.

[0113] The processing process for rst0_gen is: send to_o[0] in to_o[4:0] and rst0_cfg[0] in rst0_cfg[4:0] to rst0_gen (according to Figure 7The first AND gate in to_o[4:0] and rst0_cfg[1] in rst0_cfg[4:0] are sent to the second AND gate in rst0_gen. The two are sent to the AND gate to obtain result 2. Similarly, the result 3 of the logical AND of to_o[2] and rst0_cfg[2], the result 4 of the logical AND of to_o[3] and rst0_cfg[3], and the result 5 of the logical AND of to_o[4] and rst0_cfg[4]. Each of the results 1 to 5 can be 1 or 0. The results 1 to 5 are sent to the OR gate for logical OR operation, thereby obtaining the logic signal rst0_gen_o of rst0_gen. The logic signal rst0_gen_o can be 1 or 0.

[0114] Alternatively, in order from low to high, result 1 to result 5 form a 5-bit wide data result[4:0]. Among them, result[0] is the value of result 1, result[1] is the value of result 2, and so on, result[4] is the value of result 5. result[4:0] can be used as the intermediate signal of rst0_gen. Send result[4:0] to the OR gate for logical OR operation, thereby obtaining the logic signal rst0_gen_o of rst0_gen. Among them, to_o[0] to to_o[4] in to_o[4:0] can be used as each sub-signal in the monitoring signal. rst0_cfg[0] to rst0_cfg[4] in rst0_cfg[4:0] can be used as each sub-parameter in the reset parameter of rst0_gen.

[0115] According to the above processing of rst0_gen, similar processing is performed on other paths, thereby obtaining the logic signals rst1_gen_o to rst4_gen_o of rst1_gen to rst4_gen. According to the sorting rules for each monitoring object, rst0_gen_o to rst4_gen_o are sorted to obtain a 5-bit wide data rst_gen_o[4:0]. Among them, rst_gen_o[0] is rst0_gen_o, rst_gen_o[1] is rst1_gen_o, and so on, rst_gen_o[4] is rst4_gen_o. rst_gen_o[4:0] can be used as the first reset signal. Input rst_gen_o[4:0] to the rst_hds module.

[0116] Combination Figure 7 As shown, the rst_hds module includes a buffer, five AND gates connected to the buffer, and a DQ flip-flop connected to each AND gate. The five AND gates in the rst_hds module and the DQ flip-flops connected to each AND gate constitute five paths, each corresponding to a monitoring object. Figure 7 From top to bottom, each path corresponds to the CPU, system bus, memory, peripheral 1 and peripheral 2. It can be understood that the DQ flip-flop includes an input terminal, a data terminal (D terminal) and an output terminal (Q terminal). If the input terminal signal of the DQ flip-flop is 1, its output Q terminal is 1, and if the input terminal signal of the DQ flip-flop is 0, its output Q terminal is 0.

[0117] In each reset mode, the corresponding second reset parameter rst_en_reg is set for the rst_hds module. The bit width of rst_en_reg can be consistent with the number of monitored objects, which is 5 bits wide rst_en_reg[4:0]. rst_gen_o[4:0] is sent to the buffer of the rst_hds module. The signal on each bit in rst_gen_o[4:0] is a long level signal. In order to adapt the long level signal to the working clock of the SOC, the buffer samples the signal on each bit in rst_gen_o[4:0] under the action of the sampling clock of the SOC to obtain each sampled sub-signal, and each sampled sub-signal is inverted. If the data after the aforementioned inversion operation is rst_gen_o_sam[4:0], then rst_gen_o_sam[0] in rst_gen_o_sam[4:0] and rst_en_reg[0] in the second reset parameter rst_en_reg[4:0] can be sent to the rst_hds module (according to Figure 7 The first AND gate in the rst_hds module (from top to bottom) performs a logical AND operation and then sends it to the first DQ flip-flop. The rst_gen_o_sam[1] in rst_gen_o_sam[4:0] and the second reset parameter rst_en_reg[1] in rst_en_reg[4:0] can be sent to the second AND gate in the rst_hds module, perform a logical AND operation and then send it to the second DQ flip-flop. Similarly, the outputs of the five DQ flip-flops rst_req[0] to rst_req[4] are obtained. The rst_req[0] to rst_req[4] are sorted from low to high to obtain rst_req[4:0]. rst_req[4:0] can be used as the second reset signal.

[0118] Considering that rst_req[4:0] corresponds to the CPU, system bus, memory, peripheral 1 and peripheral 2 from low to high. Which bit in rst_req[4:0] takes the value of 1, it means that the corresponding monitoring object needs to be reset. For example, if rst_req[4:0]=00001, the lowest bit takes 1, and the monitoring object corresponding to the lowest bit is the CPU, which means that the CPU needs to be reset. If rst_req[4:0]=10000, the highest bit takes 1, and the monitoring object corresponding to the highest bit is peripheral 2, which means that peripheral 2 needs to be reset.

[0119] The rst_hds module outputs rst_req[4:0] to the reset control module, and the reset control module outputs a signal to each monitoring object, or outputs a control signal to the monitoring signal that needs to be reset, and does not output a control signal to other monitoring objects. Exemplarily, taking rst_req[4:0]=00001 as an example, the reset control module can output a signal to the CPU that can control it to reset, and does not output a signal to other monitoring objects or outputs a signal that does not control the reset.

[0120] It can be understood that the reset control module is a module in the SOC, which can realize the reset function of the monitored object. In the present application, when the first reset signal is obtained through the processing of the rst_gen module, the first reset signal needs to be output to the rst_hds module for processing to obtain the second reset signal. This is because compared with the first reset signal which is a long level signal, the second reset signal obtained after processing by the buffer, AND gate and DQ trigger in the rst_hds module is more suitable for realizing data handshake with the reset control module to realize hard reset and improve the handshake success rate, thereby ensuring the successful reset of the monitored object. From this point of view, in the hard reset scheme of the present application, the rst_gen module can be regarded as a hard reset generation module for generating a reset signal, and the rst_hds module can be regarded as a hard reset handshake module for realizing the handshake function.

[0121] Generally, when the reset control module has reset the monitored object, the reset circuit in the present application, specifically the rst_gen module, will receive a feedback signal - rst_ack signal, which is used to implement a zeroing operation on the DQ trigger to wait for the next reset process. It can be understood that the bit width of the rst_ack signal can be consistent with the number of monitored objects, which is a 5-bit bit width rst_ack[4:0]. Each bit width of the signal performs a zeroing operation on each DQ trigger.

[0122] As can be seen from the previous description, the present application provides four reset modes: bypass mode, single module reset mode, multi-module reset mode and overall reset mode. For the monitoring signal, one of the four reset modes is selected as the target reset mode. The rst_gen module processes the monitoring signal based on the first reset parameter in the target reset mode to obtain a first reset signal. The rst_hds module processes the first reset signal based on the second reset parameter in the target reset mode to obtain a second reset signal. In different reset modes, the first reset signal is different because the first reset parameter is configured differently. In different reset modes, the second reset parameter can be configured to be the same or different. In this scenario, the first reset parameter can be configured to be different and the second reset parameter can be configured to be the same.

[0123] In this application, the second reset parameter rst_en_reg[4:0] can be configured to all 0s. After passing through the AND gate and DQ trigger of the rst_hds module, the output rst_req[4:0]=00000 does not need to reset any monitored object, which is the bypass mode. In this case, it means that the hard reset solution provided in this application can be used for reset, and an existing reset solution such as a combination of soft and hard solutions can be used for reset.

[0124] In this application, each reset parameter rst0_cfg[4:0]~rst4_cfg[4:0] and the second reset parameter rst_en_reg[4:0] in the rst_gen module can be configured to all 1s. Figure 7 After the processing shown, rst_req[4:0]=11111, and all monitored objects need to be reset, that is, the SOC is reset as a whole, which is the overall reset mode.

[0125] In this application, in single module reset mode, if the first reset parameter is configured with rst0_cfg[4:0]=00001, rst1_cfg[4:0]=00010, rst2_cfg[4:0]=00100, rst3_cfg[4:0]=01000rst4_cfg[4:0]=10000, and the second reset parameter is configured with rst_en_reg[4:0]=11111, then if to_ o[4:0]=00001, that is, the CPU is detected to have a timeout signal. According to the above description of the processing process of the rst_gen module, each bit in to_o[4:0]=00001 and rst0_cfg[4:0]=00001 can be logically ANDed through their respective AND gates, and then logically ORed through the OR gate, so as to obtain the logic signal rst0_gen_o=1 of the rst0_gen path. Each bit in to_o[4:0]=00001 and rst1_cfg[4:0]=00010 can be logically ANDed through their respective AND gates, and then logically ORed through the OR gate, so as to obtain the logic signal rst1_gen_o=0 of the rst1_gen path. Each bit in to_o[4:0]=00001 and rst2_cfg[4:0]=00100 is logically ANDed through its own AND gate, and then logically ORed through the OR gate, so that the logic signal rst2_gen_o=0 of rst2_gen is obtained. Each bit in to_o[4:0]=00001 and rst3_cfg[4:0]=01000 is logically ANDed through its own AND gate, and then logically ORed through the OR gate, so that the logic signal rst3_gen_o=0 of rst3_gen is obtained. Each bit in to_o[4:0]=00001 and rst4_cfg[4:0]=10000 is logically ANDed through its own AND gate, and then logically ORed through the OR gate, so that the logic signal rst4_gen_o=0 of rst4_gen is obtained. It can be seen that the monitoring signal to_o[4:0]=00001 is processed by the rst_gen module based on the first reset parameter in the single module reset mode to obtain the first reset signal rst_gen_o[4:0]=00001. rst_gen_o[4:0]=00001 is sent to the rst_hds module.

[0126] After rst_gen_o[4:0]=00001 is processed by the buffer in the rst_hds module, the value remains unchanged, but it changes from a long level signal to a pulse signal. After the pulse signal 00001 and each bit of the second reset parameter rst_en_reg[4:0]=11111 are logically ANDed by each AND gate of the rst_hds module and the DQ trigger, rst_req[0]=1 is obtained, and rst_req[1]~rst_req[4] are all 0. That is, rst_req[4:0]=00001. In rst_req[4:0]=00001, the monitoring object corresponding to the bit with a value of 1 is the CPU, and the reset control module generates a signal to control the reset of the CPU to achieve the reset of only the CPU among the five monitoring objects. The above scheme can be used as a scheme for resetting a single monitoring object in the target reset mode of the single module reset mode.

[0127] In this application, in the multi-module reset mode, if the first reset parameter is configured with rst0_cfg[4:0]=01001, rst1_cfg[4:0]=01010, rst2_cfg[4:0]=00100, rst3_cfg[4:0]=01000, rst4_cfg[4:0]=10000, and the second reset parameter is configured with rst_en_reg[4:0]=11111, then if to_ o[4:0]=01000, that is, the timeout signal of peripheral 1 is detected. According to the above description of the processing process of the rst_gen module, each bit in to_o[4:0]=01000 and rst0_cfg[4:0]=01001 can be logically ANDed through their respective AND gates, and then logically ORed through the OR gate, so as to obtain the logic signal rst0_gen_o=1 of the rst0_gen path. Each bit in to_o[4:0]=01000 and rst1_cfg[4:0]=01010 can be logically ANDed through their respective AND gates, and then logically ORed through the OR gate, so as to obtain the logic signal rst1_gen_o=1 of the rst1_gen path. Each bit in to_o[4:0]=01000 and rst2_cfg[4:0]=00100 is logically ANDed through its own AND gate, and then logically ORed through the OR gate, so that the logic signal rst2_gen_o=0 of rst2_gen is obtained. Each bit in to_o[4:0]=01000 and rst3_cfg[4:0]=01000 is logically ANDed through its own AND gate, and then logically ORed through the OR gate, so that the logic signal rst3_gen_o=1 of rst3_gen is obtained. Each bit in to_o[4:0]=01000 and rst4_cfg[4:0]=10000 is logically ANDed through its own AND gate, and then logically ORed through the OR gate, so that the logic signal rst4_gen_o=0 of rst4_gen is obtained. It can be seen that the monitoring signal to_o[4:0]=01000 is processed by the rst_gen module based on the first reset parameter in the multi-module reset mode to obtain the first reset signal rst_gen_o[4:0]=01011. rst_gen_o[4:0]=01011 is sent to the rst_hds module.

[0128] After rst_gen_o[4:0]=01011 is processed by the buffer in the rst_hds module, the value remains unchanged, but it changes from a long level signal to a pulse signal. After the pulse signal 01011 and each bit of the second reset parameter rst_en_reg[4:0]=11111 are logically ANDed by each AND gate of the rst_hds module and the DQ trigger, rst_req[0]=1, rst_req[1]=1, rst_req[2]=0, rst_req[3]=1, rst_req[4]=0 are obtained. That is, rst_req[4:0]=01011. In rst_req[4:0]=01011, the monitoring objects corresponding to the bits with a value of 1 are the CPU, the system bus, and the peripheral 1. The reset control module generates a signal to control the reset of the CPU, the system bus, and the peripheral 1, so as to achieve the reset of the three monitoring objects of the CPU, the system bus, and the peripheral 1 among the five monitoring objects. The above scheme can be used as a scheme for resetting the combined monitoring objects in the target reset mode of the multi-module reset mode.

[0129] It can be seen from the above scheme that for the case where the peripheral 1 monitored by the monitoring module has a timeout, that is, to_o[4:0]=01000, if the reset scheme is executed according to the values ​​of the first reset parameter and the second reset parameter in the single module reset mode, the result of rst_req[4:0]=01000 will be obtained in the end, and only the single monitoring object of peripheral 1 needs to be reset, and other monitoring objects do not need to be reset. If the reset scheme is executed according to the first reset parameter and the second reset parameter in the multi-module reset mode, the result of rst_req[4:0]=01011 will be obtained in the end, and not only the monitoring object of peripheral 1 needs to be reset, but also the CPU and the system bus need to be reset (all objects in the combination need to be reset). In the multi-module reset mode, the peripheral 1, the CPU and the system bus are combined as a combined monitoring or reset object. As long as one of the monitoring objects in the combined or reset monitoring object is abnormal, all monitoring objects in the combined or reset monitoring object are reset. In the combined monitoring object composed of peripheral 1, CPU and system bus, not only peripheral 1, the monitoring object, but also the CPU and system bus need to be reset because in actual applications, there is a possibility that the CPU accesses peripheral 1 through the system bus. If the CPU still accesses peripheral 1 through the system bus without knowing that peripheral 1 has timed out, the CPU and system bus will be hung due to the timeout of peripheral 1. In order to avoid the problem of non-operating due to the hang of the CPU and system bus, in the multi-module reset mode, peripheral 1, CPU and system bus are used as combined reset objects by configuring reset parameters such as rst0_cfg[4:0]~rst4_cfg[4:0] and rst_en_reg[4:0]. When peripheral 1 times out, peripheral 1 is reset together with the CPU and system bus in the combined monitoring object.

[0130] It can be seen from the above scheme that in the technical scheme of the present application, the values ​​of reset parameters such as rst0_cfg[4:0]~rst4_cfg[4:0] are different in different reset modes, thereby realizing different reset methods. It can also be considered that in the present application, different reset modes can be realized by different configurations of reset parameters such as rst0_cfg[4:0]~rst4_cfg[4:0]. For example, by different configurations of rst0_cfg[4:0]~rst4_cfg[4:0], a single-module reset mode for resetting only a single monitored object and a multi-module reset mode for resetting a combined monitored object can be realized.

[0131] Those skilled in the art will know that for a logical AND operation of two bits, the result is 1 only when both bits are 1. As long as one of the two bits is 0, the result is 0. For a logical OR operation of two bits, as long as one of the two bits is 1, the result is 1. When both bits are 0, the result of the logical OR operation is 0. The results of the logical AND operation and the logical OR operation in the above examples are calculated based on this principle.

[0132] As can be seen from the above description, in the hard reset solution of the present application, the rst_gen module can be regarded as a hard reset generation module for generating a reset signal, and the rst_hds module can be regarded as a hard reset handshake module for implementing a handshake function. Figure 8 As shown, the reset circuit of the present application may include: a monitoring module, a hard reset generation module, a hard reset handshake module, a reset control module, and a mode configuration module for configuring reset parameters such as rst0_cfg[4:0] to rst4_cfg[4:0], rst_en_reg[4:0]. The reset circuit may also include a reset state monitoring module for monitoring the state of the hard reset handshake module.

[0133] In the above scheme, the rst_gen module processes the monitoring signal based on the first reset parameter of the target reset mode to obtain the scheme of the first reset signal, which is implemented by hardware logic gate operations (logical AND operation of the AND gate and logical OR operation of the OR gate). The rst_hds module processes the first reset signal based on the second reset parameter of the target reset mode to obtain the scheme of the second reset signal, which is implemented by hardware operations (logical AND operation of the AND gate and operation of holding input of the DQ trigger). It can be seen that the present application is a reset scheme at the hardware level, referred to as a hardware reset scheme.

[0134] Compared with the software-hard combination method in the related art, the hard reset solution in the present application can directly realize the rapid acquisition of the reset signal at the hardware level, so that abnormal hardware or hardware that may have abnormalities (CPU, system bus, memory, peripherals) can be reset in the first time, meeting the real-time requirements of reset. The hardware reset solution in the present application can effectively avoid the occupation of software resources, so that limited software resources can be released.

[0135] In addition, the present application provides a variety of reset modes, each of which corresponds to its own (first) reset parameter. By using the (first) reset parameters in different reset modes, the monitoring object that needs to be reset can be accurately reset. This can effectively avoid the problem in the related art that the normal monitoring object cannot work normally due to the global reset, or avoid the problem that the object that does not need to be reset is reset by mistake.

[0136] Furthermore, the hard reset solution of the present application is realized by the cooperation between multiple components (AND gate, OR gate, trigger). The reset solution realized by the cooperation between hardware components is highly feasible in engineering and easy to apply.

[0137] In addition, the hard reset solution of the present application can greatly shorten the reset time compared with the software + watchdog reset solution in the related art, because it directly resets abnormal hardware or hardware that may cause abnormalities from the hardware level, and avoids the problem that the monitored object cannot be used normally due to the long reset time. It is a fast hard reset solution.

[0138] This fast hard reset solution can also find or locate which intervals in the memory have problems. During implementation, for the situation of accessing the memory, when the memory is reset twice or more times using the technical solution of the present application, the memory addresses accessed during the two or more resets are obtained, and based on the memory addresses accessed during the two or more resets, the problem intervals in the memory are obtained. Exemplarily, the memory is accessed in the order of memory addresses. If a hard reset of the memory is generated when address 1 is accessed, and a hard reset of the memory is also generated when address 2 is accessed, then the memory interval from address 1 to memory address 2 can be considered to be the problem interval.

[0139] Directly resetting abnormal hardware or hardware that may be abnormal from the hardware level can shorten the reset time, achieve fast reset, and meet the growing real-time requirements.

[0140] The present application provides a reset method, which is applied to a multi-core heterogeneous system, wherein the multi-core heterogeneous system includes at least two hardware domains; each hardware domain is composed of multiple processor cores with different architectures in the multi-core heterogeneous system and hardware resources connected to each processor core, and the hardware domains are isolated from each other; each hardware domain and the operating system corresponding to each hardware domain constitute each domain system; each domain system accesses system resources through a system bus. Fig. 9 As shown, the method includes:

[0141] S901: Monitor each monitoring object to obtain a monitoring signal for each monitoring object, wherein each monitoring object includes at least one of a domain system, a system bus, and a system resource;

[0142] S902: Obtain a target reset mode from at least two reset modes for the monitoring signal; and process the monitoring signal based on the target reset mode to obtain a first reset signal;

[0143] S903: Control the output of a first reset signal, where the output first reset signal is used to reset the monitored object matching the target reset mode.

[0144] In one embodiment, the method further comprises:

[0145] Based on the target reset mode, the first reset signal is processed to obtain a second reset signal; the output of the second reset signal is controlled, and the output second reset signal is used to achieve the reset of the monitoring object matching the target reset mode.

[0146] In one embodiment, each reset mode includes a first reset parameter and a second reset parameter; the first reset parameters and the second reset parameters in different reset modes are different; the method further includes:

[0147] Based on the first reset parameter in the target reset mode, the monitoring signal is processed to obtain a first reset signal;

[0148] Based on the second reset parameter in the target reset mode, the first reset signal is processed to obtain a second reset signal;

[0149] The first reset parameter and the second reset parameter in the target reset mode are different.

[0150] In one embodiment, the monitoring signal is an M-way signal, where M is a positive integer greater than or equal to 2; the target reset mode has a first reset parameter, and the first reset parameter includes M-way reset parameters; the method further includes:

[0151] Performing logic operations on each monitoring signal and each reset parameter to obtain a first logic signal of each channel, wherein each first logic signal is a logic signal for each monitoring object;

[0152] The first logic signals of each channel are sorted by using the sorting rule for each monitored object to obtain the first reset signal.

[0153] In one embodiment, each monitoring signal includes M sub-signals, and each reset parameter includes M sub-parameters; the method further includes:

[0154] Performing a bitwise logical AND operation on each sub-signal in each monitoring signal and each sub-parameter in each reset parameter to obtain an intermediate signal of each channel, wherein the intermediate signal is M bits;

[0155] A logic OR operation is performed on the M-bit intermediate signals of each path to obtain the first logic signal of each path.

[0156] In one embodiment, the first reset signal includes M-bit sub-signals; the second reset parameter includes M-bit sub-parameters; wherein M is a positive integer greater than or equal to 2; and the method further includes:

[0157] Performing bitwise logic operations on each sub-signal in the first reset signal and each sub-parameter in the second reset parameter to obtain each second logic signal, wherein each second logic signal is a logic signal for each monitored object;

[0158] The second logic signals are sorted according to the sorting rule for each monitored object to obtain the second reset signal.

[0159] In one embodiment, the method further comprises:

[0160] Under the action of the sampling clock, each sub-signal is sampled to obtain each sampled sub-signal;

[0161] Performing an inversion operation on each sampled sub-signal;

[0162] Perform a bitwise logical AND operation on each inverted sampled sub-signal obtained by the inversion operation and each sub-parameter in the second reset parameter to obtain each second logic signal.

[0163] In one embodiment, the target reset mode is a first reset mode or a second reset mode, and the monitored object to be reset in the first reset mode is different from the monitored object to be reset in the second reset mode.

[0164] It should be noted that the reset method and reset circuit of the embodiments of the present application belong to the same technical concept. For an understanding of the reset method, reference can be made to the relevant description of the implementation process or principle of the scheme in the reset circuit scheme, and the repetitive parts will not be repeated.

[0165] The third aspect of the present application also provides a multi-core heterogeneous system, which includes at least two hardware domains; each hardware domain is composed of multiple processor cores with different architectures in the multi-core heterogeneous system and hardware resources connected to each processor core, and the hardware domains are isolated from each other; each hardware domain and the operating system corresponding to each hardware domain constitute each domain system; each domain system accesses system resources through a system bus; the multi-core heterogeneous system also includes the reset circuit mentioned above.

[0166] According to an embodiment of the present application, the present application also provides an electronic device and a readable storage medium.

[0167] The electronic device includes at least one processor; and a memory connected to the at least one processor in communication; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can perform the reset method described in the present application. The computer instructions are used to enable the computer to perform the reset method described in the present application.

[0168] Fig.10A schematic block diagram of an example electronic device 800 that can be used to implement an embodiment of the present application is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workbenches, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present application described and / or required herein.

[0169] like Fig.10 As shown, the device 800 includes a computing unit 801, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 802 or a computer program loaded from a storage unit 808 into a random access memory (RAM) 803. In the RAM 803, various programs and data required for the operation of the device 800 can also be stored. The computing unit 801, the ROM 802, and the RAM 803 are connected to each other via a bus 804. An input / output (I / O) interface 805 is also connected to the bus 804.

[0170] A number of components in the device 800 are connected to the I / O interface 805, including: an input unit 806, such as a keyboard, a mouse, etc.; an output unit 807, such as various types of displays, speakers, etc.; a storage unit 808, such as a disk, an optical disk, etc.; and a communication unit 809, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 809 allows the device 800 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0171] The computing unit 801 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the computing unit 801 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, digital signal processors (DSPs), and any appropriate processors, controllers, microcontrollers, etc. The computing unit 801 performs the various methods and processes described above, such as the reset method. For example, in some embodiments, the reset method may be implemented as a computer software program, which is tangibly contained in a machine-readable medium, such as a storage unit 808. In some embodiments, part or all of the computer program may be loaded and / or installed on the device 800 via ROM 802 and / or communication unit 809. When the computer program is loaded into RAM 803 and executed by the computing unit 801, one or more steps of the reset method described above may be performed. Alternatively, in other embodiments, the computing unit 801 may be configured to perform the reset method in any other appropriate manner (e.g., by means of firmware).

[0172] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0173] The program code for implementing the method of the present application can be written in any combination of one or more programming languages. These program codes can be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that the program code, when executed by the processor or controller, implements the functions / operations specified in the flow chart and / or block diagram. The program code can be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0174] In the context of the present application, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, device, or equipment. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or equipment, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0175] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0176] The systems and techniques described herein may be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), and the Internet.

[0177] A computer system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The relationship of client and server is generated by computer programs running on respective computers and having a client-server relationship with each other. The server may be a cloud server, a server of a distributed system, or a server combined with a blockchain.

[0178] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A reset circuit, characterized in that: Applied to a multi-core heterogeneous system, the multi-core heterogeneous system includes at least two hardware domains; each hardware domain is composed of a plurality of processor cores with different architectures in the multi-core heterogeneous system and hardware resources connected to each processor core, and the hardware domains are isolated from each other; Each hardware domain and the operating system corresponding to each hardware domain constitute each domain system; Each domain system accesses system resources through a system bus; the circuit includes: A monitoring module, used to monitor each monitoring object and obtain a monitoring signal for each monitoring object, wherein each monitoring object includes at least one of a domain system, a system bus and a system resource; A first processing module is used to obtain a target reset mode from at least two reset modes for the monitoring signal; based on the target reset mode, the monitoring signal is processed to obtain a first reset signal; The reset control module is used to control the output of a first reset signal, and the output first reset signal is used to achieve the reset of the monitoring object matching the target reset mode.

2. The circuit according to claim 1, characterized in that A second processing module, connected to the first processing module, for processing the first reset signal based on the target reset mode to obtain a second reset signal; The reset control module is connected to the second processing module and is used to control the output of the second reset signal. The output second reset signal is used to reset the monitored object matching the target reset mode.

3. The circuit according to claim 2, characterized in that Each reset mode includes a first reset parameter and a second reset parameter; the first reset parameters and the second reset parameters in different reset modes are different; The first processing module is used to process the monitoring signal based on the first reset parameter in the target reset mode to obtain a first reset signal; The second processing module is used to process the first reset signal based on the second reset parameter in the target reset mode to obtain a second reset signal; The first reset parameter and the second reset parameter in the target reset mode are different.

4. The circuit according to any one of claims 1 to 3, characterized in that: The monitoring signal is an M-channel signal, where M is a positive integer greater than or equal to 2; the target reset mode has a first reset parameter, and the first reset parameter includes an M-channel reset parameter; The first processing module is used to perform a logic operation on each monitoring signal and each reset parameter to obtain a first logic signal of each channel, wherein each first logic signal is a logic signal for each monitoring object; The first logic signals of each channel are sorted by using the sorting rule for each monitored object to obtain the first reset signal.

5. The circuit according to claim 4, characterized in that Each monitoring signal includes M bits of sub-signals, and each reset parameter includes M bits of sub-parameters; The first processing module is used to perform a bitwise logical AND operation on each sub-signal in each monitoring signal and each sub-parameter in each reset parameter to obtain an intermediate signal of each channel, wherein the intermediate signal is M bits; A logic OR operation is performed on the M-bit intermediate signals of each path to obtain the first logic signal of each path.

6. The circuit according to claim 3, characterized in that The first reset signal includes M bit sub-signals; the second reset parameter includes M bit sub-parameters; wherein M is a positive integer greater than or equal to 2; The second processing module is used to perform bitwise logic operations on each sub-signal in the first reset signal and each sub-parameter in the second reset parameter to obtain each second logic signal, wherein each second logic signal is a logic signal for each monitored object; The second logic signals are sorted according to the sorting rule for each monitored object to obtain the second reset signal.

7. The circuit according to claim 6, characterized in that The second processing module is used to sample each sub-signal under the action of the sampling clock to obtain each sampled sub-signal; Performing an inversion operation on each sampled sub-signal; Perform a bitwise logical AND operation on each inverted sampled sub-signal obtained by the inversion operation and each sub-parameter in the second reset parameter to obtain each second logic signal.

8. The circuit according to claim 1, 2 or 3, characterized in that The target reset mode is a first reset mode or a second reset mode. The monitored object to be reset in the first reset mode is different from the monitored object to be reset in the second reset mode.

9. A resetting method, characterized in that: Applied to a multi-core heterogeneous system, the multi-core heterogeneous system includes at least two hardware domains; each hardware domain is composed of a plurality of processor cores with different architectures in the multi-core heterogeneous system and hardware resources connected to each processor core, and the hardware domains are isolated from each other; Each hardware domain and the operating system corresponding to each hardware domain constitute each domain system; Each domain system accesses system resources through a system bus; the method includes: Monitor each monitoring object to obtain a monitoring signal for each monitoring object, wherein each monitoring object includes at least one of a domain system, a system bus, and a system resource; For the monitoring signal, obtain a target reset mode from at least two reset modes; based on the target reset mode, process the monitoring signal to obtain a first reset signal; The output of the first reset signal is controlled, and the output first reset signal is used to achieve the reset of the monitoring object matching the target reset mode.

10. A multi-core heterogeneous system, characterized in that: The multi-core heterogeneous system includes at least two hardware domains; each hardware domain is composed of multiple processor cores with different architectures in the multi-core heterogeneous system and hardware resources connected to each processor core, and the hardware domains are isolated from each other; each hardware domain and the operating system corresponding to each hardware domain constitute each domain system; each domain system accesses system resources through a system bus; the multi-core heterogeneous system also includes the reset circuit described in any one of claims 1-8.

Images