Instruction classification processing method and device, terminal equipment and storage medium

Abstract

The invention relates to the technical field of instruction processing, and discloses an instruction classification processing method and device, terminal equipment and a storage medium. The method comprises the following steps: when an instruction packet issued by an upper computer is received, classifying instructions in the instruction packet; according to the type of the instruction, the instruction packet is distributed to parallel threads of the corresponding type, and meanwhile the instruction packet is cached to a cache space corresponding to the parallel threads; and when the instruction packet is called, sequentially calling the instruction packet from the cache space according to the storage sequence, analyzing the instruction packet to obtain a corresponding function execution signal, and outputting the function execution signal. The instructions are processed in parallel and cached, so that the processing efficiency is improved, and the instructions are prevented from being lost.

Description

Technical Field

[0001] The present application relates to the technical field of instruction processing, and in particular to an instruction classification processing method, apparatus, terminal device and storage medium. Background Art

[0002] In the electronic device development system, communication between devices or chips is necessary. Only with communication can devices or chips interact with each other. In general, the communication process uses common buses such as UART, PCIE, etc., and then formulates a communication protocol to carry interactive instructions according to the application scenario. Generally, when the device receives the communication, it will parse it according to the formulated protocol and execute the corresponding operation of the instruction. This is feasible for the scenario of slow and intermittent control instructions. However, when the device continuously receives various control instructions from the host computer, if it still executes them serially after parsing, it will cause the continuous same type of instructions to be incomplete and subsequently lost, and it will cause different types of instructions to be blocked. Obviously, such a device has limitations and is prone to errors. Summary of the invention

[0003] In view of this, an embodiment of the present application provides an instruction classification processing method, which can effectively solve problems such as instruction loss and blocking.

[0004] In a first aspect, an embodiment of the present application provides an instruction classification processing method, comprising:

[0005] When receiving an instruction packet sent by a host computer, classifying the instructions in the instruction packet;

[0006] According to the type of the instruction, the instruction packet is allocated to a parallel thread of a corresponding category, and the instruction packet is cached in a cache space corresponding to the parallel thread;

[0007] When the instruction packet is retrieved, it is retrieved from the cache space in sequence according to the order in which it is stored, and the instruction packet is parsed to obtain a corresponding function execution signal, and the function execution signal is output.

[0008] In one embodiment, when receiving the instruction packet sent by the host computer, classifying the instructions in the instruction packet includes:

[0009] Receive an instruction packet from a host computer, and determine a communication protocol address of an instruction stored in the instruction packet according to a communication protocol;

[0010] The type of the instruction is determined according to the address segment where the communication protocol address is located.

[0011] In one embodiment, the instruction packets in the cache space are retrieved in sequence according to the order in which they are stored, including:

[0012] If there is an instruction packet being parsed currently, pausing to retrieve the instruction packet from the cache space;

[0013] If no instruction packet is currently parsed, the instruction packet stored first is retrieved from the cache space.

[0014] In one embodiment, parsing the instruction packet to obtain a corresponding function execution signal includes:

[0015] According to the communication protocol, determining the instruction location in the instruction packet where the instruction is stored, extracting the instruction and determining the corresponding communication protocol address;

[0016] The instruction is parsed to determine the type of function corresponding to the instruction, and a corresponding execution signal is generated according to the type of function.

[0017] In one embodiment, after determining the function type corresponding to the instruction, the method further includes:

[0018] Determine the matching type corresponding to the communication protocol address according to the communication protocol address and a preset function matching table;

[0019] If the matching type and the function type are different, the current instruction packet is discarded.

[0020] In one embodiment, after caching the instruction packet into the cache space corresponding to the parallel thread, the method further includes:

[0021] The storage capacity status of the cache space is output to provide debugging information.

[0022] In one embodiment, the communication protocol sets a frame width and an instruction field, and determining the instruction location storing the instruction in the instruction packet according to the communication protocol, extracting the instruction and determining the corresponding communication protocol address includes:

[0023] Taking the frame width as a unit, count and traverse from the packet header of the instruction packet to find the location of the instruction field, so as to obtain the instruction under the instruction field and the communication protocol address where the instruction is located.

[0024] In a second aspect, the present application further provides an instruction classification processing device, comprising:

[0025] A classification module, for classifying instructions in an instruction packet when receiving an instruction packet sent by a host computer;

[0026] A cache module, used for allocating the instruction packets to parallel threads of corresponding categories according to the types of the instructions, and caching the instruction packets in a cache space corresponding to the parallel threads;

[0027] The parsing module is used to sequentially retrieve the instruction packets from the cache space in the order in which they are stored when the instruction packets are retrieved, parse the instruction packets to obtain corresponding function execution signals, and output the function execution signals.

[0028] In a third aspect, the present application further provides a terminal device, comprising a processor and a memory, wherein the memory stores a computer program, and the processor is used to execute the computer program to implement the instruction classification processing method.

[0029] In a fourth aspect, the present application also provides a computer-readable storage medium storing a computer program, which, when executed on a processor, implements the instruction classification processing method.

[0030] The embodiments of the present application have the following beneficial effects:

[0031] The instruction classification processing method of the present application adopts a design of classification instruction buffering and then parsing, which has the ability to immediately process multiple communication instructions in parallel without causing blocking, thereby speeding up the response speed. In addition, the number of classifications can be configured to increase or decrease the ability of parallel lines and the cache space can be user-defined. Therefore, it has the characteristics of compatibility, high fault tolerance, and fast communication rate in electronic equipment systems. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0033] Figure 1 A schematic diagram of a flow chart of an instruction classification processing method according to an embodiment of the present application is shown;

[0034] Figure 2 A data flow diagram of instruction classification processing according to an embodiment of the present application is shown;

[0035] Figure 3 A schematic diagram of the structure of an instruction classification processing device according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0036] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments.

[0037] The components of the embodiments of the present application generally described and shown in the drawings herein may be arranged and designed in various configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application claimed for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present application.

[0038] Hereinafter, the terms "including", "having" and their cognates that can be used in various embodiments of the present application are intended only to indicate specific features, numbers, steps, operations, elements, components or a combination of the foregoing items, and should not be understood as first excluding the existence of one or more other features, numbers, steps, operations, elements, components or a combination of the foregoing items or increasing the possibility of one or more features, numbers, steps, operations, elements, components or a combination of the foregoing items. In addition, the terms "first", "second", "third" and the like are only used to distinguish descriptions and cannot be understood as indicating or implying relative importance.

[0039] Unless otherwise defined, all terms (including technical terms and scientific terms) used herein have the same meanings as those generally understood by those skilled in the art to which the various embodiments of the present application belong. The terms (such as those defined in generally used dictionaries) will be interpreted as having the same meanings as the contextual meanings in the relevant technical field and will not be interpreted as having idealized meanings or overly formal meanings unless clearly defined in the various embodiments of the present application.

[0040] The technical solution of the present application pre-sets classification rules. When the device receives an instruction packet, it can determine the instruction category based on the protocol address where the instruction is stored in the instruction packet. Instructions of different categories are processed and cached through different threads, thereby achieving parallel and cache processing between different instructions and avoiding instruction loss and blocking.

[0041] The method is described below in conjunction with some specific embodiments.

[0042] Example 1

[0043] Figure 1 A flow chart of the instruction classification processing method of an embodiment of the present application is shown. Exemplarily, the instruction classification processing method includes the following steps:

[0044] Step S100, when receiving an instruction packet sent by a host computer, classify the instructions in the instruction packet.

[0045] This embodiment is applied to the scenario of communication between devices or communication between a device and a chip. The method of this embodiment is mainly applied to the processing device at the end receiving the instruction. These processing devices can be various engineering equipment or control equipment and other devices that can process instructions.

[0046] The host computer sends control instructions to the processing device or chip. These control instructions are encapsulated into an instruction packet through the communication protocol and then sent to the corresponding processing device. When the processing device receives the instruction packet, it classifies the instructions carried in it.

[0047] It should be noted that the various instructions in this embodiment have various functions. For each instruction, a communication protocol address will be assigned to it. The protocol address is the address reserved for storing the instruction in the instruction packet. When the control instruction is encapsulated into an instruction packet, it exists in the communication protocol address. Among them, the communication protocol addresses corresponding to instructions classified into the same category will also be divided into the same interval. For example, instruction A and instruction B are both instructions of the same category. The addresses of the two are different, but the addresses assigned to the two instructions are in the same interval.

[0048] In this way, when identifying an instruction packet, the address segment where the communication protocol address is located can be determined according to the communication protocol address of the instruction stored in the instruction packet, so as to determine the type of the instruction.

[0049] The classification of the above instructions is based on whether the instructions are mutually exclusive, or whether they can be executed synchronously. Instructions that cannot be executed synchronously will be classified into the same category. For example, instruction A is to turn on the switch, and instruction B is to turn off the switch. Obviously, a switch cannot be turned on and off at the same time, and cannot be parallel. Therefore, instructions A and B are the same category of instructions. Instruction C is used to control the voltage, so instruction C can be executed synchronously with instructions A and B, so instruction C and instructions A\B are not the same category. When allocating addresses, instruction C will not be in the same address range as instructions A\B.

[0050] It is understandable that the categories here can be completely customized by the user according to the actual working environment, and some instructions that do not exclude each other can be divided into different categories, and those that exclude each other can be divided into the same category. At the same time, considering the large number of instructions, dividing too many categories may have a counterproductive effect. Therefore, some non-exclusive instructions can be classified into the same category to a certain extent. In other words, as long as instructions of different categories can be run in parallel, the specific classification can be flexibly set according to the actual situation. And this setting can be completed through a custom communication protocol.

[0051] The corresponding relationship between the instruction and the protocol address can be preset through the communication protocol to ensure that the upper computer can store the instruction into the specified protocol address according to the corresponding relationship when assembling the package.

[0052] After receiving the instruction packet, the device can preliminarily determine the address range of the storage control instruction through the information carried in the packet (packet parsing operation is not required at this time), and can determine what category the instruction in the received instruction packet is.

[0053] It should be noted that this step only performs a classification operation and does not perform any analysis. Therefore, it can be considered that a classification operation based on the instructions carried by the received instruction packet is performed to facilitate subsequent analysis.

[0054] Step S200, according to the type of the instruction, the instruction packet is allocated to a parallel thread of a corresponding category, and the instruction packet is cached in a cache space corresponding to the parallel thread.

[0055] Based on the aforementioned classification operation, the instruction packet will be assigned to the corresponding parallel thread according to the category of the grid, where the parallel thread is a plurality of threads separated for parallel computing, and each thread corresponds to each instruction category one by one.

[0056] Here, the correspondence between parallel threads and categories can also be pre-designed through the communication protocol. For example, category 1 corresponds to thread 1, and so on. If there are several categories, several threads will be generated, thereby realizing parallel processing of multiple instruction packets.

[0057] After receiving the instruction packet, each parallel thread will cache it. Each parallel thread has a corresponding cache space, so instruction packets of different categories will be stored in the cache space corresponding to the parallel thread respectively, and instruction packets of different categories will not be stored in the same cache space.

[0058] It should be noted that the instructions issued by the upper computer are all issued serially, one after another. This embodiment classifies the instruction packets by category and caches them through each thread to ensure that these instruction packets will not be discarded even if they cannot be parsed at the first time. At the same time, multiple threads are processed in parallel to increase the processing efficiency of the instruction packets.

[0059] Among them, after caching the instruction package, you can also output the storage capacity in the current cache space. Because storage resources are not infinite, outputting the storage capacity as a monitoring and debugging method can effectively locate problems when they occur, and provide a basis for further optimizing the storage space size used by each parallel cache logic.

[0060] For example, in the preset communication protocol, the base frame width of the communication instruction packet, the instruction storage location and the storage space allocated to the instruction, and other related parameters for storing the instruction packet can be set. The number of instruction categories can also be set, so that the corresponding number of communication address segments can be divided according to the number of categories, so as to realize the flexible setting of the storage and classification of the instruction packet. Moreover, for different application scenarios, there will be some unused instructions. These unused instructions can be removed from the protocol and not classified. In this way, there is no need to allocate communication addresses for these unused instructions, thereby saving space.

[0061] Step S300, when the instruction packet is retrieved, it is retrieved from the cache space in sequence according to the order in which it is stored, and the instruction packet is parsed to obtain a corresponding function execution signal, and the function execution signal is output.

[0062] The cache space may store instruction packets in the form of a queue, so that the cached instruction packets may be retrieved in sequence in a first-in-first-out order.

[0063] The purpose of calling the instruction package is to parse it, obtain the instructions and perform the corresponding operations. Each thread can parse only one instruction package at a time. Therefore, if the current parsing is in progress, the instruction package will not be called from the cache space. When an instruction package is parsed and the parsing task is idle, the earliest stored instruction package will be called from the cache space to parse the instruction package. Parsing the instruction package can obtain the instructions in the instruction package, and then the corresponding execution signals can be generated. Outputting these execution signals and matching them with the corresponding execution devices completes the task of the instruction package.

[0064] It is understandable that each thread works in parallel, so each instruction package cached in different cache spaces will be parsed and executed in parallel. Combining the operations of step S100 and step S200, it can be seen that these instruction packages are classified, and instruction packages of different categories are not mutually exclusive and can be executed in parallel, ensuring the execution efficiency of the instructions. And when too many instructions are issued too quickly, these instructions can be pre-cached, so that the issued instructions will not be lost and can be executed in the original order.

[0065] When parsing the instruction packet, a communication protocol address storing the instruction in the instruction packet is determined according to the communication protocol.

[0066] The communication protocol will set the frame width and instruction field of the base frame of the communication protocol. The frame width is the byte width of the base frame, such as 1 bit or 2 bits, and the instruction field is the field name indicating the storage location of the instruction, such as "name" or "order".

[0067] When parsing, start from the header of the instruction packet and traverse in units of frame width, one field at a time. Once the corresponding instruction field is found, the location where the instruction is stored is found, so that the instruction can be obtained from the instruction field. Once the location of the instruction is located, the specific communication protocol address where the instruction is stored can be obtained.

[0068] In the classification of the aforementioned step S100, only the address segment to which the communication protocol address belongs is determined, while this step determines the communication protocol address of the instruction. Because a communication protocol address corresponds to an instruction one-to-one, a matching verification can be performed based on the communication protocol address to determine whether the type of the instruction and the currently classified thread are in a correct correspondence.

[0069] Among them, the correspondence between the types of the above-mentioned instructions and the threads currently classified can be recorded by presetting a function matching table, which is set synchronously when setting the communication protocol. After obtaining the communication protocol address, it can be determined based on the communication protocol address and the preset function matching table whether the instruction is correctly assigned to the current thread. If so, the corresponding execution signal can be generated according to the instruction.

[0070] Specifically, the communication protocol address of the instruction is compared with the address range of the instruction type corresponding to the current thread in the function matching table. If it falls into the range recorded in the function matching table, it means that the match is successful, otherwise the match fails.

[0071] The execution signal is a signal that controls the corresponding execution device to execute the instruction based on the above-mentioned instruction. The execution device is the downstream device that specifically executes the instruction. For example, a switch signal, the switch device that specifically executes the switch action is the selected switch device.

[0072] The execution signal needs to be generated by the processing device that receives the instruction and then sent to the specific execution device. For example, the above instructions are often code instructions that can be directly executed, such as "FF", etc. There is also a one-to-one correspondence between these code instructions and specific execution information. As long as the above matching operation is successful, the instruction can be directly issued, and the instruction can automatically match the corresponding execution signal for output, and then perform the corresponding operation.

[0073] In addition, when parsing instructions, if it is found that the instruction type does not match the current thread, the packet will be discarded directly and the instruction will not be executed. For example, sometimes when testing, the host computer will deliberately send meaningless and wrong instructions. In this case, the instruction will have an incorrect address, and the packet must be discarded. There are also cases where the host computer packet is wrong, and the packet must be discarded at this time to avoid synchronous execution of mutually exclusive instructions, which will cause confusion.

[0074] like Figure 2The figure is a schematic diagram of the processing flow after the instruction is sent from the host computer in this embodiment.

[0075] The host computer sends instructions to the processing device 100, which are instruction packets issued serially. After receiving these instruction packets, the processing device 100 performs classification operations according to the communication protocol and distributes each instruction packet to different threads for parallel processing. Each thread first caches these instructions, and in the order of caching of each instruction, takes out the instruction packets, performs parsing operations in turn, and then sends them to the corresponding execution device.

[0076] The instruction classification processing method of this embodiment adopts the operation of classifying and buffering instructions before parsing, so that multiple instructions can be processed in parallel when processing instructions without causing blocking and instruction loss, thereby accelerating the response speed. In addition, the number of classifications can be configured to increase or decrease the ability of parallel lines and the cache space can be user-defined. Therefore, it has the characteristics of compatibility, high fault tolerance, and fast communication rate in electronic equipment systems.

[0077] Example 2

[0078] like Figure 3 As shown, this embodiment also provides an instruction classification processing device, including:

[0079] The classification module 10 is used to classify the instructions in the instruction package when receiving the instruction package sent by the host computer;

[0080] A cache module 20, configured to allocate the instruction packet to a corresponding type of parallel thread according to the type of the instruction, and cache the instruction packet in a cache space corresponding to the parallel thread;

[0081] The parsing module 30 is used to sequentially retrieve the instruction packets from the cache space in the order in which they are stored when the instruction packets are retrieved, parse the instruction packets to obtain corresponding function execution signals, and output the function execution signals.

[0082] It can be understood that the device of this embodiment corresponds to the method of the above embodiment, and the options in the above embodiment are also applicable to this embodiment, so they will not be described repeatedly here.

[0083] The present application also provides a terminal device, which includes a processor and a memory, wherein the memory stores a computer program, and the processor is used to execute the computer program to implement the instruction classification processing method.

[0084] The terminal device may be a device with computing capabilities such as a control chip, which can receive and parse instructions from a host computer and then transmit them to an execution device, such as a memory with a chip, a solid-state hard drive, a single-chip microcomputer, etc.

[0085] The present application also provides a computer-readable storage medium storing a computer program, which implements the instruction classification processing method when executed on a processor.

[0086] Among them, the processor can be an integrated circuit chip with signal processing capabilities. The processor can be a general-purpose processor, including a central processing unit (CPU), a graphics processing unit (GPU) and a network processor (NP), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or at least one of other programmable logic devices, discrete gates or transistor logic devices, and discrete hardware components. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc., which can implement or execute the disclosed methods, steps and logic block diagrams in the embodiments of the present application.

[0087] The memory may be, but is not limited to, a random access memory (RAM), a read only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), etc. The memory is used to store a computer program, and the processor may execute the computer program accordingly after receiving an execution instruction.

[0088] For example, the computer-readable storage medium may include, but is not limited to, various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0089] In several embodiments provided in the present application, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely schematic. For example, the flowcharts and structure diagrams in the accompanying drawings show the possible architecture, functions and operations of the devices, methods and computer program products according to multiple embodiments of the present application. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of a code, and the module, a program segment or a part of a code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in an alternative implementation, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the structure diagram and / or the flow diagram, and the combination of boxes in the structure diagram and / or the flow diagram, can be implemented with a dedicated hardware-based system that performs a specified function or action, or can be implemented with a combination of dedicated hardware and computer instructions.

[0090] In addition, the functional modules or units in the various embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

[0091] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for a computer device (which can be a smart phone, a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in the various embodiments of the present application.

[0092] The above description is only a specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application.

Claims

1. A method for classifying and processing instructions, characterized in that: include: When receiving an instruction packet sent by a host computer, classifying the instructions in the instruction packet; According to the type of the instruction, the instruction packet is allocated to a parallel thread of a corresponding category, and the instruction packet is cached in a cache space corresponding to the parallel thread; When the instruction packet is retrieved, it is retrieved from the cache space in sequence according to the order in which it is stored, and the instruction packet is parsed to obtain a corresponding function execution signal, and the function execution signal is output.

2. The instruction classification processing method according to claim 1, characterized in that: When receiving the instruction packet sent by the host computer, classifying the instructions in the instruction packet includes: Receive the instruction packet sent by the host computer, and determine the communication protocol address of the instruction stored in the instruction packet according to the communication protocol; The type of the instruction is determined according to the address segment where the communication protocol address is located.

3. The instruction classification processing method according to claim 1, characterized in that: The sequentially retrieving from the cache space in the order of storage includes: If there is an instruction packet being parsed currently, pausing to retrieve the instruction packet from the cache space; If no instruction packet is currently parsed, the instruction packet stored first is retrieved from the cache space.

4. The instruction classification processing method according to claim 1, characterized in that: The step of parsing the instruction packet to obtain a corresponding function execution signal includes: According to the communication protocol, determining the instruction location in the instruction packet where the instruction is stored, extracting the instruction and determining the corresponding communication protocol address; The instruction is parsed to determine the type of function corresponding to the instruction, and a corresponding execution signal is generated according to the type of function.

5. The instruction classification processing method according to claim 4, characterized in that: After determining the function type corresponding to the instruction, the method further includes: Determine the matching type corresponding to the communication protocol address according to the communication protocol address and a preset function matching table; If the matching type and the function type are different, the current instruction packet is discarded.

6. The instruction classification processing method according to claim 1, characterized in that: After caching the instruction packet into the cache space corresponding to the parallel thread, the method further includes: The storage capacity status of the cache space is output to provide debugging information.

7. The instruction classification processing method according to claim 4, characterized in that: The communication protocol sets the frame width and instruction field; The step of determining, according to the communication protocol, the instruction location in the instruction packet where the instruction is stored, extracting the instruction and determining the corresponding communication protocol address comprises: Taking the frame width as a unit, count and traverse from the packet header of the instruction packet to find the location of the instruction field, so as to obtain the instruction under the instruction field and the communication protocol address where the instruction is located.

8. An instruction classification processing device, characterized in that: include: A classification module, for classifying instructions in an instruction packet when receiving an instruction packet sent by a host computer; A cache module, used for allocating the instruction packets to parallel threads of corresponding categories according to the types of the instructions, and caching the instruction packets in a cache space corresponding to the parallel threads; The parsing module is used to sequentially retrieve the instruction packets from the cache space in the order in which they are stored when the instruction packets are retrieved, parse the instruction packets to obtain corresponding function execution signals, and output the function execution signals.

9. A terminal device, characterized in that: The terminal device includes a processor and a memory, the memory stores a computer program, and the processor is used to execute the computer program to implement the instruction classification processing method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: The computer program stores a computer program, which, when executed on a processor, implements the instruction classification processing method according to any one of claims 1 to 7.

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