Pin arrangement method and device, electronic equipment and computer readable medium

Abstract

The invention discloses a pin arrangement method and device, electronic equipment and a computer readable medium, and belongs to the technical field of integrated circuit design, and the method comprises the steps: obtaining a pin fan-out drawing of a peripheral chip; a target routing set meeting a preset rule is determined according to the pin fan-out diagram, the target routing set comprises a plurality of target routing lines, the two ends of each target routing line are the first end and the second end respectively, the first end is used for being connected with one pin of the peripheral chip, and the second end is used for being connected to a target pin on the substrate; according to the position of the second end of each target wire in the reference direction, the arrangement sequence of the multiple target wires in the reference direction is determined; determining the arrangement sequence of each target pin on the substrate in the reference direction according to the arrangement sequence of the plurality of target wires in the reference direction; and determining the positions of the via holes corresponding to the target pins on the substrate based on the arrangement sequence of the target pins in the reference direction. Repeated execution of PCB pre-design can be avoided, and the speed of substrate pin arrangement design is improved.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuit design, and more specifically, to a pin arrangement method, device, electronic device and computer-readable medium. Background Art

[0002] The design of chip substrate pin arrangement is a difficult problem in current large-scale integrated circuit (IC) design. It is not only related to the mapping relationship between wafer signals and substrate pins, but also involves the smoothness of board-level PCB output lines and the number of board-level stacking. However, the design cycle of existing chip substrate pin arrangement methods is long and the development efficiency is low. Summary of the invention

[0003] The present application proposes a pin arrangement method, device, electronic device and computer-readable medium to improve the above-mentioned defects.

[0004] In a first aspect, the present application provides a pin arrangement method, which is applied to a substrate, wherein the substrate is used to be integrated with a wafer package, and the pins on the substrate are used to communicate with a peripheral chip. The method includes: obtaining a pin fan-out diagram of the peripheral chip; determining a target routing set that meets a preset rule according to the pin fan-out diagram, wherein the target routing set includes a plurality of target routings, and each of the target routings has a first end and a second end at both ends, the first end is used to connect to a pin of the peripheral chip, and the second end is used to connect to a target pin on the substrate; determining an arrangement order of the plurality of target routings in the reference direction according to the position of the second end of each of the target routings in the reference direction; determining an arrangement order of each target pin on the substrate in the reference direction according to the arrangement order of the plurality of target routings in the reference direction; and determining a position of a via corresponding to each target pin on the substrate based on the arrangement order of each target pin in the reference direction.

[0005] Optionally, for a possible implementation, determining the position of the via corresponding to each target pin on the substrate based on the arrangement order of each target pin in a reference direction includes: establishing a two-dimensional coordinate system, wherein a unit in the coordinate system is the minimum spacing between the centers of two vias; determining the coordinates of each target pin according to the arrangement order of each target pin in the reference direction, wherein the reference direction is the ordinate direction or the abscissa direction of the coordinate system, and the abscissa and ordinate of each target pin are both integers; and determining the position of the via on the substrate corresponding to each target pin based on the coordinates of each target pin.

[0006] Optionally, for a possible implementation, the peripheral chip is a double-rate synchronous dynamic random access memory, the target pins include data signal pins and control signal pins, and at least one via is spaced between two adjacent data signal pins or control signal pins in the reference direction.

[0007] Optionally, for a possible implementation, after determining the position of the via on the substrate corresponding to each target pin based on the coordinates of each target pin, it also includes: determining that the pin on the wafer corresponding to the target pin is the original pin; determining a temporary routing set according to the position of the via on the substrate corresponding to each target pin and the corresponding original pin, the temporary routing set includes multiple temporary routings, and the two ends of each temporary routing are used to connect the original pin and the corresponding target pin; if the temporary routing set does not meet the conditions, adjust the coordinates of the target pin in the non-reference direction, and return to execute the determination of the position of the via on the substrate corresponding to each target pin based on the coordinates of each target pin and subsequent steps.

[0008] Optionally, for a possible implementation, the peripheral chip is a double-rate synchronous dynamic random access memory, and obtaining the pin fan-out diagram of the peripheral chip includes: obtaining a data sheet of the peripheral chip, the data sheet including the function, signal type, electrical characteristics, and requirements of each pin of the peripheral chip; determining preset requirements based on the data sheet; and fanning out each pin of the peripheral chip based on the preset requirements to obtain a pin fan-out diagram.

[0009] Optionally, for a possible implementation, the pins of the peripheral chip include data signal pins and control signal pins, and the preset requirements include: the data signal pins and the control signal pins are not adjacent to each other, there is a ground hole between each signal pin of the peripheral chip, and the power pins and the ground pins are fanned out to place filter capacitors.

[0010] Optionally, for a possible implementation, the peripheral chip is a double-rate synchronous dynamic random access memory, and the preset rules include: each pin of the peripheral chip is connected to a target routing line, multiple target routing lines do not cross, the target routing line is the shortest in length, the target routing line has a small number of layers and the reference layer is complete.

[0011] In a second aspect, the present application further provides a pin arrangement device, which is applied to a substrate, the substrate is used to be integrated with a wafer package, and the pins on the substrate are used to communicate with a peripheral chip, including: a fan-out unit, used to obtain a pin fan-out diagram of the peripheral chip; a routing design unit, used to determine a target routing set that meets a preset rule according to the pin fan-out diagram, the target routing set including a plurality of target routings, each of which has a first end and a second end at both ends, the first end being used to connect to a pin of the peripheral chip, and the second end being used to connect to a target pin on the substrate; a routing arrangement unit, used to determine an arrangement order of the plurality of target routings in a reference direction according to a position of the second end of each of the target routings in the reference direction; a pin arrangement unit, used to determine an arrangement order of each target pin on the substrate in the reference direction according to the arrangement order of the plurality of target routings in the reference direction; a pin determination unit, used to determine the position of a via corresponding to each target pin on the substrate based on the arrangement order of each target pin in the reference direction.

[0012] In a third aspect, the present application also provides an electronic device, comprising: one or more processors; a memory; one or more applications, wherein the one or more applications are stored in the memory, the one or more applications are configured to be executed by the one or more processors, and the one or more applications are configured to execute the above method.

[0013] In a fourth aspect, the present application further provides a computer-readable storage medium, wherein the computer-readable storage medium stores a program code executable by a processor, and when the program code is executed by the processor, the processor executes the above method.

[0014] The solution provided by the present application is as follows: first, a pin fan-out diagram of the peripheral chip is obtained; then, a target routing set satisfying a preset rule is determined according to the pin fan-out diagram, wherein the target routing set includes a plurality of target routings, and each of the target routings has a first end and a second end, respectively, the first end is used to connect to a pin of the peripheral chip, and the second end is used to connect to a target pin on the substrate; secondly, an arrangement order of the plurality of target routings in the reference direction is determined according to the position of the second end of each of the target routings in the reference direction; an arrangement order of each target pin on the substrate in the reference direction is determined according to the arrangement order of the plurality of target routings in the reference direction; finally, based on the arrangement order of each target pin in the reference direction, the position of the via corresponding to each target pin on the substrate is determined.

[0015] This application determines the pin fan-out diagram through the peripheral chip, and determines the target routing set that meets the preset rules based on the pin fan-out diagram, ensuring that the board-level PCB pre-design between the peripheral chip and the substrate is reasonable, and can avoid the occurrence of unreasonable board-level PCB presets, and then determines the arrangement order of the target routing in the reference direction based on the target routing set, determines the arrangement order of the target pins based on the arrangement order of the target routing, and determines the position of the via corresponding to the target pin on the substrate based on the arrangement order of the target pins in the reference direction. Compared with the prior art method of determining the substrate pin arrangement from the wafer end, this application determines the position of the target pin on the substrate from the peripheral chip end, which can avoid repeated execution of PCB pre-design, improve the speed of substrate pin arrangement design, and thus improve research and development efficiency.

[0016] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or be understood by practicing the present application. The purpose and other advantages of the present application can be realized and obtained by the structures specifically pointed out in the written description, claims, and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0018] Figure 1 A flow chart of a method for arranging pins provided in an embodiment of the present application is shown;

[0019] Figure 2 A method flow chart of a pin arrangement method provided by another embodiment of the present application is shown;

[0020] Figure 3 A method flow chart of a pin arrangement method provided by another embodiment of the present application is shown;

[0021] Figure 4 A method flow chart of a pin arrangement method provided by another embodiment of the present application is shown;

[0022] Figure 5 A method flow chart of a pin arrangement method provided by another embodiment of the present application is shown;

[0023] Figure 6 A flowchart of a pin arrangement method provided by another embodiment of the present application is shown;

[0024] Figure 7 A schematic diagram of a pin fan-out diagram provided by an embodiment of the present application is shown;

[0025] Figure 8 A schematic diagram showing the routing of the target routing provided by an embodiment of the present application on the first layer of the PCB board is shown;

[0026] Fig. 9 A schematic diagram showing the routing of the target routing provided by an embodiment of the present application on the second layer PCB board is shown;

[0027] Fig.10 A schematic diagram showing a wiring diagram of a target wiring provided by an embodiment of the present application arranged on a third layer PCB board;

[0028] Fig.11 A plan view of the first layer PCB board routing provided by an embodiment of the present application is shown;

[0029] Fig.12 A planar schematic diagram of converting each target routing line in the AB coordinate system to the XY coordinate system provided by an embodiment of the present application is shown;

[0030] Fig.13 A schematic plan view of converting target lines in an AB coordinate system to an XY coordinate system is shown in another embodiment of the present application;

[0031] Fig.14 A structural block diagram of an electronic device provided in an embodiment of the present application is shown;

[0032] Fig.15 A structural block diagram of a computer-readable storage medium provided in an embodiment of the present application is shown;

[0033] Fig.16 A structural block diagram of a computer program product provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0034] In order to make those skilled in the art better understand the present application scheme, the technical scheme in the present application embodiment will be clearly and completely described below in conjunction with the drawings in the present application embodiment. Obviously, the described embodiment is only a part of the present application embodiment, rather than all the embodiments. The components of the present application embodiment usually described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the present application for protection, but merely represents the selected embodiment of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present application.

[0035] It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. At the same time, in the description of this application, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0036] The chip substrate pin layout design is a difficult problem in the current large-scale integrated circuit (IC) design. It is not only related to the mapping relationship between the wafer signal and the substrate pin, but also involves the smoothness of the board-level PCB output line and the number of board-level stacking. The existing chip substrate pin layout method mainly uses an EXCEL table to match the wafer signal and the chip substrate pin one by one. After the substrate pin layout design is completed, the board-level PCB pre-design is used to verify whether the substrate pin layout design is reasonable. If it is unreasonable, it will be fed back to the packaging engineer to adjust the substrate pin layout. This method has a long design cycle, involves multiple design changes, occupies more design resources, and has low development efficiency.

[0037] Therefore, in the embodiments of the present application, a pin arrangement method, device, electronic device and computer-readable medium are provided to solve or partially solve the above-mentioned problems.

[0038] See also Figure 1 , which shows a method flow chart of a pin arrangement method provided in an embodiment of the present application, the method is applied to a substrate, the substrate is used to be integrated with the wafer package, the pins on the substrate are used to connect with the peripheral chip, and the method specifically includes steps S110 to S150.

[0039] Step S110: Obtain a pin fan-out diagram of the peripheral chip.

[0040] It should be noted that the wafer is a bare chip with a circuit etched thereon, and the wafer and the substrate are packaged as a whole to form a packaged chip, which can be connected to an external chip to achieve different functions. Among them, the chip packaged by the wafer and the substrate can be a system on chip (System on Chip, SoC), a field-programmable gate array (Field-Programmab le Gate Array, FPGA) or an application-specific integrated circuit (Application-Specific Integrated Circuit, ASIC), which is not specifically limited here.

[0041] The peripheral chip may be a memory chip using double data rate (DDR) technology, such as double data rate synchronous dynamic random access memory (DDR SDRAM), double data rate 2 synchronous dynamic random access memory (DDR2 SDRAM), etc. The peripheral chip may also be a chip using a peripheral component interconnect express (PCIe) interface or a chip using a mobile industry processor interface (MIPI). The type and model of the peripheral chip are not specifically limited here.

[0042] It should be noted that since the pins of the peripheral chip may not match the pads on the PCB, it is difficult to directly connect the peripheral chip to the pads on the PCB. For this reason, it is necessary to fan out the pins of the peripheral chip to obtain a pin fan-out diagram. The pin fan-out diagram includes the label and function of each pin of the peripheral chip, such as the labels and functions of the power, ground, input, output and other pins, as well as the external components or circuit signals to which each pin is connected. For multi-channel components, the pin fan-out diagram also includes the relative position and arrangement of the pins. On the one hand, the pin fan-out diagram can provide a visual representation of the pins of the peripheral chip, clarifying the function and connection target of each pin; on the other hand, the pin fan-out diagram can provide guidance for circuit wiring and PCB design to ensure that the pins of the peripheral chip are correctly connected.

[0043] Specifically, an electronic design automation (EDA) tool may be used to obtain a pin fan-out diagram of a peripheral chip, or the pin fan-out diagram of a peripheral chip may be manually created.

[0044] In an optional embodiment, the data sheet of the peripheral chip can be obtained and preset requirements can be determined based on the data sheet; the pins of the peripheral chip can be fanned out based on the preset requirements to obtain a pin fan-out diagram. For details, please refer to subsequent embodiments.

[0045] Step S120: Determine a target routing set that meets preset rules based on the pin fan-out diagram, the target routing set includes multiple target routings, and each of the target routings has a first end and a second end, the first end is used to connect to a pin of the peripheral chip, and the second end is used to connect to the target pin on the substrate.

[0046] The pin fan-out diagram includes a connection target for each pin in the peripheral chip, and a target routing set that meets a preset rule can be determined based on the pin fan-out diagram. The target routing set includes multiple target routings, and each target routing has a first end and a second end at both ends. The first end is used to connect to a pin of the peripheral chip, and the second end is used to connect to a target pin on the substrate. The pin on the substrate connected to the target routing is the pin corresponding to the target routing.

[0047] The target routing is used to connect the peripheral chip and the substrate on the PCB board. The pins of the peripheral chip can be connected to the target pins on the substrate through the target routing. When the substrate is connected to the wafer signal, the connection between the wafer and the peripheral chip can be realized.

[0048] It should be noted that the peripheral chip can be connected to the substrate by laying out multi-layer PCB board routing. The preset rules can be that the PCB consumables meet the standard requirements, there is no intersection between multiple target routings on the same layer of PCB board, and the length of the target routing is short, the purpose is to save PCB board materials and save costs. There may be multiple routing sets that meet the preset rules, and one can be selected from the multiple routing sets as the target routing set.

[0049] Step S130: determining the arrangement order of the plurality of target routing lines in the reference direction according to the position of the second end of each of the target routing lines in the reference direction.

[0050] After obtaining the pin fan-out diagram of the peripheral chip, a target routing set that meets the preset rules can be designed. At this time, the target pins of the substrate are not determined, so the target pins on the substrate can be determined by the target routing set.

[0051] It can be known that the target routing is deployed based on the pin fan-out diagram, so the target routing is deployed on a two-dimensional image. The second end of each target routing is used to connect to the target pin of the substrate. The arrangement order of the second ends of multiple target routings in the reference direction can be determined according to the position of the second end of each target routing in the reference direction.

[0052] Step S140: determining the arrangement order of the target pins on the substrate in the reference direction according to the arrangement order of the plurality of target routing lines in the reference direction.

[0053] The arrangement order of target pins on the substrate in the reference direction is determined according to the arrangement order of multiple target routing lines in the reference direction, that is, the arrangement order of target pins on the substrate in the reference direction is determined by the target routing lines.

[0054] Specifically, the requirement that the target routing lines in one layer of PCS routing lines cannot cross each other must be met, and for this purpose, the arrangement order of the target pins corresponding to the target routing lines is the same as the arrangement order of the target routing lines.

[0055] Exemplarily, the target routing set includes 4 target routings, namely target routing A, target routing B, target routing C and target routing D. The first end of target routing A is connected to pin A of the peripheral chip, and the second end of target routing A is used to connect to target pin A; the first end of target routing B is connected to pin B of the peripheral chip, and the second end of target routing B is used to connect to target pin B; the first end of target routing C is connected to pin C of the peripheral chip, and the second end of target routing C is used to connect to target pin C; the first end of target routing D is connected to pin D of the peripheral chip, and the second end of target routing D is used to connect to target pin D. The arrangement order of the 4 target routings in the reference direction is: target routing C, target routing B, target routing A and target routing D, then it can be determined that the arrangement order of the target pins in the reference direction is: target pin C, target pin B, target pin A and target pin D.

[0056] Step S150: determining the position of the via hole corresponding to each target pin on the substrate based on the arrangement order of each target pin in the reference direction.

[0057] After determining the arrangement order of the target pins on the substrate in the reference direction, the vias are evenly distributed on the substrate. Therefore, it is necessary to determine the positions of the vias corresponding to each target pin on the substrate, so as to obtain the mapping relationship between the wafer signal and the target pins on the substrate, thereby determining the wiring of the wafer and the substrate and preparing for packaging the wafer.

[0058] It should be noted that the target routing set can be obtained through the known pin fan-out diagram, and the target routing set meets the requirements of PCB pre-design. Therefore, the pin layout design obtained in this application is determined according to the target routing set. When the wafer and the substrate are packaged and the wafer is connected to the peripheral chip, the PCB design of the substrate and the peripheral chip is also reasonable. Therefore, after the substrate pin design of this application is completed, there is no need to perform PCB pre-design, which can greatly shorten the pin layout design cycle.

[0059] An embodiment of the present application provides a pin arrangement method, first, obtaining a pin fan-out diagram of the peripheral chip; then, determining a target routing set that meets a preset rule according to the pin fan-out diagram, the target routing set including a plurality of target routings, each of the target routings having a first end and a second end, the first end being used to connect to a pin of the peripheral chip, and the second end being used to connect to a target pin on the substrate; secondly, determining an arrangement order of the plurality of target routings in the reference direction according to a position of the second end of each of the target routings in the reference direction; determining an arrangement order of each target pin on the substrate in the reference direction according to the arrangement order of the plurality of target routings in the reference direction; finally, determining a position of a via corresponding to each target pin on the substrate based on the arrangement order of each target pin in the reference direction.

[0060] This application determines the pin fan-out diagram through the peripheral chip, and determines the target routing set that meets the preset rules based on the pin fan-out diagram, ensuring that the board-level PCB pre-design between the peripheral chip and the substrate is reasonable, and can avoid the occurrence of unreasonable board-level PCB presets, and then determines the arrangement order of the target routing in the reference direction based on the target routing set, determines the arrangement order of the target pins based on the arrangement order of the target routing, and determines the position of the via corresponding to the target pin on the substrate based on the arrangement order of the target pins in the reference direction. Compared with the prior art method of determining the substrate pin arrangement from the wafer end, this application determines the position of the target pin on the substrate from the peripheral chip end, which can avoid repeated execution of PCB pre-design, improve the speed of substrate pin arrangement design, and thus improve research and development efficiency.

[0061] This application optimizes the substrate pin arrangement in advance, eliminating the intermediate link of board-level PCB pre-design, and shortening the substrate pin arrangement cycle; the substrate pin arrangement method is digitized and visualized, which can adapt to the substrate pin arrangement of different chips. This application has a high degree of freedom in adjusting the substrate pin arrangement, and can take into account both substrate packaging and PCB design.

[0062] See also Figure 2 , which shows a method flow chart of a pin arrangement method provided in an embodiment of the present application, the method is applied to a substrate, the substrate is used to be integrated with the wafer package, the pins on the substrate are used to connect with the peripheral chip, and the method specifically includes steps S210 to S270.

[0063] Step S210: Obtain a pin fan-out diagram of the peripheral chip.

[0064] Step S220: Determine a target routing set that meets preset rules based on the pin fan-out diagram, the target routing set includes multiple target routings, and each of the target routings has a first end and a second end, the first end is used to connect to a pin of the peripheral chip, and the second end is used to connect to the target pin on the substrate.

[0065] Step S230: determining the arrangement order of the plurality of target routing lines in the reference direction according to the position of the second end of each of the target routing lines in the reference direction.

[0066] Step S240: determining the arrangement order of the target pins on the substrate in the reference direction according to the arrangement order of the plurality of target routing lines in the reference direction.

[0067] Among them, step S210 and step S240 have been introduced in detail in the above embodiments and will not be repeated here.

[0068] Step S250: establishing a two-dimensional coordinate system, where one unit in the coordinate system is the minimum distance between the centers of two via holes.

[0069] Since the arrangement order of the target pins represents the arrangement order in the reference direction on the two-dimensional plane, the specific position of the target pins on the substrate is not obtained. Establishing the mapping relationship between the wafer signal and the target pins requires knowing the actual position of the target pins on the substrate.

[0070] To this end, a two-dimensional coordinate system is established, in which one unit is the minimum distance between the centers of two vias, so that the coordinates of the target pins are determined according to the arrangement order of the target pins in the reference direction.

[0071] Step S260: determining the coordinates of each target pin according to the arrangement order of the target pins in the reference direction, wherein the reference direction is the ordinate direction or the abscissa direction of the coordinate system, and the abscissa and ordinate of each target pin are both integers.

[0072] In an optional embodiment, the reference direction may be the vertical coordinate direction in the coordinate system, and the coordinates of each target pin may be determined according to the arrangement order of the target pins in the reference direction, while keeping the arrangement order of each target pin in the vertical coordinate direction unchanged. The horizontal coordinate of each target pin may select an integer within a preset range.

[0073] In an optional embodiment, the reference direction may be the horizontal coordinate direction in the coordinate system, and the coordinates of each target pin may be determined according to the arrangement order of the target pins in the reference direction, while keeping the arrangement order of each target pin in the horizontal coordinate direction unchanged. The vertical coordinate of each target pin may select an integer within a preset range.

[0074] The horizontal and vertical coordinates of the target pins are both integers, that is, the minimum distance between two adjacent target pins is the minimum distance between the centers of two vias. That is, the target pins in the coordinate system can be directly mapped to the vias on the substrate.

[0075] Continuing with the above-mentioned embodiment, the target pins are arranged in the order of: target pin C, target pin B, target pin A and target pin D in the reference direction, and the reference direction is the vertical coordinate. It can be obtained that the coordinates of target pin A, target pin B, target pin C and target pin D are (7, 4), (5, 4), (2, 4), (8, 4) respectively. It can also be obtained that the coordinates of target pin A, target pin B, target pin C and target pin D are (6, 4), (5, 4), (2, 4), (8, 4) respectively. The arrangement order of the four target pins in the mid-coordinate direction is kept the same, that is, the relative size relationship of the vertical coordinates of the four target pins remains unchanged. It can also be obtained that the coordinates of the target pin A, the target pin B, the target pin C and the target pin D are (7, 2), (5, 2), (2, 2, (8, 2) respectively, and the horizontal coordinate of each target pin can select an integer within a preset range. The horizontal coordinate of the target pin can also be adjusted based on the wiring between the wafer and the substrate. For details, please refer to the subsequent embodiments.

[0076] Step S270: determining the position of each target pin corresponding to the via hole on the substrate based on the coordinates of each target pin.

[0077] After obtaining the coordinates of the target pins, it is necessary to match the coordinate system with the position of the substrate to obtain the position of each target pin corresponding to the via hole on the substrate. To this end, it is necessary to determine the position of each target pin corresponding to the via hole on the substrate based on the coordinates of each target pin.

[0078] Specifically, the origin of the coordinate system is mapped to a certain via hole on the substrate, and then the position of the via hole corresponding to each target pin on the substrate can be determined based on the mapping relationship.

[0079] The embodiment of the present application provides a pin arrangement method, which can be based on the pin fan-out diagram of the peripheral chip, obtain a target routing set based on the pin fan-out diagram, determine the arrangement order of the target pins in the reference direction based on the target routing set, and then determine the position of the corresponding via of the target pin on the substrate based on the arrangement order of the target pins. On the one hand, the present application can realize the visual design of the substrate pin arrangement in the form of a pin fan-out diagram, thereby improving the efficiency of the pin arrangement design. On the other hand, the present application limits the arrangement order of each target pin in the reference direction, and each target pin still has a large adjustment space, so the pin arrangement of the substrate is highly variable, which is conducive to the adjustment of the wafer signal to the substrate package.

[0080] Furthermore, the peripheral chip is a double rate synchronous dynamic random access memory, the target pins include data signal pins and control signal pins, and at least one via is spaced between two adjacent data signal pins or control signal pins in the reference direction.

[0081] See also Figure 3 , which shows a method flow chart of a pin arrangement method provided in an embodiment of the present application, the method is applied to a substrate, the substrate is used to be integrated with the wafer package, the pins on the substrate are used to connect with the peripheral chip, and the method specifically includes steps S310 to S3100.

[0082] Step S310: Obtain a pin fan-out diagram of the peripheral chip.

[0083] Step S320: Determine a target routing set that meets preset rules based on the pin fan-out diagram, the target routing set includes multiple target routings, and each of the target routings has a first end and a second end, the first end is used to connect to a pin of the peripheral chip, and the second end is used to connect to the target pin on the substrate.

[0084] Step S330: determining the arrangement order of the plurality of target routing lines in the reference direction according to the position of the second end of each of the target routing lines in the reference direction.

[0085] Step S340: determining the arrangement order of the target pins on the substrate in the reference direction according to the arrangement order of the plurality of target routing lines in the reference direction.

[0086] Step S350: establishing a two-dimensional coordinate system, where one unit in the coordinate system is the minimum distance between the centers of two via holes.

[0087] Step S360: determining the coordinates of each target pin according to the arrangement order of the target pins in the reference direction, wherein the reference direction is the ordinate direction or the abscissa direction of the coordinate system, and the abscissa and ordinate of each target pin are both integers.

[0088] Step S370: determining the position of each target pin corresponding to the via hole on the substrate based on the coordinates of each target pin.

[0089] Among them, step S310 and step S370 have been introduced in detail in the above embodiments and will not be repeated here.

[0090] Step S380: Determine that the pin on the wafer corresponding to the target pin is the original pin.

[0091] It should be noted that the wafer signal is connected to the target pin on the substrate, the wafer is packaged into a chip based on the substrate, the packaged chip is connected to the peripheral chip through the target pin on the substrate, and the pin on the wafer corresponding to the target pin is the original pin.

[0092] Step S390: Determine a temporary routing set according to the position of the via on the substrate corresponding to each target pin and the corresponding original pin, wherein the temporary routing set includes multiple temporary routings, and both ends of each temporary routing are used to connect the original pin and the corresponding target pin.

[0093] The temporary routing set is determined according to the position of the vias on the substrate corresponding to each target pin and the corresponding original pin. The temporary routing set includes multiple temporary routings, and the two ends of each temporary routing are used to connect the original pin and the corresponding target pin. That is, the original pin is connected to the target pin through the temporary routing, and the target pin can be connected to the peripheral chip, that is, the connection between the wafer and the peripheral chip can be realized.

[0094] Step S3100: If the temporary routing set does not meet the conditions, the coordinates of the target pin in the non-reference direction are adjusted, and the process returns to determine the position of each target pin corresponding to the via on the substrate based on the coordinates of each target pin and subsequent steps.

[0095] Among them, the condition can be that the two temporary routing lines do not cross and overlap, and the temporary routing lines can be arranged in layers. When the temporary routing lines do not meet the conditions, it means that there is a contradiction between the pin arrangement of the wafer and the substrate. The coordinates of the target pins in the non-reference direction can be adjusted, and the execution can be returned to determine the position of each target pin corresponding to the via on the substrate based on the coordinates of each target pin and subsequent steps.

[0096] The prior art requires adjustment of the horizontal and vertical coordinates of the pins for adjusting the substrate pin arrangement, and after adjusting the pin coordinates of the substrate, it is also necessary to determine whether the PCB pre-design of the adjusted pin arrangement is reasonable. However, when the temporary routing set does not meet the conditions, the present application only needs to adjust the coordinates of the target pins in the non-reference direction, and fine-tune the substrate pin arrangement. The arrangement order of the target pins on the substrate in the reference direction does not change, and there is no need to determine whether the PCB pre-design is reasonable. Compared with the prior art, the adjustment of the present application is simpler and faster, and the efficiency of the pin arrangement can be improved.

[0097] See also Figure 4 , which shows a method flow chart of a pin arrangement method provided in an embodiment of the present application, the method is applied to a substrate, the substrate is used to be integrated with a wafer package, the pins on the substrate are used to communicate with a peripheral chip, the peripheral chip is a double-rate synchronous dynamic random access memory, and the method specifically includes steps S410 to S470.

[0098] Step S410: Obtain a data sheet of the peripheral chip, wherein the data sheet includes the function, signal type, electrical characteristics and requirements of each pin of the peripheral chip.

[0099] You can obtain a data sheet or specification sheet from the manufacturer of the peripheral chip, which contains the pinout diagram and functional description of the chip. The data sheet includes the function, signal type, electrical characteristics, and requirements of each pin of the peripheral chip.

[0100] Step S420: Determine preset requirements based on the data manual.

[0101] Preset requirements based on each pin's function, signal type, electrical characteristics, and requirements in the data sheet.

[0102] Furthermore, the pins of the peripheral chip include data signal pins and control signal pins, and the preset requirements include: the data signal pins and the control signal pins are not adjacent to each other, there is a ground hole between each signal pin of the peripheral chip, and the power pins and the ground pins are fanned out to place filter capacitors.

[0103] Step S430: Fan out each pin of the peripheral chip based on the preset requirement to obtain a pin fan-out diagram.

[0104] The pins of the peripheral chip are fanned out based on the preset requirements to obtain a pin fan-out graph, that is, the pin fan-out graph meets the preset requirements.

[0105] Step S440: Determine a target routing set that meets preset rules based on the pin fan-out diagram, the target routing set includes multiple target routings, and each of the target routings has a first end and a second end, the first end is used to connect to a pin of the peripheral chip, and the second end is used to connect to the target pin on the substrate.

[0106] Specifically, the peripheral chip is a double-rate synchronous dynamic random access memory, and the preset rules include: each pin of the peripheral chip is connected to a target routing line, multiple target routing lines do not cross, the target routing line is the shortest, the target routing line has a small number of layers and the reference layer is complete.

[0107] Step S450: determining the arrangement order of the plurality of target routing lines in the reference direction according to the position of the second end of each of the target routing lines in the reference direction.

[0108] Step S460: determining the arrangement order of the target pins on the substrate in the reference direction according to the arrangement order of the plurality of target routing lines in the reference direction.

[0109] Step S470: determining the position of the via hole corresponding to each target pin on the substrate based on the arrangement order of each target pin in the reference direction.

[0110] Among them, step S450 and step S470 have been introduced in detail in the above embodiments and will not be repeated here.

[0111] For further information, see Figure 6 , first design the optimal signal routing template on the DDR particle side, and map it to the coordinate system on the DDR particle side. At this time, the signal routing order of the DDR particles is fixed, so the relative position mapped to the AB coordinate system is fixed. For the substrate pin design, the arrangement of the SOC side pins is a two-dimensional plane, so an XY coordinate system can be established. Through the coordinate system conversion, the signal pins of the AB coordinate system are converted to the XY coordinate system, as long as the relationship between the relative positions of the signal pins is consistent. This application only needs to meet the size relationship of the ordinates of the two points in the AB coordinate system. After the coordinate system conversion, the size relationship of the ordinates in the XY coordinate system is consistent, and the pin arrangement of the substrate is correct. Finally, the pin distribution of the coordinate system is mapped to the pin arrangement table, and the substrate pin design of the DDR module can be completed. In addition, this design method has no constraints on the horizontal coordinates of each signal, so the pin arrangement of the substrate is highly variable, which is also conducive to the adjustment of the wafer signal to the substrate package.

[0112] See also Figure 5 , which shows a method flow chart of a pin arrangement method provided in an embodiment of the present application, the method is applied to a substrate, the substrate is used to be packaged as one with a wafer, the pins on the substrate are used to connect with a peripheral chip, the peripheral chip is a DDR synchronous dynamic random access memory, the wafer is a SOC, and the method specifically includes steps S510 to S550.

[0113] Step S510: Design an optimal fan-out solution for DDR particles and obtain a pin fan-out diagram.

[0114] Among them, the pin fan-out diagram is as follows Figure 7As shown, it is necessary to measure whether the fan-out of this part is reasonable from two dimensions. First, try to ensure that the data signal (Data Quick, DQ) or control signal (Command / Address, C / A) of DDR are not adjacent, and there is a ground hole between each signal to ensure the optimal integrity of the DDR signal. Secondly, the power pin and ground pin fan-out can place filter capacitors to ensure the power integrity of DDR particles. Among them, the pin fan-out diagram includes power pins, ground (Ground, GND) pins, clock signal (Clock, CK) pins, C / A pins, DQ pins, bidirectional data control pins (Bi-di rect iona l Data Strobe, DQS) pins, among which the solid circle is the ground hole 11 and the two-color circle is the via 12.

[0115] It should be noted that a pin fan-out diagram can be obtained based on the DDR particles, and the pin fan-out diagram meets the conventional requirements of fan-out.

[0116] Step S520: Design an optimal routing template for DDR particles.

[0117] Taking DDR3 as an example, the board-level PCB design meets the preset rules in two aspects: first, the routing from DDR chip to SOC is smooth and short. Second, the routing from DDR chip to SOC has less stacking and the reference layer is complete. The board-level PCB output line occupies the least PCB stacking, which can reduce the board manufacturing cost.

[0118] According to the above preset rules, the DDR signal can be routed on each signal layer. The optimal routing template is the target routing set that meets the preset rules. The target routing set needs to be laid out on 3 layers of PCB routing, where the first layer of PCB routing is as follows: Figure 8 As shown, the second layer PCB routing is as follows Fig. 9 As shown, the third layer PCB routing is as follows Fig.10 As shown, one end of the target trace 13 is connected to the via 12 on the PCB board, and the other end is used to connect to the target pin on the substrate.

[0119] Arrange the CA and DQ on the same layer from top to bottom, and map the DDR signal routing on the same layer to the DDR pins on the SOC side on the plane diagram. The first routing layer is shown in the plane diagram. Fig.11 As shown. Each letter arranged from top to bottom on the DDR particle side represents a target trace. The large circle on the substrate on the SOC side represents a solder ball, which is used to connect to the pad. The small circle on the substrate represents a via. The via is connected to its corresponding solder ball. The via is connected to the wafer signal. The wafer signal can be connected to the pin of the peripheral chip through the solder ball connected to the via.

[0120] Step S530: Establishing the coordinate system of each signal on the SOC side and the DDR particle side.

[0121] An AB coordinate system is established for each layer of routing, and the coordinates of each target routing in the AB coordinate system are determined according to the arrangement order of the multiple target routings in the longitudinal direction. An XY coordinate system is established, and each target routing in the AB coordinate system is converted to the XY coordinate system to obtain the coordinates of the target pins corresponding to each target routing in the XY coordinate system.

[0122] like Fig.12 As shown, the coordinates of the first layer target trace in the AB coordinate system and the coordinates of the corresponding target pins converted to the XY coordinate system are shown. Among them, the letter "AI" represents the DQ signal, the letters "P" and "N" in the circle represent the DQS signal, and the letter "JM" and the letter "N" in the square represent the C / A signal.

[0123] According to the principle of signal line sequence from top to bottom, Fig.11 The signal "AI" on the DDR particle side is mapped to the AB coordinate system, and it is assumed that there are "1-9" pins corresponding to them on the SOC side to establish an XY coordinate system. Taking the SOC with a 1.0mm pitch BGA package as an example, usually only one single-ended signal or a pair of differential signals are passed between vias. Therefore, on the SOC side, the vertical coordinates of the pin arrangement of each signal differ by at least 1 unit, and the DDR differential pair can be adjacent to the single-ended signal of the DDR. In order to make the signal on the DDR particle side correspond to the pin on the SOC side, ideally, it is only necessary to correspond the DDR signal on the particle side of the AB coordinate system to the DDR pin on the SOC side of the XY coordinate system one by one. For example Fig.12 The "1-9" on the neutral SOC side corresponds to the "AI" on the DDR particle side, and the pin arrangement is regular and orderly.

[0124] Step S540: Convert the coordinate systems of each signal on the SOC side and the DDR particle side.

[0125] First, quantify the signals on the DDR particle side, taking 4 signal lines as an example.

[0126] The coordinates of the DDR signal "A" in the coordinate system AB are (A1, B1).

[0127] The coordinates of the DDR signal "B" in the coordinate system AB are (A2, B2).

[0128] The coordinates of the signal "C" of DDR in the coordinate system AB are (A3, B3).

[0129] The coordinates of the signal "D" of DDR in the coordinate system AB are (A4, B4).

[0130] The following conclusions can be drawn from the signal line sequence: B1>B2>B3>B4, and the sizes of A1, A2, A3, and A4 can be arbitrary.

[0131] Four pins on the SOC side are randomly selected and quantized in XY coordinates.

[0132] The coordinates of the DDR signal "1" in the coordinate system XY are (X1, Y1).

[0133] The coordinates of the DDR signal "2" in the coordinate system XY are (X2, Y2).

[0134] The coordinates of the DDR signal "3" in the coordinate system XY are (X3, Y3).

[0135] The coordinates of the DDR signal "4" in the coordinate system XY are (X4, Y4).

[0136] In order to make the signal routing sequence on the SOC side smooth, it is only necessary to match the "1-4" on the SOC side with the "AD" on the DDR side. Only 4 signals on the SOC side are required to meet the following conditions: Y1>Y2>Y3>Y4, and the sizes of X1, X2, X3, and X4 can be arbitrary.

[0137] In the same way, the coordinate systems of each signal on each layer of routing on the SOC side and the DDR particle side can be transformed to obtain the coordinates of the target pin on the SOC side.

[0138] According to the above conditions, another general pin arrangement diagram of the SOC side can be obtained, such as Fig.13 As shown. It can be seen that in the XY coordinate system, for a single signal, as long as its ordinate meets the above requirements, its abscissa can be translated left or right. Fig.12 The "2" in the XY coordinate system corresponds to the "B" in the AB coordinate system, but in Fig.13 The position of "2" in the figure can be shifted. This method leaves room for signal adjustment of power supply, GND and other layers, and also leaves room for the routing design of wafer signal to substrate.

[0139] It should be noted that each layer of PCB routing can determine the coordinates of a part of the target pins on the substrate. The target pins corresponding to the multi-layer routing can be set in one area of ​​the substrate, or can be set in different areas of the substrate respectively. It can be determined according to the actual situation and needs to meet the requirements of wafer and substrate wiring.

[0140] Step S550: Map the signals of each layer to a pin layout table.

[0141] The signals of all layers are mapped to the SOC side pins, and finally the pins of each layer after mapping are summarized into the substrate pin arrangement table, and the substrate pin arrangement design is completed. The mapping relationship between the wafer signal and the target pin on the substrate can be obtained based on the pin arrangement table.

[0142] See also Fig.14 , which shows a structural block diagram of a test device 600 provided in an embodiment of the present application, wherein the test device 600 includes: a fan-out unit 610, a routing design unit 620, a routing arrangement unit 630, a pin arrangement unit 640 and a pin determination unit 650.

[0143] The fan-out unit 610 is used to obtain a pin fan-out diagram of the peripheral chip.

[0144] Furthermore, the fan-out unit 610 can also be used to obtain a data sheet of the peripheral chip, which includes the function, signal type, electrical characteristics and requirements of each pin of the peripheral chip; determine preset requirements based on the data sheet; and fan out each pin of the peripheral chip based on the preset requirements to obtain a pin fan-out diagram.

[0145] The routing design unit 620 is used to determine a target routing set that meets preset rules based on the pin fan-out diagram, and the target routing set includes multiple target routings, and each of the target routings has a first end and a second end, respectively, the first end is used to connect to a pin of the peripheral chip, and the second end is used to connect to the target pin on the substrate.

[0146] The routing arrangement unit 630 is used to determine the arrangement order of the multiple target routing lines in the reference direction according to the position of the second end of each of the target routing lines in the reference direction.

[0147] The pin arrangement unit 640 is used to determine the arrangement order of each target pin on the substrate in the reference direction according to the arrangement order of the plurality of target routing lines in the reference direction.

[0148] The pin determination unit 650 is used to determine the position of the via hole corresponding to each target pin on the substrate based on the arrangement order of each target pin in the reference direction.

[0149] Furthermore, the pin determination unit 650 can also be used to establish a two-dimensional coordinate system, in which a unit in the coordinate system is the minimum spacing between the centers of two vias; the coordinates of each target pin are determined according to the arrangement order of the target pins in the reference direction, the reference direction is the ordinate direction or the abscissa direction of the coordinate system, and the abscissa and ordinate of each target pin are integers; based on the coordinates of each target pin, the position of each target pin corresponding to the via on the substrate is determined.

[0150] Furthermore, the pin determination unit 650 can also be used to determine that the pin on the wafer corresponding to the target pin is the original pin; determine a temporary routing set based on the position of the via on the substrate corresponding to each target pin and the corresponding original pin, the temporary routing set includes multiple temporary routings, and the two ends of each temporary routing are used to connect the original pin and the corresponding target pin; if the temporary routing set does not meet the conditions, adjust the coordinates of the target pin in the non-reference direction, and return to execute the position of the via on the substrate corresponding to each target pin based on the coordinates of each target pin and subsequent steps.

[0151] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described devices and modules can refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here.

[0152] In several embodiments provided in the present application, the coupling between modules may be electrical, mechanical or other forms of coupling.

[0153] In addition, each functional module in each embodiment of the present application can be integrated into a processing module, or each module can exist physically separately, or two or more modules can be integrated into one module. The above integrated modules can be implemented in the form of hardware or software functional modules.

[0154] Please refer to Fig.15 , which shows a structural block diagram of an electronic device 700 provided in an embodiment of the present application. The electronic device 700 may be a vehicle system, which may be arranged in a vehicle. The electronic device 700 in the present application may include one or more of the following components: a processor 711, a memory 712, and one or more application programs, wherein the processor 711 is electrically connected to the memory 712, and the one or more program configurations are used to execute the methods described in the various embodiments of the aforementioned test method.

[0155] The processor 711 may include one or more processing cores. The processor 711 uses various interfaces and lines to connect various parts of the entire electronic device 700, and executes various functions and processes data of the electronic device 700 by running or executing instructions, programs, code sets or instruction sets stored in the memory 712, and calling data stored in the memory 712. Optionally, the processor 711 can be implemented in at least one hardware form of digital signal processing (DSP), field programmable gate array (FPGA), and programmable logic array (PLA). The processor 711 can integrate one or a combination of a central processing unit (CPU), a graphics processor (GPU), and a modem. Among them, the CPU mainly processes the operating system, user interface, and computer programs; the GPU is responsible for rendering and drawing display content; and the modem is used to process wireless communications. It can be understood that the above-mentioned modem may not be integrated into the processor 711, but may be implemented separately through a communication chip. Specifically, the method described in the above embodiments may be executed by one or more processors 711 .

[0156] For some embodiments, the memory 712 may include a random access memory (RAM) or a read-only memory (ROM). The memory 712 may be used to store instructions, programs, codes, code sets, or instruction sets. The memory 712 may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for implementing at least one function, instructions for implementing the following various method embodiments, etc. The data storage area may also store data created by the electronic device 700 during use, etc.

[0157] Please refer to Fig.16 , which shows a structural block diagram of a computer-readable medium provided in an embodiment of the present application. The computer-readable medium 800 stores program codes, which can be called by a processor to execute the method described in the above method embodiment.

[0158] The computer readable medium 800 can be an electronic memory such as a flash memory, an EEPROM (electrically erasable programmable read-only memory), an EPROM, a hard disk, or a ROM. Optionally, the computer readable medium 800 includes a non-transitory computer-readable storage medium. The computer readable medium 800 has storage space for program code 810 that performs any method step in the above method. These program codes can be read from or written to one or more computer program products. The program code 810 can be compressed, for example, in an appropriate form.

[0159] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A pin arrangement method, characterized in that: The method is applied to a substrate, the substrate is used to be integrated with a wafer package, and the pins on the substrate are used to communicate with a peripheral chip. The method includes: Obtaining a pin fan-out diagram of the peripheral chip; Determine a target routing set that meets a preset rule according to the pin fan-out diagram, wherein the target routing set includes a plurality of target routings, and each of the target routings has a first end and a second end, wherein the first end is used to connect to a pin of the peripheral chip, and the second end is used to connect to a target pin on the substrate; Determining an arrangement order of the plurality of target routing lines in the reference direction according to a position of the second end of each of the target routing lines in the reference direction; Determining an arrangement order of each target pin on the substrate in the reference direction according to an arrangement order of the plurality of target routing lines in the reference direction; Based on the arrangement order of the target pins in the reference direction, the position of the via hole corresponding to each target pin on the substrate is determined.

2. The method according to claim 1, characterized in that The determining the position of the via hole corresponding to each target pin on the substrate based on the arrangement order of each target pin in the reference direction includes: Establishing a two-dimensional coordinate system, wherein one unit in the coordinate system is the minimum spacing between the centers of two via holes; Determine the coordinates of each target pin according to the arrangement order of the target pins in the reference direction, the reference direction is the ordinate direction or the abscissa direction of the coordinate system, and the abscissa and ordinate of each target pin are both integers; The position of each target pin corresponding to the via hole on the substrate is determined based on the coordinates of each target pin.

3. The method according to claim 2, characterized in that The peripheral chip is a double rate synchronous dynamic random access memory, the target pins include data signal pins and control signal pins, and at least one via is spaced between two adjacent data signal pins or control signal pins in the reference direction.

4. The method according to claim 2, characterized in that: After determining the position of each target pin corresponding to the via hole on the substrate based on the coordinates of each target pin, the method further includes: Determining that a pin on the wafer corresponding to the target pin is an original pin; Determine a temporary routing set according to the position of the via hole on the substrate corresponding to each target pin and the original pin corresponding thereto, wherein the temporary routing set includes a plurality of temporary routings, and two ends of each temporary routing are used to connect the original pin and the corresponding target pin; If the temporary routing set does not meet the conditions, the coordinates of the target pins in the non-reference direction are adjusted, and the process returns to executing the steps of determining the position of the via hole on the substrate corresponding to each target pin based on the coordinates of each target pin and subsequent steps.

5. The method according to claim 1, characterized in that The peripheral chip is a double rate synchronous dynamic random access memory, and the step of obtaining a pin fan-out diagram of the peripheral chip includes: Obtaining a data sheet of the peripheral chip, wherein the data sheet includes the function, signal type, electrical characteristics, and requirements of each pin of the peripheral chip; Determining preset requirements based on the data sheet; Each pin of the peripheral chip is fanned out based on the preset requirement to obtain a pin fan-out graph.

6. The method according to claim 5, characterized in that The pins of the peripheral chip include data signal pins and control signal pins. The preset requirements include: the data signal pins are not adjacent to the control signal pins, there is a ground hole between each signal pin of the peripheral chip, and the power pins and the ground pins are fanned out to place filter capacitors.

7. The method according to claim 1, characterized in that The peripheral chip is a double rate synchronous dynamic random access memory, and the preset rules include: each pin of the peripheral chip is connected to a target routing line, multiple target routing lines do not cross, the target routing line has the shortest length, the target routing line has a small number of layers and the reference layer is complete.

8. A pin arrangement device, characterized in that: The device is applied to a substrate, the substrate is used to be integrated with a wafer package, and the pins on the substrate are used to communicate with a peripheral chip, including: A fan-out unit, used to obtain a pin fan-out diagram of the peripheral chip; A routing design unit, configured to determine a target routing set satisfying a preset rule according to the pin fan-out diagram, wherein the target routing set includes a plurality of target routings, and each of the target routings has a first end and a second end, wherein the first end is used to connect to a pin of the peripheral chip, and the second end is used to connect to a target pin on the substrate; A routing arrangement unit, used to determine the arrangement order of the plurality of target routing lines in the reference direction according to the position of the second end of each of the target routing lines in the reference direction; A pin arrangement unit, used to determine the arrangement order of each target pin on the substrate in the reference direction according to the arrangement order of the plurality of target routing lines in the reference direction; The pin determination unit is used to determine the position of the via hole corresponding to each target pin on the substrate based on the arrangement order of each target pin in the reference direction.

9. An electronic device, characterized in that: include: one or more processors; Memory; One or more applications, wherein the one or more applications are stored in the memory, the one or more applications are configured to be executed by the one or more processors, and the one or more applications are configured to execute the method according to any one of claims 1-7.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores program codes, which can be called by a processor to execute the method according to any one of claims 1 to 7.

Images