LDO (Low Dropout Regulator) circuit with pull current and sink current capabilities

Abstract

The invention discloses an LDO (Low Dropout Regulator) circuit with pull current and sink current capabilities, which comprises an input stage module, a current processing module, a power tube module and a compensation module, and is characterized in that the input stage module is used for calculating an error value of a reference voltage and a feedback voltage and converting the error value into an error current; the current processing module is used for carrying out operational amplification on the error current and outputting the error current to the power tube module, the power tube module is composed of two groups of power tubes and respectively provides a pull current and a sink current for an output node, and the compensation module compensates the frequency characteristic of the circuit and realizes stable regulation and control on the output voltage under different load conditions. Compared with a traditional LDO structure, the LDO structure can provide a pull current power supply mode and a sink current power supply mode, and is suitable for wider load scenes; and meanwhile, a Gm driving type error amplifier structure and a symmetric current mirror Miller compensation structure are used, so that compared with a traditional error amplifier, the wide bandwidth is achieved, rapid transient response is achieved, and better performance is achieved.

Description

Technical Field

[0001] The invention belongs to the technical field of analog integrated circuits, and in particular relates to an LDO circuit with both current sourcing and current sinking capabilities. Background Art

[0002] LDO (Low Dropout Linear Regulator) is one of the most common power management chips in today's electronic equipment systems. Its high performance and reliability have become the core of electronic systems. Better driving capability has always been one of the research hotspots and development trends of LDO. The systems of electronic equipment are becoming more and more complex, and the functions are becoming more and more complete. More complex functional modules have led to an increasing overall demand for electrical energy, so the requirements for LDO's load capacity are also getting higher and higher.

[0003] In terms of product application, integrated circuit giants such as Texas Instruments (TI) and Analog Devices (ADI) have achieved many results in the research of low-voltage linear regulators. The TLV767 launched by TI is a large-current load LDO chip with a maximum current load of 1A; the LT1963 chip launched by ADI can output a maximum current of 1.5A; Li Zhongwei's team at Northwestern University has realized an LDO with 2A source and sink current capability to power DDR SDRAM (Double Data Rate Synchronous Dynamic Random-Access Memory); however, the bandwidth of these chips is not large, and there is still room for optimization in transient response performance.

[0004] In terms of academic research, the literature [Lv Wenzhao. Research and Design of High-Reliability Source and Sink Large Current Fast Transient Response LDO [D]. Hunan University, 2021] uses two NMOS power tubes to realize the source and sink current capability of the LDO circuit, which can achieve a maximum output current of 3A. The error amplifier uses a cascode (common source and common gate) structure to obtain sufficient gain, and uses nested Miller compensation to separate the primary and secondary poles to meet stability requirements, so that the LDO can obtain good stability in the load range of 1m~3A; but because it uses a cascode structure, the circuit needs to consume more voltage margin, and the LDO cannot work under low power supply voltage conditions, and has certain requirements for the minimum power supply voltage. The error amplifier in the literature [Huang Chong. Design of a Sink and Source Type High Current Linear Regulator [D]. Xidian University, 2013] uses a two-stage structure. The first stage amplifier uses a folded common source and common gate structure to amplify the voltage signal. The second stage uses an improved push-pull structure to drive two NMOS power tubes to achieve the current source and sink capability of the LDO circuit, which can achieve a maximum output current of 2A. However, due to its low internal pole frequency, a large capacitor cannot be set outside the chip to ensure stability, resulting in poor transient response performance of the LDO when the output current changes. Summary of the invention

[0005] In view of the above, the present invention provides an LDO circuit with both current sourcing and current sinking capabilities, which uses a Gm-driven error amplifier to provide current sourcing and current sinking for a load while achieving a higher bandwidth and improving the transient response characteristics of the circuit.

[0006] An LDO circuit with both current sourcing and current sinking capabilities comprises an input stage module, a current processing module, a power tube module and a compensation module, wherein the input stage module is used to calculate the error between a reference voltage and a feedback voltage (i.e., the output voltage is obtained in the form of unit gain negative feedback) and convert it into an error current; the current processing module is used to perform operational amplification on the error current and then output it to the power tube module; the power tube module is composed of two groups of power tubes, which respectively provide the capabilities of sourcing and sinking current to the output node, and feed back the output voltage to the input stage module; the compensation module uses a symmetrical current mirror Miller compensation structure to compensate for the frequency characteristics of the LDO circuit, so as to achieve stable regulation of the output voltage under different load conditions.

[0007] Further, the input stage module includes a PMOS tube M0, two PNP transistors Q1~Q2, two NPN transistors Q3~Q4, four resistors R1~R4 and two current sources I1~I2, wherein the source of M0 is connected to the power supply voltage, the gate of M0 is externally connected to the bias voltage, the drain of M0 is connected to one end of R1 and one end of R2, the other end of R1 is connected to the emitter of Q1, the other end of R2 is connected to the emitter of Q2, the base of Q1 is connected to the reference voltage, the base of Q2 is connected to the feedback voltage, and the collector of Q1 is connected to the collector of Q3, the base of Q3 and the input end of I1 to generate an error current I Q3 , the collector of Q2 is connected to the collector of Q4, the base of Q4 and the input of I2 to generate an error current I Q4 , the emitter of Q3 is connected to one end of R3, the emitter of Q4 is connected to one end of R4, the other end of R3 is connected to the other end of R4, the output end of I1 and the output end of I2 and are grounded.

[0008] Furthermore, the current processing module includes: The current summing module is used to sum the two error currents I generated by the input stage module. Q3 ,I Q4 The average current signal is obtained after summing and averaging; The current difference module is used to compare the average current signal with the error current I Q3 ,I Q4 Do the difference and get two current signals I2 H and I2 L ; Multi-channel current mirror module, used for current signal I2 H and I2 L Copy and nonlinearly amplify the two current signals I3 H and I3 L .

[0009] Furthermore, the current summing module includes two PMOS tubes M5-M6, two NPN transistors Q5-Q6 and two resistors R5-R6, wherein the source of M5 is connected to the source of M6 and connected to the power supply voltage, the drain of M5 is connected to the gate of M5, the collector of Q5, the drain of M6, the gate of M5 and the collector of Q6 to generate an average current signal, and the base of Q5 is connected to the error current I Q3 , the base of Q6 is connected to the error current I Q4 , the emitter of Q5 is connected to one end of R5, the emitter of Q6 is connected to one end of R6, and the other end of R5 is connected to the other end of R6 and grounded.

[0010] Further, the current difference module includes four PMOS tubes M7~M10, four NPN transistors Q7~Q10 and four resistors R7~R10, wherein the source of M7 is connected to the source of M8, the source of M9 and the source of M10 and connected to the power supply voltage, the gate of M7 is connected to the gate of M8 and connected to the average current signal, and the gate of M9 is connected to the drain of M7, the collector of Q7, the collector of Q9 and the drain of M9 to generate the current signal I2 L , the base of Q7 and the base of Q9 are connected in parallel to the error current I Q3 , the emitter of Q7 is connected to one end of R7, the emitter of Q9 is connected to one end of R9, the gate of M10 is connected to the drain of M8, the collector of Q8, the collector of Q10 and the drain of M10 to generate a current signal I2 H , the base of Q8 and the base of Q10 are connected in parallel to the error current I Q4 , the emitter of Q8 is connected to one end of R8, the emitter of Q10 is connected to one end of R10, the other end of R7 is connected to the other end of R8, the other end of R9 and the other end of R10 and is grounded.

[0011] Furthermore, the multi-channel current mirror module includes six PMOS tubes M11, M12, M17~M20, six NMOS tubes M21, M22, M13~M16 and six resistors R11~R16, wherein the source of M11 is connected to the source of M12, the source of M19, the source of M20, one end of R11 and one end of R12 and connected to the power supply voltage, and the gate of M11 is connected to the current signal I2 L , the other end of R11 is connected to the source of M17, the gate of M17 is connected to the gate of M19 and one end of R13, the other end of R13 is connected to the drain of M17 and the drain of M15, the drain of M19 is connected to the drain of M21 and the gate of M21 to generate a current signal I3 L , the source of M21 is connected to one end of R15, the drain of M11 is connected to the drain of M13, the gate of M13 and the gate of M15, and the gate of M12 is connected to the current signal I2 H , the other end of R12 is connected to the source of M18, the gate of M18 is connected to the gate of M20 and one end of R14, the other end of R14 is connected to the drain of M18 and the drain of M16, the drain of M20 is connected to the drain of M22 and the gate of M22 to generate a current signal I3 H , the source of M22 is connected to one end of R16, the other end of R16 is connected to the output voltage, the drain of M12 is connected to the drain of M14, the gate of M14 and the gate of M16, the source of M16 is connected to the source of M14, the source of M13, the source of M15 and the other end of R15 and is grounded.

[0012] Preferably, the multi-channel current mirror module further includes a dead zone control circuit, which is composed of two bias current sources I5 and I6, the input end of I5 is connected to the drain of M11, the input end of I6 is connected to the drain of M12, and the output end of I5 is connected to the output end of I6 and grounded; by setting a certain dead zone current, it is possible to avoid the high and low side power tubes being turned on at the same time due to current copy deviation.

[0013] Furthermore, the compensation module includes four PMOS tubes M1-M4, two current sources I3-I4 and a capacitor C1, wherein the source of M1 is connected to the source of M2, the source of M3 and the source of M4 and connected to the power supply voltage, the gate of M3 is connected to the gate of M1, the drain of M3 and the input end of I3, and the drain of M1 is connected to the error current I Q3 The gate of M4 is connected to the gate of M2, the drain of M4, one end of C1 and the input end of I4, and the drain of M2 is connected to the error current I Q4 , the other end of C1 is connected to the output voltage, and the output end of I3 is connected to the output end of I4 and grounded.

[0014] Furthermore, the power tube module includes a high-side power tube and a low-side power tube, wherein the gate of the high-side power tube is connected to the current signal I3 H The drain of the high-side power tube is connected to the supply voltage, the source of the high-side power tube is connected to the drain of the low-side power tube and generates an output voltage, and the gate of the low-side power tube is connected to the current signal I3 L , the source of the low-side power tube is grounded.

[0015] Based on the above technical solution, the present invention has the following beneficial technical effects: 1. Strong load capacity: The present invention uses a high-side power tube and a low-side power tube to provide a maximum of 3A of source current and sink current for the load respectively, and has a strong load capacity.

[0016] 2. Fast transient response speed: The present invention uses a Gm-driven error amplifier, the circuit bandwidth is large, and the system has a fast transient response speed.

[0017] 3. Stable output voltage: The non-main pole frequencies inside the circuit of the present invention are relatively high, the phase margin is relatively large, and the rated voltage can be stably output within a wide load range. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 4 is a block diagram of the LDO circuit structure in an embodiment of the present invention.

[0019] Figure 2 Schematic diagram of the LDO core circuit structure in an embodiment of the present invention.

[0020] Figure 3Schematic diagram of the circuit structure of a multi-channel current mirror module and a power tube module in an embodiment of the present invention. DETAILED DESCRIPTION

[0021] In order to describe the present invention more specifically, the technical solution of the present invention is described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0022] like Figure 1 As shown, the LDO circuit with both current sourcing and current sinking capabilities of the present invention comprises an input stage module 1, a current processing module 2, a dead zone control circuit, a power tube module 3 and a compensation module, wherein the input stage module is used to calculate the error value between the reference voltage REFOUT and the feedback voltage VFB and convert it into an error current and input it into the current processing module; the current processing module comprises a current summing module, a high-side current difference module and a low-side current difference module, a high-side multi-channel current mirror module and a low-side multi-channel current mirror module, which are used to calculate and amplify the error current and output it to the power tube module; the dead zone control circuit sets a certain dead zone current to avoid the high and low side power tubes being turned on at the same time; the power tube module consists of two groups of high-side and low-side power tubes, which respectively provide the ability to source and sink current to the output node; the compensation module is used to compensate for the frequency characteristics of the LDO circuit to achieve stable regulation of the output voltage under different load conditions.

[0023] The reference voltage REFOUT is connected to the positive input terminal of the input stage module. The output signal Vo is connected to the negative input terminal of the input stage module by obtaining the feedback voltage VFB in the form of unit gain negative feedback. The positive and negative current output terminals of the input stage are respectively connected to the input terminals of the current summing module and the current difference module in the current processing module. The output terminal of the current summing module is respectively connected to the input terminals of the high-side current difference module and the low-side current difference module. The output terminals of the high-side current difference module and the low-side current difference module are respectively connected to the input terminals of the high-side multi-channel current mirror module and the low-side multi-channel current mirror module. The power tube module is composed of a transconductance amplifier g mH and g mL The actual circuit is two groups of NMOS power tubes. The output of the current processing module and the dead zone control circuit are respectively connected to the input of the power tube module, i.e., the gate of the power tube. The output node of the LDO circuit is connected to the load RL and the capacitor Co with the resistor ESR, and is connected to the inverting input of the input stage in the form of unit gain negative feedback. The compensation module consists of two groups of symmetrical current mirrors g m1 , g m2 and Miller compensation capacitor C1, connected from the output node of the LDO circuit to the output end of the input stage module.

[0024] like Figure 2As shown, the input stage module circuit includes a MOS tube M0, four transistors Q1-Q4, four resistors R1-R4 and two shunt currents I1 and I2. The gate of the MOS tube M0 is connected to the external bias voltage VB, and the drain is connected to the resistors R1 and R2 to provide a tail current for the input stage module; one end of the resistor R1 is connected to the drain of the MOS tube M0, and the other end is connected to the emitter of the transistor Q1 to form a source negative feedback structure; one end of the resistor R2 is connected to the drain of the MOS tube M0, and the other end is connected to the emitter of the transistor Q2 to form a source negative feedback structure; the base of the transistor Q1 is connected to the reference voltage REF, and the collector is connected to the collector of the transistor Q3 and the shunt current I1; the base of the transistor Q2 is connected to the feedback voltage VFB, and the collector is connected to the collector of the transistor Q4 and the shunt current I1; the transistor Q3 uses a diode connection method, the collector is connected to the base, and the emitter is connected to the resistor R3; the transistor Q4 uses a diode connection method, the collector is connected to the base, and the emitter is connected to the resistor R4.

[0025] The compensation module uses a symmetrical current mirror Miller compensation structure. The ratio of MOS tubes M1, M3 and M2, M4 is 4:1, and the fixed current source bias I3 and I4 are equal. The fixed bias voltage generated by the current source I3 at the MOS tube M3 is V3. The current mirrors M1, M3 and M2, M4 are highly symmetrical to ensure the symmetry of the DC static operating point. At the same time, a Miller compensation capacitor C1 is connected across the drain of the MOS tube M4 and the output of the LDO circuit to separate the main pole of the Q4 base and the secondary main pole at the LDO output, so as to achieve high bandwidth and improve transient response performance.

[0026] The current summing module circuit includes two MOS tubes M5 and M6, two transistors Q5 and Q6, and two resistors R5 and R6. Both MOS tubes M5 and M6 are connected by diodes, and the source is connected to the power supply VIN. The gate and drain of MOS tube M5 are connected to the Vx point and to the gate and drain of MOS tube M6, so as to achieve accurate copying of the current of MOS tubes M5 and MOS tubes M6. The collector of transistor Q5 is connected to the drain of MOS tube M5, the emitter is connected to the resistor R5, and the base is connected to the base of transistor Q3 in the input stage module, so as to achieve copying of the current of transistor Q3; the collector of transistor Q6 is connected to the drain of MOS tube M6, the emitter is connected to the resistor R6, and the base is connected to the base of transistor Q4 in the input stage module, so as to achieve copying of the current of transistor Q4.

[0027] The circuit structures of the high-side current difference module and the low-side current difference module are exactly the same, and are respectively connected to the two output ends of the current summing module. The high-side current difference module circuit includes two MOS tubes M8 and M10, two transistors Q8 and Q10, and two resistors R8 and R10; the gate of the MOS tube M8 is connected to the gate of the MOS tube M6 in the current summing structure, and is connected to the gate and drain of the MOS tube M10, and finally connected to the collectors of the transistors Q8 and Q10; the emitters of the transistors Q8 and Q10 are respectively connected to the resistors R8 and R10, and the bases are connected to the base of the transistor Q6 in the current summing circuit to achieve current copying. The low-side current difference module circuit includes two MOS tubes M7 and M9, two transistors Q7 and Q9 and two resistors R7 and R9; the gate of the MOS tube M3 is connected to the gate of the MOS tube M5 in the current summing structure, and is connected to the gate and drain of the MOS tube M9, and finally connected to the collectors of the transistors Q7 and Q9; the emitters of the transistors Q7 and Q9 are connected to the resistors R7 and R9 respectively, and the bases are connected to the base of the transistor Q5 in the current summing circuit to realize current copying.

[0028] like Figure 3As shown, the circuit structures of the high-side multi-channel current mirror module and the low-side multi-channel current mirror module are exactly the same, and are respectively connected to the output ends of the high-side current difference module and the low-side current difference module. The high-side multi-channel current mirror module includes six MOS tubes M12, M14, M16, M18, M20, and M22, three resistors R12, R14, and R16, and a shunt current I6. The gate of the MOS tube M12 is connected to the gate of the high-side current difference module to copy the output current of the high-side current difference module; the drain of the MOS tube M12 is connected to the drain and gate of the MOS tube M14, and is connected to the shunt current I6 and the gate of the MOS tube M12; the drain of the MOS tube M12 The MOS tube M14 is connected to the drain of the MOS tube M14. One end of the resistor R14 is connected to the drain of the MOS tube M12, and the other end is connected to the gates of the MOS tubes M14 and M16. The source of the MOS tube M14 is connected to the resistor R12, so that the MOS tube M16 amplifies the current of the MOS tube M14. The drain of the MOS tube M16 is connected to the gate and drain of the MOS tube M18. The source of the MOS tube M18 is connected to the resistor R16, and the gate is connected to the gate of the high-side power tube MH to amplify the current. The low-side multi-channel current mirror module includes six MOS tubes M11, M13, M15, M17, M19, and M21, three resistors R11, R13, and R15, and a shunt current I5. The gate of the MOS tube M11 is connected to the gate of the low-side current difference module to copy the output current of the low-side current difference module; the drain of the MOS tube M11 is connected to the drain and gate of the MOS tube, and is connected to the shunt current I5 and the gate of the MOS tube M15; the drain of the MOS tube M15 is connected to the gate of the low-side current difference module. The drain of the MOS tube M17 is connected, one end of the resistor R13 is connected to the drain of the MOS tube M15, and the other end is connected to the gates of the MOS tubes M17 and M19; the source of the MOS tube M17 is connected to the resistor R11, so that the MOS tube M19 amplifies the current of the MOS tube M17; the drain of the MOS tube M19 is connected to the gate and drain of the MOS tube M21, the source of the MOS tube M21 is connected to the resistor R15, and the gate is connected to the gate of the low-side power tube ML to amplify the current.

[0029] The dead zone control circuit is composed of two symmetrical fixed bias currents I5 and I6, and a certain dead zone current is set to avoid the high and low side power tubes being turned on at the same time due to current copy deviation.

[0030] The power tube module circuit uses a high-side power tube MH to realize the load's requirement for current sourcing capability, and uses a low-side power tube ML to realize the load's requirement for current sinking capability, so that the LDO circuit has both current sourcing and current sinking capabilities; wherein the drain of the high-side power tube MH is connected to the power tube supply voltage VPOW, and the source is connected to the output node VO of the LDO circuit, the drain of the low-side power tube ML is connected to the output node VO of the LDO circuit, and the source is connected to the ground potential GND.

[0031] like Figure 2 As shown, the LDO circuit is highly symmetrical as a whole and has excellent matching. When the circuit is balanced, the voltages at the positive and negative terminals of the op amp are equal, so the currents flowing through the left and right input pairs of tubes Q1 and Q2 are equal. By adding and subtracting the currents from the current mirrors M1 and M2 and the shunt currents I1 and I2, the currents of the transistor circuit mirrors Q3 and Q4 can be obtained, which are recorded as IQ3 and IQ4 respectively. At the same time, since the transistors Q3~Q10 have the same size and the resistors R3~R10 have the same resistance value, the currents on the transistor current mirrors Q3~Q10 are equal and equal to IQ3. From the KCL law, it can be seen that the currents flowing through the transistors Q5 and Q6 are equal to the currents flowing through the transistors M5 and M6, and M5 and M6 are both diode-connected and gate-connected, so the currents flowing through M5 and M6 are equal and equal to half of the sum of the currents of Q5 and Q6, that is, IQ3. The size ratios of M7 to M5, and M8 to M6 are both 2:1, so the currents flowing through M7 and M8 are both the sum of the currents of Q5 and Q6, 2IQ3, which means the current summing function is realized. According to the KCL law, the currents flowing through M7 and M9 are equal to the currents flowing through Q7 and Q9, and the currents flowing through M8 and M10 are equal to the currents flowing through Q8 and Q10. Therefore, the current flowing through M9 is the sum of the currents of Q7 and Q9 minus the current of M7, and the current flowing through M10 is the sum of the currents of Q8 and Q10 minus the current of M8. The calculation shows that both are zero. At this time, both the high-side power tube and the low-side power tube are turned off, so the static current of the circuit is very small.

[0032] When the circuit is unbalanced, the currents flowing through the input pair Q1 and Q2 are not equal and one current is greater than the other. According to the above derivation, the currents of M7 and M8 are 2IQ3 and 2IQ4 respectively, the currents of Q7 and Q9 are IQ3, the currents of Q8 and Q10 are IQ4, and the currents of M5 and M6 are (IQ3+IQ4) / 2. At this time, it is calculated that the currents on M11 and M12 are zero on one side and non-zero on the other side, the high-side power tube and the low-side power tube are turned off on one side and turned on on the other side, and the two groups of NMOS on the high and low sides are not turned on at the same time, avoiding the waste of current.

[0033] The compensation module is composed of two groups of current mirrors M1, M3 and M2, M4 and a Miller compensation capacitor C1. Different from the traditional Miller compensation that connects the compensation capacitor across the two ends of the operational amplifier, the symmetrical current mirror Miller compensation proposed by the present invention passes through the current mirrors M2 and M4 and then connects back to the output of the input stage module. The feedforward path is eliminated by the current copy effect, and the generation of the right half plane zero point is avoided; at the same time, due to the 4:1 amplification effect of the current copy of M2 and M4, the Miller equivalent capacitance generated by the Miller capacitor C1 at the base of Q4 is 4 times larger than that of the general Miller capacitor. The amplification factor from the output end of the input stage module to the LDO output node VO is Av1, and the equivalent Miller capacitance generated at the output end of the input stage module of the present invention is 4Av1×C1, which has a better compensation effect than the traditional Miller compensation.

[0034] like Figure 3 As shown, the power tubes can be divided into two groups according to their uses: high-side power tubes and low-side power tubes. The high-side power tubes realize the current sourcing capability, and the low-side power tubes realize the current sinking capability.

[0035] Taking the high-side multi-channel current mirror module as an example, when the current on M10 is not zero, the following analysis is performed: at this time, the current on M12 flows to M14 and is shunted away by the shunt current I6. The purpose of the shunt current I6 is to create a "dead zone" for the circuit, so that the current on M10 is not zero only when the current of M8 is greater than a certain threshold, that is, when the circuit is unbalanced, a section is also set to turn off all power tubes. The purpose of setting this dead zone is to avoid the high and low-side power tubes from repeatedly switching on or turning on at the same time due to disturbances or circuit mismatch when the positive and negative input voltages VFB and REFOUT of the error amplifier are close.

[0036] The size ratio of MOS tubes M14 and M16 is 1:6. If the current on M12 is greater than the set threshold, the current on M14 is amplified 6 times and copied to M16. The existence of resistor R12 makes the gate-source voltage of M20 greater than the gate-source voltage of M18, so the current copy between M18 and M20 has an amplifying effect; the amplified current flows into M22, and is amplified again to the current on the high-side power tube MH using the above principle to provide the required current for the load. The analysis of the low-side multi-channel current mirror module is the same as above, and finally the high-side and low-side power tubes are used to realize the current sinking capability of the LDO circuit.

[0037] It is worth noting that, unlike the traditional error amplifier, each node in the error amplifier in the LDO circuit of the present invention is a low-resistance node, the impedance of each node is at the 1 / gm level, and the capacitance of each node is formed by the parasitic capacitance of the device. Therefore, the frequencies of the remaining poles except the primary and secondary poles in the LDO circuit of the present invention are all at higher frequencies, the primary point is set inside the chip through the Miller capacitor, and the secondary primary pole is set at the LDO output. Therefore, the LDO circuit of the present invention can achieve a larger bandwidth without using a complex compensation method, greatly improving the transient response performance of the circuit, and has strong innovation and practicality; at the same time, the present invention uses a Gm-driven error amplifier, which is essentially an amplification of the current signal, and can achieve a larger amplification factor without a cascode structure, and can work at a lower power supply voltage, and there is no high-resistance node in the circuit structure.

[0038] The above description of the embodiments is to facilitate the understanding and application of the present invention by those skilled in the art. It is obvious that those skilled in the art can easily make various modifications to the above embodiments and apply the general principles described herein to other embodiments without creative work. Therefore, the present invention is not limited to the above embodiments. Improvements and modifications made by those skilled in the art to the present invention based on the disclosure of the present invention should be within the protection scope of the present invention.

Claims

1. An LDO circuit having both current sourcing and current sinking capabilities, characterized in that: It includes an input stage module, a current processing module, a power tube module and a compensation module, wherein the input stage module is used to calculate the error between the reference voltage and the feedback voltage and convert it into an error current; the current processing module is used to perform operational amplification on the error current and then output it to the power tube module; the power tube module is composed of two groups of power tubes, which respectively provide the ability to pull current and sink current to the output node, and feed back the output voltage to the input stage module; The compensation module uses a symmetrical current mirror Miller compensation structure to compensate for the frequency characteristics of the LDO circuit, thereby achieving stable regulation of the output voltage under different load conditions.

2. The LDO circuit according to claim 1, characterized in that: The input stage module includes a PMOS tube M0, two PNP transistors Q1~Q2, two NPN transistors Q3~Q4, four resistors R1~R4 and two current sources I1~I2, wherein the source of M0 is connected to the power supply voltage, the gate of M0 is externally connected to the bias voltage, the drain of M0 is connected to one end of R1 and one end of R2, the other end of R1 is connected to the emitter of Q1, the other end of R2 is connected to the emitter of Q2, the base of Q1 is connected to the reference voltage, the base of Q2 is connected to the feedback voltage, and the collector of Q1 is connected to the collector of Q3, the base of Q3 and the input end of I1 to generate an error current I Q3 , the collector of Q2 is connected to the collector of Q4, the base of Q4 and the input of I2 to generate an error current I Q4 , the emitter of Q3 is connected to one end of R3, the emitter of Q4 is connected to one end of R4, the other end of R3 is connected to the other end of R4, the output end of I1 and the output end of I2 and are grounded.

3. The LDO circuit according to claim 2, characterized in that: The current processing module comprises: The current summing module is used to sum the two error currents I generated by the input stage module. Q3 ,I Q4 The average current signal is obtained after summing and averaging; The current difference module is used to compare the average current signal with the error current I Q3 ,I Q4 Do the difference and get two current signals I2 H and I2 L ; Multi-channel current mirror module, used for current signal I2 H and I2 L Copy and nonlinearly amplify the two current signals I3 H and I3 L .

4. The LDO circuit according to claim 3, characterized in that: The current summing module includes two PMOS tubes M5-M6, two NPN transistors Q5-Q6 and two resistors R5-R6, wherein the source of M5 is connected to the source of M6 and connected to the power supply voltage, the drain of M5 is connected to the gate of M5, the collector of Q5, the drain of M6, the gate of M5 and the collector of Q6 to generate an average current signal, and the base of Q5 is connected to the error current I Q3 , the base of Q6 is connected to the error current I Q4 , the emitter of Q5 is connected to one end of R5, the emitter of Q6 is connected to one end of R6, and the other end of R5 is connected to the other end of R6 and grounded.

5. The LDO circuit according to claim 3, characterized in that: The current difference module includes four PMOS tubes M7-M10, four NPN transistors Q7-Q10 and four resistors R7-R10, wherein the source of M7 is connected to the source of M8, the source of M9 and the source of M10 and connected to the power supply voltage, the gate of M7 is connected to the gate of M8 and connected to the average current signal, and the gate of M9 is connected to the drain of M7, the collector of Q7, the collector of Q9 and the drain of M9 to generate the current signal I2 L , the base of Q7 and the base of Q9 are connected in parallel to the error current I Q3 , the emitter of Q7 is connected to one end of R7, the emitter of Q9 is connected to one end of R9, the gate of M10 is connected to the drain of M8, the collector of Q8, the collector of Q10 and the drain of M10 to generate a current signal I2 H , the base of Q8 and the base of Q10 are connected in parallel to the error current I Q4 , the emitter of Q8 is connected to one end of R8, the emitter of Q10 is connected to one end of R10, the other end of R7 is connected to the other end of R8, the other end of R9 and the other end of R10 and is grounded.

6. The LDO circuit according to claim 3, characterized in that: The multi-channel current mirror module includes six PMOS tubes M11, M12, M17~M20, six NMOS tubes M21, M22, M13~M16 and six resistors R11~R16, wherein the source of M11 is connected to the source of M12, the source of M19, the source of M20, one end of R11 and one end of R12 and connected to the power supply voltage, and the gate of M11 is connected to the current signal I2 L , the other end of R11 is connected to the source of M17, the gate of M17 is connected to the gate of M19 and one end of R13, the other end of R13 is connected to the drain of M17 and the drain of M15, the drain of M19 is connected to the drain of M21 and the gate of M21 to generate a current signal I3 L , the source of M21 is connected to one end of R15, the drain of M11 is connected to the drain of M13, the gate of M13 and the gate of M15, and the gate of M12 is connected to the current signal I2 H , the other end of R12 is connected to the source of M18, the gate of M18 is connected to the gate of M20 and one end of R14, the other end of R14 is connected to the drain of M18 and the drain of M16, the drain of M20 is connected to the drain of M22 and the gate of M22 to generate a current signal I3 H , the source of M22 is connected to one end of R16, the other end of R16 is connected to the output voltage, the drain of M12 is connected to the drain of M14, the gate of M14 and the gate of M16, the source of M16 is connected to the source of M14, the source of M13, the source of M15 and the other end of R15 and is grounded.

7. The LDO circuit according to claim 6, characterized in that: The multi-channel current mirror module also includes a dead zone control circuit, which is composed of two bias current sources I5 and I6, the input end of I5 is connected to the drain of M11, the input end of I6 is connected to the drain of M12, and the output end of I5 is connected to the output end of I6 and grounded.

8. The LDO circuit according to claim 2, characterized in that: The compensation module includes four PMOS tubes M1-M4, two current sources I3-I4 and a capacitor C1, wherein the source of M1 is connected to the source of M2, the source of M3 and the source of M4 and connected to the power supply voltage, the gate of M3 is connected to the gate of M1, the drain of M3 and the input end of I3, and the drain of M1 is connected to the error current I Q3 The gate of M4 is connected to the gate of M2, the drain of M4, one end of C1 and the input end of I4, and the drain of M2 is connected to the error current I Q4 , the other end of C1 is connected to the output voltage, and the output end of I3 is connected to the output end of I4 and grounded.

9. The LDO circuit according to claim 3, characterized in that: The power tube module includes a high-side power tube and a low-side power tube, wherein the gate of the high-side power tube is connected to the current signal I3 H The drain of the high-side power tube is connected to the supply voltage, the source of the high-side power tube is connected to the drain of the low-side power tube and generates an output voltage, and the gate of the low-side power tube is connected to the current signal I3 L , the source of the low-side power tube is grounded.

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