Startup method, shutdown method, logic device, server and readable storage medium

Abstract

The invention discloses a startup method, a shutdown method, a logic device, a server and a readable storage medium, the logic device is located in the server, the logic device is in communication connection with a field programmable gate array of the server, and after the server is powered on, the logic device is triggered to be reloaded by firmware; after firmware reloading is completed, a standby component of the server is powered on, and the state of the standby component is monitored; after it is monitored that the field programmable gate array is started, level information is transmitted to the field programmable gate array; and after the standby time sequence control is finished, performing power-on time sequence interaction with the field programmable gate array under the condition of receiving a power-on signal, and performing power-on processing on the processor. The method and the device have the technical effects that the startup action can be realized only by performing the standby time sequence and the power-on time sequence on the logic device and the field programmable logic gate array, and decoupling of the startup and shutdown of the server and the substrate management controller is realized, so that the startup and shutdown of the server are accelerated.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a startup method, a shutdown method, a logic device, a server, and a readable storage medium. Background Art

[0002] At present, in order to meet the diverse computing acceleration needs of global data centers, the MGX server architecture has been proposed. This specification provides a modular reference architecture to manufacture a variety of server models quickly, economically and efficiently.

[0003] NV C2 is the first CPU (processor) model of the MGX (acceleration platform) architecture ARM platform. This processor plays a vital role in the development of the MGX architecture. When designing a server with NV C2, the design on the HPM (Host Processor Module) board is crucial for server manufacturers.

[0004] The public version of the boot topology, on the HPM board, relies on the BMC (Baseboard Management Controller, a controller on the server motherboard used for server management, that is, the baseboard management controller) to control the timing of power on and off.

[0005] Since the server relies on BMC for power on and off, a BMC failure will cause the server to not work properly. In addition, due to the need for BMC to initialize the system and peripherals, when the server is powered on for the first time, it is necessary to wait for the BMC initialization to complete before it is allowed to start, resulting in a long boot waiting time.

[0006] In summary, how to effectively solve the problems of powering on and off the server is a technical problem that technical personnel in this field urgently need to solve. Summary of the invention

[0007] The purpose of this application is to provide a startup method, a shutdown method, a logic device, a server and a readable storage medium to achieve decoupling of server startup and shutdown from BMC, thereby accelerating server startup and shutdown.

[0008] In order to solve the above technical problems, this application provides the following technical solutions:

[0009] A startup method is applied to a logic device, the logic device is located in a server, the logic device has a communication connection with a field programmable gate array of the server, and the method comprises:

[0010] After the server is powered on, a firmware reload is triggered;

[0011] After completing the firmware reloading, powering on the standby component of the server and monitoring the status of the standby component;

[0012] After monitoring that the field programmable gate array is started, transmitting level information to the field programmable gate array so that the field programmable gate array completes a standby timing sequence based on the level information;

[0013] After the standby timing control is completed, in the case of receiving a power-on signal, a power-on timing interaction is performed with the field programmable gate array so that the field programmable gate array controls the processor to power on and start.

[0014] Preferably, the logic device is in communication connection with a baseboard management controller in the server; accordingly, after monitoring the state of the standby component, the method further comprises:

[0015] The status of the standby component is sent to the baseboard management controller.

[0016] Preferably, receiving a power-on signal includes:

[0017] In the case of receiving a power-on command sent after the baseboard management controller is initialized, determining that the power-on signal is received;

[0018] Or, when it is detected that the physical power button is pressed, it is determined that the power-on signal is received.

[0019] Preferably, it also includes:

[0020] Receiving a polling request from the baseboard management controller;

[0021] Feedback register information to the baseboard management controller; the register information includes at least one of status information and alarm information.

[0022] Preferably, the logic device has a parallel communication connection with a field programmable gate array of the server;

[0023] Accordingly, the level information is transmitted to the field programmable gate array, including:

[0024] A level matching the level information is output to the field programmable gate array through the parallel communication connection.

[0025] A shutdown method is applied to a logic device, the logic device is located in a server, the logic device has a communication connection with a field programmable gate array of the server, the method comprising:

[0026] Receive shutdown signal;

[0027] Transmitting the shutdown signal to the field programmable gate array so that the field programmable gate array performs a shutdown operation on the processor;

[0028] Receiving a current shutdown state fed back by the field programmable gate array by connecting to an input / output interface of the field programmable gate array; wherein the current shutdown state corresponds to the processor;

[0029] Determining whether the processor is powered off according to the current power-off state;

[0030] If not, outputting a lower level shutdown signal corresponding to the current shutdown state to the field programmable gate array;

[0031] If yes, the shutdown operation is completed.

[0032] Preferably, according to the current shutdown state, determining whether the processor has been shut down; if not, outputting a lower-level shutdown signal corresponding to the current shutdown state to the field programmable gate array; if yes, completing the shutdown operation, including:

[0033] Transmitting the shutdown signal to the field programmable gate array so that the field programmable gate array performs a shutdown operation on the processor;

[0034] Receiving a current shutdown state fed back by the field programmable gate array by connecting to an input / output interface of the field programmable gate array; wherein the current shutdown state corresponds to the processor;

[0035] According to the current shutdown state, jump to the state of the shutdown state machine;

[0036] After completing the state jump, determining whether the state of the shutdown state machine is the shutdown state;

[0037] If not, outputting a shutdown signal of the next state of the shutdown state machine to the field programmable gate array through the input-output interface;

[0038] If yes, the shutdown operation is completed;

[0039] After determining that the shutdown operation is completed, maintaining standby power supply to the standby component;

[0040] After receiving the power-on signal, sending the power-on signal to the field programmable gate array so that the field programmable gate array performs a power-on operation on the processor;

[0041] Receiving the current power-on state fed back by the field programmable gate array through the input-output interface; wherein the current power-on state corresponds to the processor;

[0042] According to the current power-on state, jump to the state of the power-on state machine;

[0043] After the state jump is completed, determining whether the state of the power-on state machine is the power-on state;

[0044] If not, outputting a power-on signal of the next state of the shutdown state machine to the field programmable gate array through the input-output interface;

[0045] If yes, then confirm that the power-on operation is completed.

[0046] A logic device, the logic device is located in a server, the logic device is in communication connection with a field programmable gate array of the server, and the logic device comprises:

[0047] The firmware loading module is used to trigger firmware reloading after the server is powered on;

[0048] A standby power-on module, used to power on the standby component of the server after completing the firmware reloading, and monitor the status of the standby component;

[0049] A standby timing control module, configured to transmit level information to the field programmable gate array after detecting that the field programmable gate array is started, so that the field programmable gate array completes the standby timing based on the level information;

[0050] The power-on timing control module is used to perform power-on timing interaction with the field programmable gate array after the standby timing control is completed and when a power-on signal is received, so that the field programmable gate array controls the processor to power on and start; after completing the power-on timing interaction, it is determined that the processor has been powered on.

[0051] A server, comprising:

[0052] A field programmable gate array, a baseboard management controller, a processor, and a logic device as claimed in claim 7;

[0053] The thread editable gate array is connected to the logic device, the thread editable gate array is connected to the processor, and the baseboard management controller is connected to the logic device;

[0054] The steps of the power-on method as described above are executed in the logic device, and / or the steps of the power-on method as described above are executed in the logic device.

[0055] A readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of the above-mentioned startup method, and / or, when executed by a processor, implements the steps of the above-mentioned shutdown method.

[0056] A computer program product includes a computer program / instruction. When the computer program / instruction is executed by a processor, the steps of the above-mentioned startup method and / or the steps of the above-mentioned shutdown method are implemented.

[0057] The method provided by the embodiment of the present application is applied in a logic device, the logic device is located in a server, and the logic device has a communication connection with the field programmable gate array of the server. The method includes: after the server is powered on, triggering firmware reloading; after completing the firmware reloading, powering on the standby component of the server and monitoring the status of the standby component; after monitoring that the field programmable gate array is started, transmitting level information to the field programmable gate array so that the field programmable gate array completes the standby timing based on the level information; after the standby timing control is completed, when a power-on signal is received, the power-on timing interaction is performed with the field programmable gate array so that the field programmable gate array controls the processor to power on and start.

[0058] In the present application, after the server is powered on, the firmware reloading of the logic device is initiated first. After the logic device completes the firmware loading, the standby component of the server can be powered on and the status of the standby component can be detected. After monitoring the startup of the field editable logic gate array, a communication connection can be provided to transmit level information to the field programmable gate array, so that the field programmable gate array completes its own standby timing and meets the startup conditions. After determining that the standby timing control is completed, after receiving the power-on signal, the power-on timing interaction can be performed with the field programmable gate array so that the field programmable gate array controls the processor to power on and start. After completing the power-on timing interaction, it can be determined that the processor has been powered on.

[0059] Technical effect of the present application: During the power-on process of the server, without the involvement of the baseboard management controller, the logic device and the field editable logic gate array can perform the standby timing and power-on timing to realize the power-on action, thereby decoupling the server power on and off from the baseboard management controller, thereby accelerating the server power on and off.

[0060] Correspondingly, the embodiments of the present application also provide a shutdown method, a logic device, a server, a readable storage medium and a computer program product corresponding to the above-mentioned startup method, which have the above-mentioned technical effects and are not repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related technologies, the drawings required for use in the embodiments or the related technical descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0062] FIG1 is a flowchart of a method for starting a computer according to an embodiment of the present application;

[0063] FIG2 is a schematic diagram of the structure of a logic device in an embodiment of the present application;

[0064] FIG3 is a schematic diagram of the structure of a server in an embodiment of the present application;

[0065] FIG4 is a schematic diagram of the internal structure of a server;

[0066] FIG5 is a schematic diagram of the internal structure of a server in an embodiment of the present application;

[0067] FIG. 6 is a schematic diagram showing a specific implementation of a startup method in an embodiment of the present application. DETAILED DESCRIPTION

[0068] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below in conjunction with the accompanying drawings and specific implementation methods. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present application.

[0069] Please refer to FIG. 1 , which is a flow chart of a startup method in an embodiment of the present application, which is applied to a logic device (such as a CPLD, Complex Programmable Logic Device), the logic device is located in a server, and the logic device has a communication connection with a field programmable gate array (FPGA, Field Programmable Gate Array) of the server, and the method includes the following steps:

[0070] S101. After the server is powered on, firmware reloading is triggered.

[0071] The CPLD performs firmware reloading, and the firmware to be loaded is stored in the CPLD, so the CPLD can be loaded quickly.

[0072] After the server is powered on, only the BMC and CPLD are powered on, so that the BMC is initialized and the CPLD reloads the FW (firmware). Since the BMC initialization time is long, during the BMC initialization process, the CPLD will be loaded quickly and start to perform logic function control, that is, execute the operation of step S102. This firmware corresponds to the control logic related to the server startup.

[0073] S102: After the firmware reloading is completed, the standby component of the server is powered on, and the status of the standby component is monitored.

[0074] After the CPLD completes the firmware reload, it can power on the standby components of the server, such as FPGA, network port and other devices or chips.

[0075] The CPLD continuously monitors the status of the standby components through GPIO (General-purpose input / output).

[0076] In a specific implementation of the present application, the logic device is in communication with a baseboard management controller in the server; accordingly, after monitoring the status of the standby component, the method further includes:

[0077] Sends the status of the standby component to the baseboard management controller.

[0078] That is, after waiting for BMC to be initialized, the status of the standby component sent by CPLD can be received, so that BMC can monitor the standby component.

[0079] S103 . After monitoring that the field programmable gate array is started, transmit level information to the field programmable gate array so that the field programmable gate array completes a standby sequence based on the level information.

[0080] After detecting that the FPGA is started, the level information corresponding to the standby timing can be transmitted to the FPGA. Based on the level information, the FPGA can complete its own standby timing (STBY timing, or STBY electrical timing).

[0081] In a specific embodiment of the present application, the logic device has a parallel communication connection with a field programmable gate array of the server;

[0082] Accordingly, the level information is transmitted to the field programmable gate array, including:

[0083] Through the parallel communication connection, a level matching the level information is output to the field programmable gate array.

[0084] That is, the CPLD and FPGA signals are directly connected, and after the signal quality is optimized, there is no risk of bit errors and error frames.

[0085] In practical applications, considering the standby timing, it is necessary to make it clear that the previous state has been completed before entering the next state. In practical applications, CPLD can set a standby state machine. That is, after the FPGA is started, the CPLD uses the standby state machine in the logic code to interact with the FPGA through GPIO level control. The FPGA completes its own STBY timing according to the received GPIO level changes. After completion, the FPGA is ready to start.

[0086] S104 , after the standby timing control is completed, upon receiving a power-on signal, a power-on timing interaction is performed with the field programmable gate array so that the field programmable gate array controls the processor to power on and start.

[0087] After the standby timing control is completed, it indicates that the FPGA is ready for power-on and you can just wait to receive the power-on signal.

[0088] After receiving the power-on signal, the power-on timing can be interacted with the FPGA to power on and start the processor.

[0089] For the convenience of control, a power-on state machine can be set up, and the power-on sequence output can be performed based on the power-on state machine. That is, after the CPLD receives the power-on action, it starts to interact with the FPGA through GPIO and starts the CORE power-on sequence (power-on sequence) part. At this time, the FPGA will control the CPU to power on and feed back the startup status information to the CPLD. The CPLD will jump the state machine according to the signal fed back by the FPGA and output the signal required for the lower-level FPGA to control the CPU to power on.

[0090] The CPU may specifically be a processor of model NVIDIA MGX C2.

[0091] In a specific implementation manner of the present application, receiving a power-on signal includes:

[0092] In the case of receiving a power-on command sent after the baseboard management controller is initialized, determining that a power-on signal is received;

[0093] Or, when it is detected that the physical power button is pressed, it is determined that the power-on signal is received.

[0094] That is to say, when the STBY timing control is completed, the CPLD can be informed to start up by pressing the physical power button or by sending a power-on I2C command after the BMC initialization is completed.

[0095] In a specific implementation of the present application, it also includes:

[0096] receiving a polling request from a baseboard management controller;

[0097] Feedback register information to the baseboard management controller; the register information includes at least one of status information and alarm information.

[0098] For ease of description, the above steps are combined for explanation below.

[0099] Due to the rich pin resources of CPLD, the signals of other chip devices on the board can be directly monitored through GPIO, and the status can be judged through logic code. After further integration, it can be reported to BMC through I2C (Inter-Integrated Circut, a serial communication bus), so that BMC can obtain the operating status of the on-board devices, power supply operating status, on / off status, etc. using only a few command frames, thereby improving the out-of-band management efficiency of BMC.

[0100] That is to say, during the boot process, the CPLD constantly monitors the voltage status and network connection status on the HPM board through GPIO. After initialization, the BMC will poll the internal register information of the CPLD through I2C to obtain status information and alarm information for recording Web logs and out-of-band management.

[0101] After completing the power-on sequence interaction, make sure the processor is powered on.

[0102] The method provided by the embodiment of the present application is applied in a logic device, the logic device is located in a server, and the logic device has a communication connection with the field programmable gate array of the server. The method includes: after the server is powered on, triggering firmware reloading; after completing the firmware reloading, powering on the standby component of the server and monitoring the status of the standby component; after monitoring that the field programmable gate array is started, transmitting level information to the field programmable gate array so that the field programmable gate array completes the standby timing based on the level information; after the standby timing control is completed, when a power-on signal is received, the power-on timing interaction is performed with the field programmable gate array so that the field programmable gate array controls the processor to power on and start.

[0103] In the present application, after the server is powered on, the firmware reloading of the logic device is initiated first. After the logic device completes the firmware loading, the standby component of the server can be powered on and the status of the standby component can be detected. After monitoring the startup of the field editable logic gate array, a communication connection can be provided to transmit level information to the field programmable gate array, so that the field programmable gate array completes its own standby timing and meets the startup conditions. After determining that the standby timing control is completed, after receiving the power-on signal, the power-on timing interaction can be performed with the field programmable gate array so that the field programmable gate array controls the processor to power on and start. After completing the power-on timing interaction, it can be determined that the processor has been powered on.

[0104] Technical effect of the present application: During the power-on process of the server, without the involvement of the baseboard management controller, the logic device and the field editable logic gate array can perform the standby timing and power-on timing to realize the power-on action, thereby decoupling the server power on and off from the baseboard management controller, thereby accelerating the server power on and off.

[0105] The present application also provides a shutdown method, which is applied to a logic device (such as a CPLD, Complex Programmable Logic Device), the logic device is located in a server, and the logic device has a communication connection with a field programmable gate array (FPGA, Field Programmable Gate Array) of the server, and the method includes the following steps:

[0106] Receive shutdown signal;

[0107] Transmitting a shutdown signal to the field programmable gate array so that the field programmable gate array performs a shutdown operation on the processor;

[0108] By connecting to the input and output interface of the field programmable gate array, receiving the current shutdown state fed back by the field programmable gate array; wherein the current shutdown state corresponds to the processor;

[0109] Determine whether the processor is powered off based on the current power off status;

[0110] If not, outputting a lower level shutdown signal corresponding to the current shutdown state to the field programmable gate array;

[0111] If yes, then the shutdown operation is determined to be complete.

[0112] For ease of description, the above steps are combined for explanation below.

[0113] When the server is shut down, the operation performed by the CPLD is similar to the startup operation. The shutdown command is sent to the CPLD through a physical button or the BMC through I2C. At this time, the CPLD receives the shutdown signal.

[0114] CPLD transmits the shutdown signal to FPGA through GPIO. FPGA shuts down the processor and informs CPLD of the shutdown status through GPIO. CPLD determines whether the processor has been shut down based on the signal fed back by FPGA. If so, the process ends. If not, the lower-level shutdown signal corresponding to the signal is output, and finally cooperates with FPGA to complete the shutdown operation of the server.

[0115] In a specific implementation of the present application, the shutdown process may further specifically include the following steps:

[0116] Receive shutdown signal;

[0117] Transmitting a shutdown signal to the field programmable gate array so that the field programmable gate array performs a shutdown operation on the processor;

[0118] By connecting to the input and output interface of the field programmable gate array, receiving the current shutdown state fed back by the field programmable gate array; wherein the current shutdown state corresponds to the processor;

[0119] According to the current shutdown state, jump to the state of the shutdown state machine;

[0120] After completing the state jump, determine whether the state of the shutdown state machine is the shutdown state;

[0121] If not, outputting a shutdown signal of the next state of the shutdown state machine to the field programmable gate array through the input and output interface;

[0122] If yes, then confirm that the shutdown operation is completed;

[0123] After determining that the shutdown operation is completed, maintaining standby power supply to the standby component;

[0124] After receiving the power-on signal, sending the power-on signal to the field programmable gate array so that the field programmable gate array performs a power-on operation on the processor;

[0125] Receiving the current power-on state fed back by the field programmable gate array through the input and output interface; wherein the current power-on state corresponds to the processor;

[0126] According to the current power-on status, jump to the state of the power-on state machine;

[0127] After completing the state jump, determine whether the state of the power-on state machine is the power-on state;

[0128] If not, outputting a power-on signal of the next state of the shutdown state machine to the field programmable gate array through the input-output interface;

[0129] If yes, then confirm that the power-on operation is completed.

[0130] For ease of description, the above steps are combined for explanation below.

[0131] When the server is shut down, the control logic is similar. The shutdown command is sent to the CPLD through a physical button or BMC through I2C. The CPLD transmits the shutdown signal to the FPGA through GPIO. The FPGA shuts down the CPU and informs the CPLD of the shutdown status through GPIO. The CPLD jumps to the shutdown state machine according to the signal fed back by the FPGA, outputs the lower-level shutdown signal, and finally cooperates with the FPGA to complete the shutdown operation of the server.

[0132] After shutdown, the CPLD maintains the STBY power supply on the HPM. When it is turned on next time, the previous STBY timing can be skipped for control.

[0133] That is to say, after the shutdown operation is completed, the standby power supply to the standby component continues to be maintained. When the power-on signal is received again, the firmware reloading and the standby timing control of the FPGA power-on preparation can be omitted, and the power-on signal can be directly sent to the FPGA so that the FPGA can power on the processor. The CPLD receives the current power-on status fed back by the FPGA through the input and output interface; wherein the current power-on status corresponds to the processor.

[0134] Then, according to the current power-on state, the state of the power-on state machine is jumped. After the state jump is completed, it is first determined whether the state of the power-on state machine is the power-on state; if not, a power-on signal of the next state of the power-off state machine is output to the FPGA through the input and output interface; if yes, it is determined that the power-on operation is completed.

[0135] Corresponding to the above method embodiment, the embodiment of the present application further provides a logic device, and the logic device described below and the power-on method and power-off method described above can refer to each other.

[0136] As shown in FIG. 2 , the logic device 100 is located in the server, and is in communication connection with the field programmable gate array 200 of the server. The logic device includes the following modules:

[0137] The firmware loading module 101 is used to trigger firmware reloading after the server is powered on;

[0138] The standby power-on module 102 is used to power on the standby component of the server after completing the firmware reloading, and monitor the status of the standby component;

[0139] The standby timing control module 103 is used to transmit level information to the field programmable gate array after monitoring that the field programmable gate array is started, so that the field programmable gate array completes the standby timing based on the level information;

[0140] The power-on sequence control module 104 is used to perform power-on sequence interaction with the field programmable gate array upon receiving a power-on signal after the standby sequence control is completed, so that the field programmable gate array controls the processor to power on and start.

[0141] The logic device provided by the embodiment of the present application is applied, the logic device is located in the server, and the logic device has a communication connection with the field programmable gate array of the server. The method includes: after the server is powered on, triggering firmware reloading; after completing the firmware reloading, powering on the standby component of the server and monitoring the status of the standby component; after monitoring the startup of the field programmable gate array, transmitting level information to the field programmable gate array so that the field programmable gate array completes the standby timing based on the level information; after the standby timing control is completed, when a power-on signal is received, the power-on timing interaction is performed with the field programmable gate array so that the field programmable gate array controls the processor to power on and start.

[0142] In the present application, after the server is powered on, the firmware reloading of the logic device is initiated first. After the logic device completes the firmware loading, the standby component of the server can be powered on and the status of the standby component can be detected. After monitoring the startup of the field editable logic gate array, a communication connection can be provided to transmit level information to the field programmable gate array, so that the field programmable gate array completes its own standby timing and meets the startup conditions. After determining that the standby timing control is completed, after receiving the power-on signal, the power-on timing interaction can be performed with the field programmable gate array so that the field programmable gate array controls the processor to power on and start. After completing the power-on timing interaction, it can be determined that the processor has been powered on.

[0143] Technical effect of the present application: During the power-on process of the server, without the involvement of the baseboard management controller, the logic device and the field editable logic gate array can perform the standby timing and power-on timing to realize the power-on action, thereby decoupling the server power on and off from the baseboard management controller, thereby accelerating the server power on and off.

[0144] In a specific implementation of the present application, the logic device has a communication connection with a baseboard management controller in the server; accordingly, it also includes a status feedback module for monitoring the status of the standby component and then sending the status of the standby component to the baseboard management controller.

[0145] In a specific implementation of the present application, the power-on timing control module is specifically used to determine that a power-on signal is received when receiving a power-on command sent after the baseboard management controller is initialized;

[0146] Or, when it is detected that the physical power button is pressed, it is determined that the power-on signal is received.

[0147] In a specific implementation of the present application, it also includes:

[0148] The information feedback module is used to receive a polling request from a baseboard management controller and to feed back register information to the baseboard management controller; the register information includes at least one of status information and alarm information.

[0149] In a specific implementation of the present application, the logic device may include:

[0150] A shutdown processing module, used for receiving a shutdown signal;

[0151] Transmitting a shutdown signal to the field programmable gate array so that the field programmable gate array performs a shutdown operation on the processor;

[0152] By connecting to the input and output interface of the field programmable gate array, receiving the current shutdown state fed back by the field programmable gate array; wherein the current shutdown state corresponds to the processor;

[0153] Determine whether the processor is powered off based on the current power off status;

[0154] If not, outputting a lower level shutdown signal corresponding to the current shutdown state to the field programmable gate array;

[0155] If yes, then the shutdown operation is determined to be complete.

[0156] In a specific implementation of the present application, it also includes:

[0157] A shutdown processing module, used for receiving a shutdown signal;

[0158] Transmitting a shutdown signal to the field programmable gate array so that the field programmable gate array performs a shutdown operation on the processor;

[0159] By connecting to the input and output interface of the field programmable gate array, receiving the current shutdown state fed back by the field programmable gate array; wherein the current shutdown state corresponds to the processor;

[0160] According to the current shutdown state, jump to the state of the shutdown state machine;

[0161] After completing the state jump, determine whether the state of the shutdown state machine is the shutdown state;

[0162] If not, outputting a shutdown signal of the next state of the shutdown state machine to the field programmable gate array through the input and output interface;

[0163] If yes, then confirm that the shutdown operation is completed;

[0164] After determining that the shutdown operation is completed, maintaining standby power supply to the standby component;

[0165] Accordingly, it also includes:

[0166] The restart module is used to send a power-on signal to the field programmable gate array after receiving the power-on signal, so that the field programmable gate array can perform a power-on operation on the processor;

[0167] Receiving the current power-on state fed back by the field programmable gate array through the input and output interface; wherein the current power-on state corresponds to the processor;

[0168] According to the current power-on status, jump to the state of the power-on state machine;

[0169] After completing the state jump, determine whether the state of the power-on state machine is the power-on state;

[0170] If not, outputting a power-on signal of the next state of the shutdown state machine to the field programmable gate array through the input-output interface;

[0171] If yes, then confirm that the power-on operation is completed.

[0172] In a specific embodiment of the present application, the logic device has a parallel communication connection with a field programmable gate array of the server;

[0173] Correspondingly, the standby power-on module is specifically used to output a level matching the level information to the field programmable gate array through a parallel communication connection.

[0174] Corresponding to the above method embodiment, the embodiment of the present application further provides a server, and the server described below can correspond to the startup method, shutdown method, and logic described above.

[0175] Please refer to Figure 3, the server includes:

[0176] Field programmable gate array 200, baseboard management controller 300, processor 400 and logic device 100 as described above;

[0177] The thread editable gate array is connected to the logic device, the thread editable gate array is connected to the processor, and the baseboard management controller is connected to the logic device;

[0178] The steps of the power-on method described in the above embodiment and / or the steps of the power-off method described in the above embodiment are executed in the logic device. And / or represents at least one of the two.

[0179] To facilitate those skilled in the art to better understand and implement the technical solutions provided in the embodiments of the present application, the following description is given in combination with specific application scenarios and in comparison with related technologies.

[0180] Please refer to Figure 4. On the HPM board, the BMC (Baseboard Management Controller, a controller used for server management on the server motherboard, i.e., the baseboard management controller) needs to be initialized first. After the BMC is initialized, it controls the PCA9555 (input and output expander) through the i2c bus to control the IO (input and output interface) level change to achieve the timing control of the FPGA (Field Programmable Gate Array). According to the timing control, the FPGA interacts with the VR (power controller) to control the power-on / off timing of the server, and the NV C2 module interacts to obtain the power-on / off status. Finally, the FPGA feeds back the NV C2 power-on / off status to the PCA9555 IO, and the BMC obtains the status through i2c (a data bus).

[0181] The above power-on and power-off scheme depends on the active state of the BMC. During the operation of the BMC, it is affected by its own operating system and may be hung, resulting in failure to work properly. The power-on / off timing of the public version is that the BMC controls the level of PCA9555 through i2c, so when the BMC is hung, the power-on and power-off operation cannot be performed. In conventional server design, when the BMC is hung, the power-on / power-off behavior is allowed.

[0182] Due to the need for BMC to initialize the system and peripherals, when the server is powered on for the first time, it is necessary to wait for the BMC initialization to complete before it can be powered on. FPGA starts faster than BMC, so it will take some time to power on during the first power-on phase.

[0183] BMC controls the IO on PCA9555 through I2C to achieve timing control. The I2C communication of BMC needs to control / read the pin status through polling, and the interaction efficiency is low. In addition, I2C communication is a low-speed signal, which has the risk of bit errors.

[0184] From the above embodiments, it can be seen that the power on / off and BMC decoupling can be achieved for the NV C2 platform server motherboard. Specifically, by adding CPLD devices on the basis of the public version design, the power on / off and power on / off timing can be controlled through logic code. The timeliness and stability of the timing control are improved. Finally, the NV C2 module power on / off timing control and BMC decoupling are achieved.

[0185] That is to say, in this application, the timing control form of using BMC to control the PCA9555 port in the public version is abandoned, and the CPLD is added to interact directly with the FPGA, so that the BMC and PFGA have no connection between up / down power and on / off signals. By taking advantage of the stability of the CPLD, it is not easy to get stuck, and the problem of being unable to turn on / off after the BMC gets stuck in the public version design can be effectively avoided. Moreover, the CPLD is directly connected to the FPGA signal, and after the signal quality is optimized, there is no risk of bit errors and error frames. At the same time, the CPLD is a logical parallel processing, without the need for polling operations, and can quickly make logical judgments and feedback on the input signals, thereby improving the efficiency of timing signal interaction.

[0186] Please refer to Figure 5. The PCA9555 chip between the BMC and FPGA is removed from the board and replaced with a CPLD chip. Only non-timing related signals are retained between the BMC and the FPGA, and timing related signals are replaced with direct connection between the CPLD and the FPGA. An I2C bus is added between the CPLD and the BMC. After the BMC is initialized, the timing status information in the CPLD can be read through the I2C bus to achieve the function of obtaining the timing status from the PCA9555 in the public version, that is, this application does not affect its server management function. The interaction between the FPGA backstage and the NV C2 module and VR remains unchanged, maximizing the use of the public version design and reducing development difficulty.

[0187] In addition, CPLD has rich pin resources and can directly monitor the signals of other chip devices on the board through GPIO, and make status judgments through logic codes. After further integration, it can be reported to BMC through I2C, so that BMC can obtain the operating status of on-board devices, power supply operating status, on / off status, etc. using only a few command frames, thereby improving the out-of-band management efficiency of BMC.

[0188] 5 and FIG6 decouple the power-on and power-off solution and the power-on process, the technical solution provided by the present application will be further described through a specific backplane working mode.

[0189] First, after the server is powered on, only the BMC and CPLD chips are powered, so that the BMC is initialized and the CPLD reloads the FW. Because the BMC initialization time is long, during the BMC initialization process, the CPLD will be loaded quickly and start to control the logic function.

[0190] After the CPLD is loaded, it starts to control the STBY power on the HPM board to power on other devices or chips such as the FPGA and network port. The CPLD continuously monitors the status of the chip devices on the board through GPIO. After waiting for the BMC to be initialized, the BMC can obtain management information as soon as possible. After the FPGA is started, the CPLD uses a state machine in the logic code to interact with the FPGA through GPIO level control. The FPGA completes its own STBY timing according to the received GPIO level changes (after completion, the FPGA is ready to start).

[0191] When the STBY timing control is completed, you can inform the CPLD to start the computer by pressing the physical power button or by sending a power-on I2C command after the BMC initialization is completed.

[0192] After receiving the power-on action, CPLD starts to interact with FPGA through GPIO and starts the CORE power-on sequence. At this time, FPGA will control the CPU to power on and feed back the startup status information to CPLD. CPLD will jump the state machine according to the signal fed back by FPGA and output the signal required by the lower-level FPGA to control the CPU to power on. Finally, when the sequence is executed, the CPU completes the power-on action.

[0193] During the boot process, the CPLD monitors the voltage status and network connection status on the HPM board through GPIO. After initialization, the BMC polls the internal register information of the CPLD through I2C to obtain status information and alarm information for recording Web logs and out-of-band management.

[0194] When the server is shut down, the control logic is similar. The shutdown command is sent to the CPLD through a physical button or BMC through I2C. The CPLD transmits the shutdown signal to the FPGA through GPIO. The FPGA shuts down the CPU and informs the CPLD of the shutdown status through GPIO. The CPLD jumps the state machine according to the signal fed back by the FPGA, outputs the lower-level shutdown signal, and finally cooperates with the FPGA to complete the shutdown operation of the server.

[0195] After shutdown, the CPLD maintains the STBY power supply on the HPM. When it is turned on next time, the previous STBY timing can be skipped for control.

[0196] Since the boot sequence is completely controlled by CPLD and does not require BMC participation, the decoupling of boot and BMC can be achieved in this application. The boot sequence of NV C2 can be completed without waiting for BMC initialization to complete. Of course, in the actual application of servers using this design, when the computer room is unattended, the server can still be turned on / off by remote operation after BMC initialization is completed.

[0197] Specifically, after the server is powered on, the logic device can enter the power-on timing after the standby timing control ends, and when the timing ends, the logic device can interact with the field programmable gate array for the power-on timing;

[0198] After completing the power-on sequence interaction, make sure the processor is powered on.

[0199] That is to say, in practical applications, the power-on timing control for the processor can be automatically executed without waiting for external triggers. It is also possible to send a power-on signal to the logic device remotely.

[0200] In summary, this application can effectively improve the problem of power on / off and on / off relying on BMC startup in the NV C2 public version design by adding CPLD as the main timing control, and avoid the situation where the server cannot be turned on and off when the BMC is hung. At the same time, the GPIO of the CPLD is directly connected to the FPGA for control, and GPIO expansion chips such as PCA9555 are no longer used, which eliminates the situation of I2C communication frame transmission errors and improves the stability of timing control. Finally, the decoupling of BMC and NV C2 platform power on / off and on / off is achieved, which not only improves the stability of the system, but also optimizes the BMC polling management process and improves management efficiency.

[0201] Corresponding to the above method embodiment, the embodiment of the present application further provides a readable storage medium. The readable storage medium described below and the power-on method and power-off method described above can refer to each other.

[0202] A readable storage medium stores a computer program, which, when executed by a processor, implements the steps of the power-on method of the above method embodiment, and / or implements the steps of the power-off method of the above method embodiment.

[0203] The readable storage medium may specifically be a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, or other readable storage medium that can store program codes.

[0204] Corresponding to the above method embodiment, the embodiment of the present application further provides a computer program product. The computer program product described below and the startup method and shutdown method described above can be referred to in correspondence with each other.

[0205] A computer program product includes a computer program / instruction. When the computer program / instruction is executed by a processor, the steps of the above-mentioned startup method and / or the steps of the above-mentioned shutdown method are implemented.

[0206] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the logic device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0207] Those skilled in the art may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented with electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in terms of function in the above description. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0208] The steps of the method or algorithm described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0209] Finally, it should be noted that, in this article, relationships such as first and second, etc. are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms include, include or any other variations are intended to cover non-exclusive inclusion, so that a process, method, article or device that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device.

[0210] Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core idea of ​​the present application. At the same time, for those skilled in the art, according to the idea of ​​the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A startup method, characterized in that: Applied to a logic device, the logic device is located in a server, the logic device has a communication connection with a field programmable gate array of the server, the method comprising: After the server is powered on, a firmware reload is triggered; After completing the firmware reloading, powering on the standby component of the server and monitoring the status of the standby component; After monitoring that the field programmable gate array is started, transmitting level information to the field programmable gate array so that the field programmable gate array completes a standby timing sequence based on the level information; After the standby timing control is completed, in the case of receiving a power-on signal, a power-on timing interaction is performed with the field programmable gate array so that the field programmable gate array controls the processor to power on and start.

2. The method according to claim 1, characterized in that: The logic device is in communication with the baseboard management controller in the server; accordingly, after monitoring the state of the standby component, the method further includes: The status of the standby component is sent to the baseboard management controller.

3. The method according to claim 2, characterized in that Receive a power-on signal, including: In the case of receiving a power-on command sent after the baseboard management controller is initialized, determining that the power-on signal is received; Or, when it is detected that the physical power button is pressed, it is determined that the power-on signal is received.

4. The method according to claim 2, characterized in that: Also includes: Receiving a polling request from the baseboard management controller; Feedback register information to the baseboard management controller; the register information includes at least one of status information and alarm information.

5. The method according to any one of claims 1 to 4, characterized in that: The logic device has a parallel communication connection with a field programmable gate array of the server; Accordingly, the level information is transmitted to the field programmable gate array, including: A level matching the level information is output to the field programmable gate array through the parallel communication connection.

6. A shutdown method, characterized in that: Applied to a logic device, the logic device is located in a server, the logic device has a communication connection with a field programmable gate array of the server, the method comprising: Receive shutdown signal; Transmitting the shutdown signal to the field programmable gate array so that the field programmable gate array performs a shutdown operation on the processor; Receiving a current shutdown state fed back by the field programmable gate array by connecting to an input / output interface of the field programmable gate array; wherein the current shutdown state corresponds to the processor; Determining whether the processor is powered off according to the current power-off state; If not, outputting a lower level shutdown signal corresponding to the current shutdown state to the field programmable gate array; If yes, the shutdown operation is completed.

7. The method according to claim 6, characterized in that Determining whether the processor has been shut down according to the current shutdown state; if not, outputting a lower-level shutdown signal corresponding to the current shutdown state to the field programmable gate array; If yes, complete the shutdown process, including: Transmitting the shutdown signal to the field programmable gate array so that the field programmable gate array performs a shutdown operation on the processor; Receiving a current shutdown state fed back by the field programmable gate array by connecting to an input / output interface of the field programmable gate array; wherein the current shutdown state corresponds to the processor; According to the current shutdown state, jump to the state of the shutdown state machine; After completing the state jump, determining whether the state of the shutdown state machine is the shutdown state; If not, outputting a shutdown signal of the next state of the shutdown state machine to the field programmable gate array through the input-output interface; If yes, the shutdown operation is completed; After determining that the shutdown operation is completed, maintaining standby power supply to the standby component; After receiving the power-on signal, sending the power-on signal to the field programmable gate array so that the field programmable gate array performs a power-on operation on the processor; Receiving the current power-on state fed back by the field programmable gate array through the input-output interface; wherein the current power-on state corresponds to the processor; According to the current power-on state, jump to the state of the power-on state machine; After the state jump is completed, determining whether the state of the power-on state machine is the power-on state; If not, outputting a power-on signal of the next state of the shutdown state machine to the field programmable gate array through the input-output interface; If yes, then confirm that the power-on operation is completed.

8. A logic device, characterized in that: The logic device is located in the server, the logic device is in communication connection with the field programmable gate array of the server, and the logic device includes: The firmware loading module is used to trigger firmware reloading after the server is powered on; A standby power-on module, used to power on the standby component of the server after completing the firmware reloading, and monitor the status of the standby component; A standby timing control module, configured to transmit level information to the field programmable gate array after detecting that the field programmable gate array is started, so that the field programmable gate array completes the standby timing based on the level information; The power-on timing control module is used to perform power-on timing interaction with the field programmable gate array after the standby timing control is completed and when a power-on signal is received, so that the field programmable gate array controls the processor to power on and start; after completing the power-on timing interaction, it is determined that the processor has been powered on.

9. A server, characterized in that: include: A field programmable gate array, a baseboard management controller, a processor, and a logic device as claimed in claim 7; The thread editable gate array is connected to the logic device, the thread editable gate array is connected to the processor, and the baseboard management controller is connected to the logic device; The steps of the power-on method according to any one of claims 1 to 5 are executed in the logic unit, and / or the steps of the power-on method according to claim 6 or 7 are executed in the logic unit.

10. A readable storage medium, characterized in that: The readable storage medium stores a computer program, which, when executed by a processor, implements the steps of the startup method as described in any one of claims 1 to 5, and / or, when executed by a processor, implements the steps of the shutdown method as described in claim 6 or 7.

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